-
Notifications
You must be signed in to change notification settings - Fork 2
/
watchdog.c
183 lines (159 loc) · 4.58 KB
/
watchdog.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
/* Emulator for LEGO RCX Brick, Copyright (C) 2003 Jochen Hoenicke.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; see the file COPYING.LESSER. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*
* $Id: watchdog.c 83 2004-05-13 11:52:49Z hoenicke $
*/
#include "h8300.h"
#include "memory.h"
#include "peripherals.h"
#include <netinet/in.h> /* for htonx/ntohx */
//#define DEBUG_WDOG
//#define VERBOSE_WDOG
#define TCSR_OVF 0x80
#define TCSR_WTIT 0x40
#define TCSR_TME 0x20
#define TCSR_RST 0x08
#define TCSR_CKS2 0x04
#define TCSR_CKS1 0x02
#define TCSR_CKS0 0x01
static uint8 tcsr, readtcsr, tcnt, pw;
static cycle_count_t last_cycles;
static uint8 freq[8] = { 1, 5, 6, 7, 8, 9, 11, 12 };
/* Hook to add ftoa/b listeners */
#define SET_FTOA(v) do {} while(0)
#define SET_FTOB(v) do {} while(0)
typedef struct {
cycle_count_t last_cycles;
uint8 tcsr, readtcsr, tcnt, pw;
} wdog_save_type;
static int wdog_save(void *buffer, int maxlen) {
wdog_save_type *data = buffer;
data->last_cycles = htonl(last_cycles);
data->tcsr = tcsr;
data->readtcsr = readtcsr;
data->tcnt = tcnt;
data->pw = pw;
return sizeof(wdog_save_type);
}
static void wdog_load(void *buffer, int len) {
wdog_save_type *data = buffer;
last_cycles = htonl(data->last_cycles);
tcsr = data->tcsr;
readtcsr = data->readtcsr;
tcnt = data->tcnt;
pw = data->pw;
}
static void wdog_reset() {
tcnt = pw = 0;
readtcsr = tcsr = 0x10;
last_cycles = cycles;
}
static void wdog_check_next_cycle() {
if (tcsr & TCSR_TME) {
cycle_count_t next_cycle = last_cycles + ((0x100 - tcnt) << freq[tcsr & 7]);
if (next_cycle < next_nmi_cycle) {
next_nmi_cycle = next_cycle;
}
if (next_cycle < next_timer_cycle) {
next_timer_cycle = next_cycle;
}
}
}
static void wdog_update_time() {
if (tcsr & TCSR_TME) {
int incr = (cycles - last_cycles) >> freq[tcsr & 7];
if (incr < 0) {
wdog_check_next_cycle();
return;
}
last_cycles += incr << freq[tcsr & 7];
//printf("Update time %d for %d\n", nr, incr);
if (tcnt + incr > 0xff) {
tcsr |= TCSR_OVF;
if (tcsr & TCSR_WTIT) {
/* calculate cycle where interrupt was fired and add 518 */
/* 518 is from the processor spec */
last_cycles -= ((tcnt + incr - 0x100) << freq[tcsr & 7]);
last_cycles += 518;
incr = 0;
tcnt = 0;
}
}
#ifdef DEBUG_WDOG
printf("wdog_update_time tcnt: %04x incr: %04x tcsr: %02x\n",
tcnt, incr, tcsr);
#endif
tcnt += incr;
wdog_check_next_cycle();
}
}
static int wdog_check_irq() {
if (tcsr & TCSR_OVF) {
tcsr &= ~TCSR_OVF;
if (tcsr & TCSR_RST) {
next_nmi_cycle = last_cycles;
return 0;
} else {
return 3;
}
}
return 255;
}
static void set_pw(uint8 val) {
pw = val;
}
static void set_val(uint8 val) {
if (pw == 0xa5) {
wdog_update_time();
val |= 0x10;
val |= (0x80 & ~readtcsr);
val &= (0x7f | tcsr);
#ifdef VERBOSE_WDOG
printf("watchdog.c: set_TCSR(%02x)\n", val);
#endif
tcsr = val;
last_cycles = cycles;
} else if (pw == 0x5a) {
wdog_update_time();
tcnt = val;
last_cycles = cycles;
} else
return;
pw = 0;
wdog_check_next_cycle();
}
static uint8 get_TCSR(void) {
return readtcsr = tcsr;
}
static uint8 get_TCNT(void) {
return tcnt;
}
static peripheral_ops watchdog = {
id: 'W',
reset: wdog_reset,
update_time: wdog_update_time,
check_irq: wdog_check_irq,
save_data: wdog_save,
load_data: wdog_load
};
void wdog_init() {
port[0xA8-0x88].set = set_pw;
port[0xA8-0x88].get = get_TCSR;
port[0xA9-0x88].set = set_val;
port[0xA9-0x88].get = get_TCNT;
register_peripheral(watchdog);
wdog_reset();
}