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Ultra96-IO-Mezzanine.kicad_pcb
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Ultra96-IO-Mezzanine.kicad_pcb
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(kicad_pcb (version 20171130) (host pcbnew 5.1.6-c6e7f7d~86~ubuntu20.04.1)
(general
(thickness 1.6)
(drawings 11)
(tracks 0)
(zones 0)
(modules 6)
(nets 37)
)
(page A4)
(title_block
(title "96Boards Mezzanine Project Template")
(date 2015-08-08)
(rev A)
(company "Linaro Ltd")
)
(layers
(0 F.Cu signal)
(31 B.Cu signal hide)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user hide)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user hide)
(48 B.Fab user hide)
(49 F.Fab user)
)
(setup
(last_trace_width 0.254)
(user_trace_width 0.254)
(user_trace_width 0.381)
(user_trace_width 0.635)
(trace_clearance 0.1778)
(zone_clearance 0.508)
(zone_45_only yes)
(trace_min 0.1778)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.1)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 3 3)
(pad_drill 2.5)
(pad_to_mask_clearance 0)
(aux_axis_origin 100 100)
(grid_origin 100 100)
(visible_elements FFFFFF7B)
(pcbplotparams
(layerselection 0x010ef_80000001)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "gerbers/"))
)
(net 0 "")
(net 1 +1V8)
(net 2 GND)
(net 3 +5V)
(net 4 I2C0_SCL)
(net 5 I2C0_SDA)
(net 6 I2C1_SCL)
(net 7 I2C1_SDA)
(net 8 PWR_BTN_N)
(net 9 RST_BTN_N)
(net 10 SYS_DCIN)
(net 11 GPIO_B)
(net 12 GPIO_A)
(net 13 SPIO_SCL)
(net 14 SPIO_DIN)
(net 15 SPIO_CS)
(net 16 SPIO_DOUT)
(net 17 PCM_FS)
(net 18 PCM_CLK)
(net 19 PCM_DO)
(net 20 PCM_DI)
(net 21 GPIO_D)
(net 22 GPIO_F)
(net 23 GPIO_H)
(net 24 GPIO_J)
(net 25 GPIO_L)
(net 26 UART1_TX)
(net 27 UART1_RX)
(net 28 GPIO_C)
(net 29 GPIO_E)
(net 30 GPIO_G)
(net 31 GPIO_I)
(net 32 GPIO_K)
(net 33 UART0_CTS)
(net 34 UART0_TX)
(net 35 UART0_RX)
(net 36 UART0_RTS)
(net_class Default "This is the default net class."
(clearance 0.1778)
(trace_width 0.254)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net GPIO_A)
(add_net GPIO_B)
(add_net GPIO_C)
(add_net GPIO_D)
(add_net GPIO_E)
(add_net GPIO_F)
(add_net GPIO_G)
(add_net GPIO_H)
(add_net GPIO_I)
(add_net GPIO_J)
(add_net GPIO_K)
(add_net GPIO_L)
(add_net I2C0_SCL)
(add_net I2C0_SDA)
(add_net I2C1_SCL)
(add_net I2C1_SDA)
(add_net PCM_CLK)
(add_net PCM_DI)
(add_net PCM_DO)
(add_net PCM_FS)
(add_net PWR_BTN_N)
(add_net RST_BTN_N)
(add_net SPIO_CS)
(add_net SPIO_DIN)
(add_net SPIO_DOUT)
(add_net SPIO_SCL)
(add_net SYS_DCIN)
(add_net UART0_CTS)
(add_net UART0_RTS)
(add_net UART0_RX)
(add_net UART0_TX)
(add_net UART1_RX)
(add_net UART1_TX)
)
(net_class Power ""
(clearance 0.1778)
(trace_width 0.381)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +1V8)
(add_net +5V)
(add_net GND)
)
(module 96boards:Socket_Strip_Straight_2x20_Pitch2mm locked (layer F.Cu) (tedit 56949A3C) (tstamp 56AB82C3)
(at 110 105 90)
(descr "Double row through-hole 2mm socket strip, 2x20 contacts")
(tags CONN)
(path /55D48226)
(fp_text reference P2 (at 1 -2 90) (layer F.SilkS)
(effects (font (size 0.7 0.7) (thickness 0.15)))
)
(fp_text value CONN_02X20 (at 1 -4 90) (layer F.Fab)
(effects (font (size 1.016 1.016) (thickness 0.2032)))
)
(fp_line (start 0 -1.2) (end -1.2 -1.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1.2 -1.2) (end -1.2 0) (layer F.SilkS) (width 0.15))
(fp_line (start 3.5 -1.5) (end 3.5 39.5) (layer F.CrtYd) (width 0.15))
(fp_line (start 3.5 39.5) (end -1.5 39.5) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 39.5) (end -1.5 -1.5) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 -1.5) (end 3.5 -1.5) (layer F.CrtYd) (width 0.15))
(fp_line (start 1 1) (end -1 1) (layer F.SilkS) (width 0.15))
(fp_line (start -1 1) (end -1 39) (layer F.SilkS) (width 0.15))
(fp_line (start -1 39) (end 3 39) (layer F.SilkS) (width 0.15))
(fp_line (start 3 39) (end 3 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 3 -1) (end 1 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -1) (end 1 1) (layer F.SilkS) (width 0.15))
(pad 40 thru_hole circle (at 2 38) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 39 thru_hole circle (at 0 38) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 38 thru_hole circle (at 2 36) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 10 SYS_DCIN))
(pad 37 thru_hole circle (at 0 36) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 3 +5V))
(pad 36 thru_hole circle (at 2 34) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 10 SYS_DCIN))
(pad 35 thru_hole circle (at 0 34) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 1 +1V8))
(pad 34 thru_hole circle (at 2 32) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 25 GPIO_L))
(pad 33 thru_hole circle (at 0 32) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 32 GPIO_K))
(pad 32 thru_hole circle (at 2 30) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 24 GPIO_J))
(pad 31 thru_hole circle (at 0 30) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 31 GPIO_I))
(pad 30 thru_hole circle (at 2 28) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 23 GPIO_H))
(pad 29 thru_hole circle (at 0 28) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 30 GPIO_G))
(pad 28 thru_hole circle (at 2 26) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 22 GPIO_F))
(pad 27 thru_hole circle (at 0 26) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 29 GPIO_E))
(pad 26 thru_hole circle (at 2 24) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 21 GPIO_D))
(pad 25 thru_hole circle (at 0 24) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 28 GPIO_C))
(pad 24 thru_hole circle (at 2 22) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 11 GPIO_B))
(pad 23 thru_hole circle (at 0 22) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 12 GPIO_A))
(pad 22 thru_hole circle (at 2 20) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 20 PCM_DI))
(pad 21 thru_hole circle (at 0 20) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 7 I2C1_SDA))
(pad 20 thru_hole circle (at 2 18) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 19 PCM_DO))
(pad 19 thru_hole circle (at 0 18) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 6 I2C1_SCL))
(pad 18 thru_hole circle (at 2 16) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 18 PCM_CLK))
(pad 17 thru_hole circle (at 0 16) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 5 I2C0_SDA))
(pad 16 thru_hole circle (at 2 14) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 17 PCM_FS))
(pad 15 thru_hole circle (at 0 14) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 4 I2C0_SCL))
(pad 14 thru_hole circle (at 2 12) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 16 SPIO_DOUT))
(pad 13 thru_hole circle (at 0 12) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 27 UART1_RX))
(pad 12 thru_hole circle (at 2 10) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 15 SPIO_CS))
(pad 11 thru_hole circle (at 0 10) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 26 UART1_TX))
(pad 10 thru_hole circle (at 2 8) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 14 SPIO_DIN))
(pad 9 thru_hole circle (at 0 8) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 36 UART0_RTS))
(pad 8 thru_hole circle (at 2 6) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 13 SPIO_SCL))
(pad 7 thru_hole circle (at 0 6) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 35 UART0_RX))
(pad 6 thru_hole circle (at 2 4) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 9 RST_BTN_N))
(pad 5 thru_hole circle (at 0 4) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 34 UART0_TX))
(pad 4 thru_hole circle (at 2 2) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 8 PWR_BTN_N))
(pad 3 thru_hole circle (at 0 2) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 33 UART0_CTS))
(pad 2 thru_hole circle (at 2 0) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(pad 1 thru_hole rect (at 0 0 90) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
(net 2 GND))
(model Socket_Strips.3dshapes/Socket_Strip_Straight_2x20.wrl
(offset (xyz 1.000759984970093 -19.02459971427918 0.4003039939880371))
(scale (xyz 0.787 0.787 0.5))
(rotate (xyz 0 0 90))
)
)
(module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55DECD77) (tstamp 55F48FD6)
(at 104 135.5)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask))
)
(module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55DECD77) (tstamp 55DED4DA)
(at 181 135.5)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask))
)
(module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55C6917D) (tstamp 55C69203)
(at 181 104)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask))
)
(module Sensors:Hole_2.5MM locked (layer F.Cu) (tedit 55C743C8) (tstamp 55C691E1)
(at 104 104)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole_2.5MM (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 2.5) (layers *.Cu *.Mask))
)
(module 96boards:Pin_Header_SMD_2x20_Pitch2mm locked (layer B.Cu) (tedit 55F9A19C) (tstamp 56AB8296)
(at 110 105 270)
(descr "Double row SMD 2mm pin header, 2x20 contacts")
(path /55D44709)
(attr smd)
(fp_text reference P1 (at -1 2 270) (layer B.SilkS)
(effects (font (size 0.7 0.7) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_02X20 (at -1 4 270) (layer B.Fab)
(effects (font (size 1.016 1.016) (thickness 0.2032)) (justify mirror))
)
(fp_line (start 2.95 0.6) (end 2.95 -38.7) (layer B.SilkS) (width 0.15))
(fp_line (start -4.95 0.6) (end 2.95 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -4.95 -38.7) (end 2.95 -38.7) (layer B.SilkS) (width 0.15))
(fp_line (start -4.95 0.6) (end -4.95 -38.7) (layer B.SilkS) (width 0.15))
(pad "" np_thru_hole circle (at -1 -37) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask B.SilkS))
(pad 1 smd rect (at 1.25 0) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad 2 smd rect (at -3.25 0.01) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad "" np_thru_hole circle (at -1 -1) (size 1.2 1.2) (drill 1.2) (layers *.Cu *.Mask B.SilkS))
(pad 4 smd rect (at -3.25 -2) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 8 PWR_BTN_N))
(pad 6 smd rect (at -3.25 -4) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 9 RST_BTN_N))
(pad 8 smd rect (at -3.25 -6) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 13 SPIO_SCL))
(pad 10 smd rect (at -3.25 -8) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 14 SPIO_DIN))
(pad 12 smd rect (at -3.25 -10) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 15 SPIO_CS))
(pad 14 smd rect (at -3.25 -12) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 16 SPIO_DOUT))
(pad 16 smd rect (at -3.25 -14) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 17 PCM_FS))
(pad 18 smd rect (at -3.25 -16) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 18 PCM_CLK))
(pad 20 smd rect (at -3.25 -18) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 19 PCM_DO))
(pad 22 smd rect (at -3.25 -20) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 20 PCM_DI))
(pad 24 smd rect (at -3.25 -22) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 11 GPIO_B))
(pad 26 smd rect (at -3.25 -24) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 21 GPIO_D))
(pad 28 smd rect (at -3.25 -26) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 22 GPIO_F))
(pad 30 smd rect (at -3.25 -28) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 23 GPIO_H))
(pad 32 smd rect (at -3.25 -30) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 24 GPIO_J))
(pad 34 smd rect (at -3.25 -32) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 25 GPIO_L))
(pad 36 smd rect (at -3.25 -34) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 10 SYS_DCIN))
(pad 38 smd rect (at -3.25 -36) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 10 SYS_DCIN))
(pad 40 smd rect (at -3.25 -38) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(pad 3 smd rect (at 1.25 -2) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 33 UART0_CTS))
(pad 5 smd rect (at 1.25 -4) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 34 UART0_TX))
(pad 7 smd rect (at 1.25 -6) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 35 UART0_RX))
(pad 9 smd rect (at 1.25 -8) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 36 UART0_RTS))
(pad 11 smd rect (at 1.25 -10) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 26 UART1_TX))
(pad 13 smd rect (at 1.25 -12) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 27 UART1_RX))
(pad 15 smd rect (at 1.25 -14) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 4 I2C0_SCL))
(pad 17 smd rect (at 1.25 -16) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 5 I2C0_SDA))
(pad 19 smd rect (at 1.25 -18) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 6 I2C1_SCL))
(pad 21 smd rect (at 1.25 -20) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 7 I2C1_SDA))
(pad 23 smd rect (at 1.25 -22) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 12 GPIO_A))
(pad 25 smd rect (at 1.25 -24) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 28 GPIO_C))
(pad 27 smd rect (at 1.25 -26) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 29 GPIO_E))
(pad 29 smd rect (at 1.25 -28) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 30 GPIO_G))
(pad 31 smd rect (at 1.25 -30) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 31 GPIO_I))
(pad 33 smd rect (at 1.25 -32) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 32 GPIO_K))
(pad 35 smd rect (at 1.25 -34) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 1 +1V8))
(pad 37 smd rect (at 1.25 -36) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 3 +5V))
(pad 39 smd rect (at 1.25 -38) (size 0.89 3) (layers B.Cu B.Paste B.Mask)
(net 2 GND))
(model Pin_Headers.3dshapes/Pin_Header_Straight_2x20.wrl
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(scale (xyz 0.787 0.787 0.5))
(rotate (xyz 0 0 90))
)
)
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