FinalReport.vl.out

#! /opt/homebrew/Cellar/icarus-verilog/11.0/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/system.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/v2005_math.vpi";
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/11.0/lib/ivl/va_math.vpi";
S_0x153f36910 .scope module, "test" "test" 2 207;
 .timescale 0 0;
v0x153f55de0_0 .net/s "EXMEM_IR", 31 0, v0x153f536e0_0;  1 drivers
v0x153f55eb0_0 .net/s "IDEX_IR", 31 0, v0x153f53f60_0;  1 drivers
v0x153f55f40_0 .net/s "IFID_IR", 31 0, v0x153f54600_0;  1 drivers
v0x153f55ff0_0 .net/s "MEMWB_IR", 31 0, v0x153f53df0_0;  1 drivers
v0x153f560a0_0 .net/s "PC", 31 0, v0x153f54e60_0;  1 drivers
v0x153f561b0_0 .net/s "WD", 31 0, L_0x153f58150;  1 drivers
v0x153f56280_0 .var "clock", 0 0;
S_0x153f2f5a0 .scope module, "test_cpu" "CPU" 2 210, 2 67 0, S_0x153f36910;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clock";
    .port_info 1 /OUTPUT 32 "PC";
    .port_info 2 /OUTPUT 32 "IFID_IR";
    .port_info 3 /OUTPUT 32 "IDEX_IR";
    .port_info 4 /OUTPUT 32 "EXMEM_IR";
    .port_info 5 /OUTPUT 32 "MEMWB_IR";
    .port_info 6 /OUTPUT 32 "WD";
L_0x153f564e0 .functor AND 1, v0x153f53640_0, v0x153f53b30_0, C4<1>, C4<1>;
L_0x153f580a0 .functor BUFZ 32, L_0x153f57dc0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
v0x153f53200_0 .net "ALUOut", 31 0, v0x153f51820_0;  1 drivers
v0x153f532d0_0 .net "ALUctl", 3 0, v0x153f41cf0_0;  1 drivers
v0x153f53360_0 .net "B", 31 0, L_0x153f57bd0;  1 drivers
v0x153f53410_0 .net "Control", 7 0, v0x153f50b80_0;  1 drivers
v0x153f534c0 .array "DMemory", 1023 0, 31 0;
v0x153f53590_0 .var "EXMEM_ALUOut", 31 0;
v0x153f53640_0 .var "EXMEM_Branch", 0 0;
v0x153f536e0_0 .var "EXMEM_IR", 31 0;
v0x153f53790_0 .var "EXMEM_MemWrite", 0 0;
v0x153f538a0_0 .var "EXMEM_MemtoReg", 0 0;
v0x153f53930_0 .var "EXMEM_RD2", 31 0;
v0x153f539e0_0 .var "EXMEM_RegWrite", 0 0;
v0x153f53a80_0 .var "EXMEM_Target", 31 0;
v0x153f53b30_0 .var "EXMEM_Zero", 0 0;
v0x153f53bd0_0 .var "EXMEM_rd", 4 0;
v0x153f53c80_0 .var "IDEX_ALUOp", 1 0;
v0x153f53d40_0 .var "IDEX_ALUSrc", 0 0;
v0x153f53ed0_0 .var "IDEX_Branch", 0 0;
v0x153f53f60_0 .var "IDEX_IR", 31 0;
v0x153f53ff0_0 .var "IDEX_MemWrite", 0 0;
v0x153f54080_0 .var "IDEX_MemtoReg", 0 0;
v0x153f54120_0 .var "IDEX_PCplus4", 31 0;
v0x153f541e0_0 .var "IDEX_RD1", 31 0;
v0x153f54270_0 .var "IDEX_RD2", 31 0;
v0x153f54300_0 .var "IDEX_RegDst", 0 0;
v0x153f54390_0 .var "IDEX_RegWrite", 0 0;
v0x153f54420_0 .var "IDEX_SignExt", 31 0;
v0x153f544b0_0 .var "IDEX_rd", 4 0;
v0x153f54550_0 .var "IDEX_rt", 4 0;
v0x153f54600_0 .var "IFID_IR", 31 0;
v0x153f546b0_0 .var "IFID_PCplus4", 31 0;
v0x153f54760 .array "IMemory", 1023 0, 31 0;
v0x153f54800_0 .var "MEMWB_ALUOut", 31 0;
v0x153f53df0_0 .var "MEMWB_IR", 31 0;
v0x153f54a90_0 .var "MEMWB_MemOut", 31 0;
v0x153f54b20_0 .var "MEMWB_MemtoReg", 0 0;
v0x153f54bb0_0 .var "MEMWB_RegWrite", 0 0;
v0x153f54c60_0 .var "MEMWB_rd", 4 0;
v0x153f54d10_0 .net "MemOut", 31 0, L_0x153f580a0;  1 drivers
v0x153f54db0_0 .net "NextPC", 31 0, L_0x153f56590;  1 drivers
v0x153f54e60_0 .var "PC", 31 0;
v0x153f54f20_0 .net "PCplus4", 31 0, v0x153f51fb0_0;  1 drivers
v0x153f54fd0_0 .net "RD1", 31 0, L_0x153f568d0;  1 drivers
v0x153f55080_0 .net "RD2", 31 0, L_0x153f56be0;  1 drivers
v0x153f55130_0 .net "SignExtend", 31 0, L_0x153f571c0;  1 drivers
v0x153f551d0_0 .net "Target", 31 0, v0x153f510b0_0;  1 drivers
v0x153f55290_0 .net "Unused1", 0 0, L_0x153f56380;  1 drivers
v0x153f55340_0 .net "Unused2", 0 0, L_0x153f575c0;  1 drivers
v0x153f553f0_0 .net "WD", 31 0, L_0x153f58150;  alias, 1 drivers
v0x153f554a0_0 .net "WR", 4 0, L_0x153f57cb0;  1 drivers
v0x153f55530_0 .net "Zero", 0 0, L_0x153f57970;  1 drivers
v0x153f555e0_0 .net *"_ivl_15", 0 0, L_0x153f56ff0;  1 drivers
v0x153f55670_0 .net *"_ivl_16", 15 0, L_0x153f57090;  1 drivers
v0x153f55720_0 .net *"_ivl_19", 15 0, L_0x153f57280;  1 drivers
v0x153f557d0_0 .net *"_ivl_26", 29 0, L_0x153f57720;  1 drivers
L_0x158068208 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x153f55880_0 .net *"_ivl_28", 1 0, L_0x158068208;  1 drivers
v0x153f55930_0 .net *"_ivl_36", 31 0, L_0x153f57dc0;  1 drivers
v0x153f559e0_0 .net *"_ivl_38", 31 0, L_0x153f57f80;  1 drivers
v0x153f55a90_0 .net *"_ivl_40", 29 0, L_0x153f57e60;  1 drivers
L_0x158068298 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x153f55b40_0 .net *"_ivl_42", 1 0, L_0x158068298;  1 drivers
v0x153f55bf0_0 .net *"_ivl_5", 0 0, L_0x153f564e0;  1 drivers
v0x153f55c90_0 .net "clock", 0 0, v0x153f56280_0;  1 drivers
L_0x153f56590 .functor MUXZ 32, v0x153f51fb0_0, v0x153f53a80_0, L_0x153f564e0, C4<>;
L_0x153f56cd0 .part v0x153f54600_0, 21, 5;
L_0x153f56df0 .part v0x153f54600_0, 16, 5;
L_0x153f56ed0 .part v0x153f54600_0, 26, 6;
L_0x153f56ff0 .part v0x153f54600_0, 15, 1;
LS_0x153f57090_0_0 .concat [ 1 1 1 1], L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0;
LS_0x153f57090_0_4 .concat [ 1 1 1 1], L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0;
LS_0x153f57090_0_8 .concat [ 1 1 1 1], L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0;
LS_0x153f57090_0_12 .concat [ 1 1 1 1], L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0, L_0x153f56ff0;
L_0x153f57090 .concat [ 4 4 4 4], LS_0x153f57090_0_0, LS_0x153f57090_0_4, LS_0x153f57090_0_8, LS_0x153f57090_0_12;
L_0x153f57280 .part v0x153f54600_0, 0, 16;
L_0x153f571c0 .concat [ 16 16 0 0], L_0x153f57280, L_0x153f57090;
L_0x153f57720 .part v0x153f54420_0, 0, 30;
L_0x153f57810 .concat [ 2 30 0 0], L_0x158068208, L_0x153f57720;
L_0x153f57a90 .part v0x153f54420_0, 0, 6;
L_0x153f57bd0 .functor MUXZ 32, v0x153f54270_0, v0x153f54420_0, v0x153f53d40_0, C4<>;
L_0x153f57cb0 .functor MUXZ 5, v0x153f54550_0, v0x153f544b0_0, v0x153f54300_0, C4<>;
L_0x153f57dc0 .array/port v0x153f534c0, L_0x153f57f80;
L_0x153f57e60 .part v0x153f53590_0, 2, 30;
L_0x153f57f80 .concat [ 30 2 0 0], L_0x153f57e60, L_0x158068298;
L_0x153f58150 .functor MUXZ 32, v0x153f54800_0, v0x153f54a90_0, v0x153f54b20_0, C4<>;
S_0x153f30e00 .scope module, "ALUCtrl" "ALUControl" 2 145, 2 49 0, S_0x153f2f5a0;
 .timescale 0 0;
    .port_info 0 /INPUT 2 "ALUOp";
    .port_info 1 /INPUT 6 "FuncCode";
    .port_info 2 /OUTPUT 4 "ALUCtl";
v0x153f41cf0_0 .var "ALUCtl", 3 0;
v0x153f50790_0 .net "ALUOp", 1 0, v0x153f53c80_0;  1 drivers
v0x153f50840_0 .net "FuncCode", 5 0, L_0x153f57a90;  1 drivers
E_0x153f3c4c0 .event edge, v0x153f50840_0, v0x153f50790_0;
S_0x153f50950 .scope module, "MainCtr" "MainControl" 2 130, 2 36 0, S_0x153f2f5a0;
 .timescale 0 0;
    .port_info 0 /INPUT 6 "Op";
    .port_info 1 /OUTPUT 8 "Control";
v0x153f50b80_0 .var "Control", 7 0;
v0x153f50c40_0 .net "Op", 5 0, L_0x153f56ed0;  1 drivers
E_0x153f50b50 .event edge, v0x153f50c40_0;
S_0x153f50d20 .scope module, "branch" "alu" 2 143, 2 17 0, S_0x153f2f5a0;
 .timescale 0 0;
    .port_info 0 /INPUT 4 "ALUctl";
    .port_info 1 /INPUT 32 "A";
    .port_info 2 /INPUT 32 "B";
    .port_info 3 /OUTPUT 32 "ALUOut";
    .port_info 4 /OUTPUT 1 "Zero";
v0x153f51000_0 .net "A", 31 0, L_0x153f57810;  1 drivers
v0x153f510b0_0 .var "ALUOut", 31 0;
L_0x1580681c0 .functor BUFT 1, C4<0010>, C4<0>, C4<0>, C4<0>;
v0x153f51160_0 .net "ALUctl", 3 0, L_0x1580681c0;  1 drivers
v0x153f51220_0 .net "B", 31 0, v0x153f54120_0;  1 drivers
v0x153f512d0_0 .net "Zero", 0 0, L_0x153f575c0;  alias, 1 drivers
L_0x158068178 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x153f513b0_0 .net/2u *"_ivl_0", 31 0, L_0x158068178;  1 drivers
E_0x153f50fb0 .event edge, v0x153f51220_0, v0x153f51000_0, v0x153f51160_0;
L_0x153f575c0 .cmp/eq 32, v0x153f510b0_0, L_0x158068178;
S_0x153f514e0 .scope module, "ex" "alu" 2 144, 2 17 0, S_0x153f2f5a0;
 .timescale 0 0;
    .port_info 0 /INPUT 4 "ALUctl";
    .port_info 1 /INPUT 32 "A";
    .port_info 2 /INPUT 32 "B";
    .port_info 3 /OUTPUT 32 "ALUOut";
    .port_info 4 /OUTPUT 1 "Zero";
v0x153f51770_0 .net "A", 31 0, v0x153f541e0_0;  1 drivers
v0x153f51820_0 .var "ALUOut", 31 0;
v0x153f518d0_0 .net "ALUctl", 3 0, v0x153f41cf0_0;  alias, 1 drivers
v0x153f519a0_0 .net "B", 31 0, L_0x153f57bd0;  alias, 1 drivers
v0x153f51a40_0 .net "Zero", 0 0, L_0x153f57970;  alias, 1 drivers
L_0x158068250 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x153f51b20_0 .net/2u *"_ivl_0", 31 0, L_0x158068250;  1 drivers
E_0x153f51720 .event edge, v0x153f519a0_0, v0x153f51770_0, v0x153f41cf0_0;
L_0x153f57970 .cmp/eq 32, v0x153f51820_0, L_0x158068250;
S_0x153f51c50 .scope module, "fetch" "alu" 2 115, 2 17 0, S_0x153f2f5a0;
 .timescale 0 0;
    .port_info 0 /INPUT 4 "ALUctl";
    .port_info 1 /INPUT 32 "A";
    .port_info 2 /INPUT 32 "B";
    .port_info 3 /OUTPUT 32 "ALUOut";
    .port_info 4 /OUTPUT 1 "Zero";
v0x153f51f00_0 .net "A", 31 0, v0x153f54e60_0;  alias, 1 drivers
v0x153f51fb0_0 .var "ALUOut", 31 0;
L_0x158068058 .functor BUFT 1, C4<0010>, C4<0>, C4<0>, C4<0>;
v0x153f52060_0 .net "ALUctl", 3 0, L_0x158068058;  1 drivers
L_0x1580680a0 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>;
v0x153f52120_0 .net "B", 31 0, L_0x1580680a0;  1 drivers
v0x153f521d0_0 .net "Zero", 0 0, L_0x153f56380;  alias, 1 drivers
L_0x158068010 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x153f522b0_0 .net/2u *"_ivl_0", 31 0, L_0x158068010;  1 drivers
E_0x153f51ed0 .event edge, v0x153f52120_0, v0x153f51f00_0, v0x153f52060_0;
L_0x153f56380 .cmp/eq 32, v0x153f51fb0_0, L_0x158068010;
S_0x153f523e0 .scope module, "rf" "reg_file" 2 129, 2 3 0, S_0x153f2f5a0;
 .timescale 0 0;
    .port_info 0 /INPUT 5 "RR1";
    .port_info 1 /INPUT 5 "RR2";
    .port_info 2 /INPUT 5 "WR";
    .port_info 3 /INPUT 32 "WD";
    .port_info 4 /INPUT 1 "RegWrite";
    .port_info 5 /OUTPUT 32 "RD1";
    .port_info 6 /OUTPUT 32 "RD2";
    .port_info 7 /INPUT 1 "clock";
L_0x153f568d0 .functor BUFZ 32, L_0x153f56690, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
L_0x153f56be0 .functor BUFZ 32, L_0x153f569c0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
v0x153f526a0_0 .net "RD1", 31 0, L_0x153f568d0;  alias, 1 drivers
v0x153f52760_0 .net "RD2", 31 0, L_0x153f56be0;  alias, 1 drivers
v0x153f52810_0 .net "RR1", 4 0, L_0x153f56cd0;  1 drivers
v0x153f528d0_0 .net "RR2", 4 0, L_0x153f56df0;  1 drivers
v0x153f52980_0 .net "RegWrite", 0 0, v0x153f54bb0_0;  1 drivers
v0x153f52a60 .array "Regs", 31 0, 31 0;
v0x153f52b00_0 .net "WD", 31 0, L_0x153f58150;  alias, 1 drivers
v0x153f52bb0_0 .net "WR", 4 0, v0x153f54c60_0;  1 drivers
v0x153f52c60_0 .net *"_ivl_0", 31 0, L_0x153f56690;  1 drivers
v0x153f52d70_0 .net *"_ivl_10", 6 0, L_0x153f56a60;  1 drivers
L_0x158068130 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x153f52e20_0 .net *"_ivl_13", 1 0, L_0x158068130;  1 drivers
v0x153f52ed0_0 .net *"_ivl_2", 6 0, L_0x153f56770;  1 drivers
L_0x1580680e8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0x153f52f80_0 .net *"_ivl_5", 1 0, L_0x1580680e8;  1 drivers
v0x153f53030_0 .net *"_ivl_8", 31 0, L_0x153f569c0;  1 drivers
v0x153f530e0_0 .net "clock", 0 0, v0x153f56280_0;  alias, 1 drivers
E_0x153f50f00 .event negedge, v0x153f530e0_0;
L_0x153f56690 .array/port v0x153f52a60, L_0x153f56770;
L_0x153f56770 .concat [ 5 2 0 0], L_0x153f56cd0, L_0x1580680e8;
L_0x153f569c0 .array/port v0x153f52a60, L_0x153f56a60;
L_0x153f56a60 .concat [ 5 2 0 0], L_0x153f56df0, L_0x158068130;
    .scope S_0x153f51c50;
T_0 ;
    %wait E_0x153f51ed0;
    %load/vec4 v0x153f52060_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 4;
    %cmp/u;
    %jmp/1 T_0.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 4;
    %cmp/u;
    %jmp/1 T_0.1, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 4;
    %cmp/u;
    %jmp/1 T_0.2, 6;
    %dup/vec4;
    %pushi/vec4 6, 0, 4;
    %cmp/u;
    %jmp/1 T_0.3, 6;
    %dup/vec4;
    %pushi/vec4 7, 0, 4;
    %cmp/u;
    %jmp/1 T_0.4, 6;
    %dup/vec4;
    %pushi/vec4 12, 0, 4;
    %cmp/u;
    %jmp/1 T_0.5, 6;
    %dup/vec4;
    %pushi/vec4 13, 0, 4;
    %cmp/u;
    %jmp/1 T_0.6, 6;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.0 ;
    %load/vec4 v0x153f51f00_0;
    %load/vec4 v0x153f52120_0;
    %and;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.1 ;
    %load/vec4 v0x153f51f00_0;
    %load/vec4 v0x153f52120_0;
    %or;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.2 ;
    %load/vec4 v0x153f51f00_0;
    %load/vec4 v0x153f52120_0;
    %add;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.3 ;
    %load/vec4 v0x153f51f00_0;
    %load/vec4 v0x153f52120_0;
    %sub;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.4 ;
    %load/vec4 v0x153f51f00_0;
    %load/vec4 v0x153f52120_0;
    %cmp/u;
    %flag_mov 8, 5;
    %jmp/0 T_0.9, 8;
    %pushi/vec4 1, 0, 32;
    %jmp/1 T_0.10, 8;
T_0.9 ; End of true expr.
    %pushi/vec4 0, 0, 32;
    %jmp/0 T_0.10, 8;
 ; End of false expr.
    %blend;
T_0.10;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.5 ;
    %load/vec4 v0x153f51f00_0;
    %inv;
    %load/vec4 v0x153f52120_0;
    %inv;
    %and;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.6 ;
    %load/vec4 v0x153f51f00_0;
    %inv;
    %load/vec4 v0x153f52120_0;
    %inv;
    %or;
    %assign/vec4 v0x153f51fb0_0, 0;
    %jmp T_0.8;
T_0.8 ;
    %pop/vec4 1;
    %jmp T_0;
    .thread T_0, $push;
    .scope S_0x153f523e0;
T_1 ;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f52a60, 4, 0;
    %end;
    .thread T_1;
    .scope S_0x153f523e0;
T_2 ;
    %wait E_0x153f50f00;
    %load/vec4 v0x153f52980_0;
    %pad/u 32;
    %pushi/vec4 1, 0, 32;
    %cmp/e;
    %flag_get/vec4 4;
    %load/vec4 v0x153f52bb0_0;
    %pad/u 32;
    %pushi/vec4 0, 0, 32;
    %cmp/ne;
    %flag_get/vec4 4;
    %and;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.0, 8;
    %load/vec4 v0x153f52b00_0;
    %load/vec4 v0x153f52bb0_0;
    %pad/u 7;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x153f52a60, 0, 4;
T_2.0 ;
    %jmp T_2;
    .thread T_2;
    .scope S_0x153f50950;
T_3 ;
    %wait E_0x153f50b50;
    %load/vec4 v0x153f50c40_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 6;
    %cmp/u;
    %jmp/1 T_3.0, 6;
    %dup/vec4;
    %pushi/vec4 35, 0, 6;
    %cmp/u;
    %jmp/1 T_3.1, 6;
    %dup/vec4;
    %pushi/vec4 43, 0, 6;
    %cmp/u;
    %jmp/1 T_3.2, 6;
    %dup/vec4;
    %pushi/vec4 4, 0, 6;
    %cmp/u;
    %jmp/1 T_3.3, 6;
    %dup/vec4;
    %pushi/vec4 8, 0, 6;
    %cmp/u;
    %jmp/1 T_3.4, 6;
    %jmp T_3.5;
T_3.0 ;
    %pushi/vec4 146, 0, 8;
    %assign/vec4 v0x153f50b80_0, 0;
    %jmp T_3.5;
T_3.1 ;
    %pushi/vec4 112, 0, 8;
    %assign/vec4 v0x153f50b80_0, 0;
    %jmp T_3.5;
T_3.2 ;
    %pushi/vec4 72, 0, 8;
    %assign/vec4 v0x153f50b80_0, 0;
    %jmp T_3.5;
T_3.3 ;
    %pushi/vec4 5, 0, 8;
    %assign/vec4 v0x153f50b80_0, 0;
    %jmp T_3.5;
T_3.4 ;
    %pushi/vec4 84, 0, 8;
    %assign/vec4 v0x153f50b80_0, 0;
    %jmp T_3.5;
T_3.5 ;
    %pop/vec4 1;
    %jmp T_3;
    .thread T_3, $push;
    .scope S_0x153f50d20;
T_4 ;
    %wait E_0x153f50fb0;
    %load/vec4 v0x153f51160_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 4;
    %cmp/u;
    %jmp/1 T_4.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 4;
    %cmp/u;
    %jmp/1 T_4.1, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 4;
    %cmp/u;
    %jmp/1 T_4.2, 6;
    %dup/vec4;
    %pushi/vec4 6, 0, 4;
    %cmp/u;
    %jmp/1 T_4.3, 6;
    %dup/vec4;
    %pushi/vec4 7, 0, 4;
    %cmp/u;
    %jmp/1 T_4.4, 6;
    %dup/vec4;
    %pushi/vec4 12, 0, 4;
    %cmp/u;
    %jmp/1 T_4.5, 6;
    %dup/vec4;
    %pushi/vec4 13, 0, 4;
    %cmp/u;
    %jmp/1 T_4.6, 6;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.0 ;
    %load/vec4 v0x153f51000_0;
    %load/vec4 v0x153f51220_0;
    %and;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.1 ;
    %load/vec4 v0x153f51000_0;
    %load/vec4 v0x153f51220_0;
    %or;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.2 ;
    %load/vec4 v0x153f51000_0;
    %load/vec4 v0x153f51220_0;
    %add;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.3 ;
    %load/vec4 v0x153f51000_0;
    %load/vec4 v0x153f51220_0;
    %sub;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.4 ;
    %load/vec4 v0x153f51000_0;
    %load/vec4 v0x153f51220_0;
    %cmp/u;
    %flag_mov 8, 5;
    %jmp/0 T_4.9, 8;
    %pushi/vec4 1, 0, 32;
    %jmp/1 T_4.10, 8;
T_4.9 ; End of true expr.
    %pushi/vec4 0, 0, 32;
    %jmp/0 T_4.10, 8;
 ; End of false expr.
    %blend;
T_4.10;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.5 ;
    %load/vec4 v0x153f51000_0;
    %inv;
    %load/vec4 v0x153f51220_0;
    %inv;
    %and;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.6 ;
    %load/vec4 v0x153f51000_0;
    %inv;
    %load/vec4 v0x153f51220_0;
    %inv;
    %or;
    %assign/vec4 v0x153f510b0_0, 0;
    %jmp T_4.8;
T_4.8 ;
    %pop/vec4 1;
    %jmp T_4;
    .thread T_4, $push;
    .scope S_0x153f514e0;
T_5 ;
    %wait E_0x153f51720;
    %load/vec4 v0x153f518d0_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 4;
    %cmp/u;
    %jmp/1 T_5.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 4;
    %cmp/u;
    %jmp/1 T_5.1, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 4;
    %cmp/u;
    %jmp/1 T_5.2, 6;
    %dup/vec4;
    %pushi/vec4 6, 0, 4;
    %cmp/u;
    %jmp/1 T_5.3, 6;
    %dup/vec4;
    %pushi/vec4 7, 0, 4;
    %cmp/u;
    %jmp/1 T_5.4, 6;
    %dup/vec4;
    %pushi/vec4 12, 0, 4;
    %cmp/u;
    %jmp/1 T_5.5, 6;
    %dup/vec4;
    %pushi/vec4 13, 0, 4;
    %cmp/u;
    %jmp/1 T_5.6, 6;
    %pushi/vec4 0, 0, 32;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.0 ;
    %load/vec4 v0x153f51770_0;
    %load/vec4 v0x153f519a0_0;
    %and;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.1 ;
    %load/vec4 v0x153f51770_0;
    %load/vec4 v0x153f519a0_0;
    %or;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.2 ;
    %load/vec4 v0x153f51770_0;
    %load/vec4 v0x153f519a0_0;
    %add;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.3 ;
    %load/vec4 v0x153f51770_0;
    %load/vec4 v0x153f519a0_0;
    %sub;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.4 ;
    %load/vec4 v0x153f51770_0;
    %load/vec4 v0x153f519a0_0;
    %cmp/u;
    %flag_mov 8, 5;
    %jmp/0 T_5.9, 8;
    %pushi/vec4 1, 0, 32;
    %jmp/1 T_5.10, 8;
T_5.9 ; End of true expr.
    %pushi/vec4 0, 0, 32;
    %jmp/0 T_5.10, 8;
 ; End of false expr.
    %blend;
T_5.10;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.5 ;
    %load/vec4 v0x153f51770_0;
    %inv;
    %load/vec4 v0x153f519a0_0;
    %inv;
    %and;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.6 ;
    %load/vec4 v0x153f51770_0;
    %inv;
    %load/vec4 v0x153f519a0_0;
    %inv;
    %or;
    %assign/vec4 v0x153f51820_0, 0;
    %jmp T_5.8;
T_5.8 ;
    %pop/vec4 1;
    %jmp T_5;
    .thread T_5, $push;
    .scope S_0x153f30e00;
T_6 ;
    %wait E_0x153f3c4c0;
    %load/vec4 v0x153f50790_0;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_6.0, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_6.1, 6;
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_6.2, 6;
    %jmp T_6.3;
T_6.0 ;
    %pushi/vec4 2, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.3;
T_6.1 ;
    %pushi/vec4 6, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.3;
T_6.2 ;
    %load/vec4 v0x153f50840_0;
    %dup/vec4;
    %pushi/vec4 32, 0, 6;
    %cmp/u;
    %jmp/1 T_6.4, 6;
    %dup/vec4;
    %pushi/vec4 34, 0, 6;
    %cmp/u;
    %jmp/1 T_6.5, 6;
    %dup/vec4;
    %pushi/vec4 36, 0, 6;
    %cmp/u;
    %jmp/1 T_6.6, 6;
    %dup/vec4;
    %pushi/vec4 37, 0, 6;
    %cmp/u;
    %jmp/1 T_6.7, 6;
    %dup/vec4;
    %pushi/vec4 39, 0, 6;
    %cmp/u;
    %jmp/1 T_6.8, 6;
    %dup/vec4;
    %pushi/vec4 42, 0, 6;
    %cmp/u;
    %jmp/1 T_6.9, 6;
    %jmp T_6.10;
T_6.4 ;
    %pushi/vec4 2, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.10;
T_6.5 ;
    %pushi/vec4 6, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.10;
T_6.6 ;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.10;
T_6.7 ;
    %pushi/vec4 1, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.10;
T_6.8 ;
    %pushi/vec4 12, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.10;
T_6.9 ;
    %pushi/vec4 7, 0, 4;
    %assign/vec4 v0x153f41cf0_0, 0;
    %jmp T_6.10;
T_6.10 ;
    %pop/vec4 1;
    %jmp T_6.3;
T_6.3 ;
    %pop/vec4 1;
    %jmp T_6;
    .thread T_6, $push;
    .scope S_0x153f2f5a0;
T_7 ;
    %pushi/vec4 2349400064, 0, 32;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 2349465604, 0, 32;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 2, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 3, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 4, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 19552298, 0, 32;
    %ix/load 4, 5, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 6, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 7, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 8, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 291504133, 0, 32;
    %ix/load 4, 9, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 10, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 11, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 12, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 2886270980, 0, 32;
    %ix/load 4, 13, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 2886336512, 0, 32;
    %ix/load 4, 14, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 15, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 16, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 17, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 2349400064, 0, 32;
    %ix/load 4, 18, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 2349465604, 0, 32;
    %ix/load 4, 19, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 20, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 21, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 22, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 21647399, 0, 32;
    %ix/load 4, 23, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 24, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 25, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 26, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 558497793, 0, 32;
    %ix/load 4, 27, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 28, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 29, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 0, 0, 32;
    %ix/load 4, 30, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 19552288, 0, 32;
    %ix/load 4, 31, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f54760, 4, 0;
    %pushi/vec4 5, 0, 32;
    %ix/load 4, 0, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f534c0, 4, 0;
    %pushi/vec4 5, 0, 32;
    %ix/load 4, 1, 0;
    %flag_set/imm 4, 0;
    %store/vec4a v0x153f534c0, 4, 0;
    %end;
    .thread T_7;
    .scope S_0x153f2f5a0;
T_8 ;
    %wait E_0x153f50f00;
    %load/vec4 v0x153f53790_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_8.0, 8;
    %load/vec4 v0x153f53930_0;
    %load/vec4 v0x153f53590_0;
    %ix/load 4, 2, 0;
    %flag_set/imm 4, 0;
    %shiftr 4;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v0x153f534c0, 0, 4;
T_8.0 ;
    %jmp T_8;
    .thread T_8;
    .scope S_0x153f2f5a0;
T_9 ;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x153f54e60_0, 0, 32;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f54390_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f54080_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f53ed0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f53ff0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f53d40_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f54300_0, 0, 1;
    %pushi/vec4 0, 0, 2;
    %store/vec4 v0x153f53c80_0, 0, 2;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x153f54600_0, 0, 32;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f539e0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f538a0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f53640_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f53790_0, 0, 1;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v0x153f53a80_0, 0, 32;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f54bb0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0x153f54b20_0, 0, 1;
    %end;
    .thread T_9;
    .scope S_0x153f2f5a0;
T_10 ;
    %wait E_0x153f50f00;
    %load/vec4 v0x153f54db0_0;
    %assign/vec4 v0x153f54e60_0, 0;
    %load/vec4 v0x153f54f20_0;
    %assign/vec4 v0x153f546b0_0, 0;
    %load/vec4 v0x153f54e60_0;
    %ix/load 5, 2, 0;
    %flag_set/imm 4, 0;
    %shiftr 5;
    %ix/vec4 4;
    %load/vec4a v0x153f54760, 4;
    %assign/vec4 v0x153f54600_0, 0;
    %load/vec4 v0x153f54600_0;
    %assign/vec4 v0x153f53f60_0, 0;
    %load/vec4 v0x153f53410_0;
    %split/vec4 2;
    %assign/vec4 v0x153f53c80_0, 0;
    %split/vec4 1;
    %assign/vec4 v0x153f53ed0_0, 0;
    %split/vec4 1;
    %assign/vec4 v0x153f53ff0_0, 0;
    %split/vec4 1;
    %assign/vec4 v0x153f54390_0, 0;
    %split/vec4 1;
    %assign/vec4 v0x153f54080_0, 0;
    %split/vec4 1;
    %assign/vec4 v0x153f53d40_0, 0;
    %assign/vec4 v0x153f54300_0, 0;
    %load/vec4 v0x153f546b0_0;
    %assign/vec4 v0x153f54120_0, 0;
    %load/vec4 v0x153f54fd0_0;
    %assign/vec4 v0x153f541e0_0, 0;
    %load/vec4 v0x153f55080_0;
    %assign/vec4 v0x153f54270_0, 0;
    %load/vec4 v0x153f55130_0;
    %assign/vec4 v0x153f54420_0, 0;
    %load/vec4 v0x153f54600_0;
    %parti/s 5, 16, 6;
    %assign/vec4 v0x153f54550_0, 0;
    %load/vec4 v0x153f54600_0;
    %parti/s 5, 11, 5;
    %assign/vec4 v0x153f544b0_0, 0;
    %load/vec4 v0x153f53f60_0;
    %assign/vec4 v0x153f536e0_0, 0;
    %load/vec4 v0x153f54390_0;
    %assign/vec4 v0x153f539e0_0, 0;
    %load/vec4 v0x153f54080_0;
    %assign/vec4 v0x153f538a0_0, 0;
    %load/vec4 v0x153f53ed0_0;
    %assign/vec4 v0x153f53640_0, 0;
    %load/vec4 v0x153f53ff0_0;
    %assign/vec4 v0x153f53790_0, 0;
    %load/vec4 v0x153f551d0_0;
    %assign/vec4 v0x153f53a80_0, 0;
    %load/vec4 v0x153f55530_0;
    %assign/vec4 v0x153f53b30_0, 0;
    %load/vec4 v0x153f53200_0;
    %assign/vec4 v0x153f53590_0, 0;
    %load/vec4 v0x153f54270_0;
    %assign/vec4 v0x153f53930_0, 0;
    %load/vec4 v0x153f554a0_0;
    %assign/vec4 v0x153f53bd0_0, 0;
    %load/vec4 v0x153f536e0_0;
    %assign/vec4 v0x153f53df0_0, 0;
    %load/vec4 v0x153f539e0_0;
    %assign/vec4 v0x153f54bb0_0, 0;
    %load/vec4 v0x153f538a0_0;
    %assign/vec4 v0x153f54b20_0, 0;
    %load/vec4 v0x153f54d10_0;
    %assign/vec4 v0x153f54a90_0, 0;
    %load/vec4 v0x153f53590_0;
    %assign/vec4 v0x153f54800_0, 0;
    %load/vec4 v0x153f53bd0_0;
    %assign/vec4 v0x153f54c60_0, 0;
    %jmp T_10;
    .thread T_10;
    .scope S_0x153f36910;
T_11 ;
    %delay 1, 0;
    %load/vec4 v0x153f56280_0;
    %inv;
    %store/vec4 v0x153f56280_0, 0, 1;
    %jmp T_11;
    .thread T_11;
    .scope S_0x153f36910;
T_12 ;
    %vpi_call 2 213 "$display", "PC   IFID_IR  IDEX_IR  EXMEM_IR MEMWB_IR  WD" {0 0 0};
    %vpi_call 2 214 "$monitor", "%3d  %h %h %h %h %2d", v0x153f560a0_0, v0x153f55f40_0, v0x153f55eb0_0, v0x153f55de0_0, v0x153f55ff0_0, v0x153f561b0_0 {0 0 0};
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0x153f56280_0, 0, 1;
    %delay 69, 0;
    %vpi_call 2 216 "$finish" {0 0 0};
    %end;
    .thread T_12;
# The file index is used to find the file name in the following table.
:file_names 3;
    "N/A";
    "<interactive>";
    "FinalReport.vl";