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imx585.c
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imx585.c
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// SPDX-License-Identifier: GPL-2.0
/*
* A V4L2 driver for Sony imx585 cameras.
*
* Based on Sony imx477 camera driver
* Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd
* Modified by Will WHANG
* Modified by sohonomura2020 in Soho Enterprise Ltd.
* Modified by OCTOPUSCINEMA
* Copyright (C) 2024 OCTOPUS CINEMA
*/
#include <asm/unaligned.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-mediabus.h>
static bool monochrome_mode;
module_param(monochrome_mode, bool, 0644);
MODULE_PARM_DESC(monochrome_mode, "Set for monochrome sensor: 1=mono, 0=color");
// Support for rpi kernel pre git commit 314a685
#ifndef MEDIA_BUS_FMT_SENSOR_DATA
#define MEDIA_BUS_FMT_SENSOR_DATA 0x7002
#endif
/* Chip ID */
#define IMX585_REG_CHIP_ID 0x30DC
#define IMX585_CHIP_ID 0x32
/* Standby or streaming mode */
#define IMX585_REG_MODE_SELECT 0x3000
#define IMX585_MODE_STANDBY 0x01
#define IMX585_MODE_STREAMING 0x00
#define IMX585_STREAM_DELAY_US 25000
#define IMX585_STREAM_DELAY_RANGE_US 1000
/* In clk */
#define IMX585_XCLK_FREQ 24000000
/* VMAX internal VBLANK*/
#define IMX585_REG_VMAX 0x3028
#define IMX585_VMAX_MAX 0xfffff
/* HMAX internal HBLANK*/
#define IMX585_REG_HMAX 0x302C
#define IMX585_HMAX_MAX 0xffff
/* SHR internal */
#define IMX585_REG_SHR 0x3050
#define IMX585_SHR_MIN 11
/* Exposure control */
#define IMX585_EXPOSURE_MIN 52
#define IMX585_EXPOSURE_STEP 1
#define IMX585_EXPOSURE_DEFAULT 1000
#define IMX585_EXPOSURE_MAX 49865
/* HDR threshold */
#define IMX585_REG_EXP_TH_H 0x36D0
#define IMX585_REG_EXP_TH_L 0x36D4
#define IMX585_REG_EXP_BK 0x36E2
/* Gradation compression control */
#define IMX585_REG_CCMP1_EXP 0x36E8
#define IMX585_REG_CCMP2_EXP 0x36E4
#define IMX585_REG_ACMP1_EXP 0x36EE
#define IMX585_REG_ACMP2_EXP 0x36EC
/* Black level control */
#define IMX585_REG_BLKLEVEL 0x30DC
#define IMX585_BLKLEVEL_DEFAULT 0
/* Digital Clamp */
#define IMX585_REG_DIGITAL_CLAMP 0x3458
/* Analog gain control */
#define IMX585_REG_ANALOG_GAIN 0x306C
#define IMX585_REG_FDG_SEL0 0x3030
#define IMX585_ANA_GAIN_MIN 0
#define IMX585_ANA_GAIN_MAX 240 // x3980= 72db = 0.3db x 240
#define IMX585_ANA_GAIN_STEP 1
#define IMX585_ANA_GAIN_DEFAULT 0
#define IMX585_ANA_GAIN_HCG_LEVEL 51 // = 15.3db / 0.3db
#define IMX585_ANA_GAIN_HCG_THRESHOLD (IMX585_ANA_GAIN_HCG_LEVEL+29)
#define IMX585_ANA_GAIN_HCG_MIN 34
/* Flip */
#define IMX585_FLIP_WINMODEH 0x3020
#define IMX585_FLIP_WINMODEV 0x3021
/* Embedded metadata stream structure */
#define IMX585_EMBEDDED_LINE_WIDTH 16384
#define IMX585_NUM_EMBEDDED_LINES 1
#define IMX585_PIXEL_RATE 74250000
enum pad_types {
IMAGE_PAD,
METADATA_PAD,
NUM_PADS
};
/* Gradation compression */
enum v4l2_xfer_func_sony {
V4L2_XFER_FUNC_GRADATION_COMPRESSION = 10
};
/* imx585 native and active pixel array size. */
#define IMX585_NATIVE_WIDTH 3856U
#define IMX585_NATIVE_HEIGHT 2180U
#define IMX585_PIXEL_ARRAY_LEFT 8U
#define IMX585_PIXEL_ARRAY_TOP 8U
#define IMX585_PIXEL_ARRAY_WIDTH 3840U
#define IMX585_PIXEL_ARRAY_HEIGHT 2160U
struct imx585_reg {
u16 address;
u8 val;
};
struct IMX585_reg_list {
unsigned int num_of_regs;
const struct imx585_reg *regs;
};
/* Mode : resolution and related config&values */
struct imx585_mode {
/* Frame width */
unsigned int width;
/* Frame height */
unsigned int height;
/* mode uses Clear HDR */
bool hdr;
/* mode has linear output (gradation compression disabled) */
bool linear;
/* minimum H-timing */
uint64_t min_HMAX;
/* minimum V-timing */
uint64_t min_VMAX;
/* default H-timing */
uint64_t default_HMAX;
/* default V-timing */
uint64_t default_VMAX;
/* minimum SHR */
uint64_t min_SHR;
/* Analog crop rectangle. */
struct v4l2_rect crop;
/* Default register values */
struct IMX585_reg_list reg_list;
};
/* Common Modes */
static const struct imx585_reg mode_common_regs[] = {
{0x3002, 0x01},
{0x301A, 0x00}, //WDMODE Normal mode
//{0x301A, 0x10}, //WDMODE Clear HDR
{0x301B, 0x00}, //ADDMODE 0x00 non-binning
{0x3024, 0x00}, // COMBI_EN
// {0x3024, 0x02}, // COMBI_EN 0x02=Clear HDR mode
{0x3069, 0x00},
//{0x3069, 0x02}, // for Clear HDR mode
{0x3074, 0x64},
{0x30D5, 0x04}, // DIG_CLP_VSTART
// {0x3074, 0x63}, // for Clear HDR
{0x3930, 0x0c},//DUR normal mode 12bit
{0x3931, 0x01},//DUR normal mode 12bit
// {0x3930, 0xE6},//DUR Clear HDR 12bit
// {0x3931, 0x00},//DUR Clear HDR 12bit
{0x3A4C, 0x39},// WAIT_ST0 Normal
{0x3A4D, 0x01},// Normal
{0x3A50, 0x48},// WAIT_ST1 Normal
{0x3A51, 0x01},// Normal
// {0x3A4C, 0x61},// WAIT_ST0
// {0x3A4D, 0x02},//
// {0x3A50, 0x70},// WAIT_ST1
// {0x3A51, 0x02},//
{0x3E10, 0x10},// ADTHEN Normal
// {0x3E10, 0x17},// ADTHEN
{0x493C, 0x23},// ADTHEN
{0x4940, 0x41},// ADTHEN
// {0x493C, 0x41},// ADTHEN
// {0x4940, 0x41},// ADTHEN
{0x3014, 0x04},// INCK_SEL [3:0] 24 MHz
{0x3015, 0x02},// DATARATE_SEL [3:0] 1782 Mbps
// {0x302C, 0x4C},// HMAX [15:0]
// {0x302D, 0x04},//
{0x3030, 0x00},// FDG_SEL0 LCG, HCG:0x01
{0x3040, 0x03},// LANEMODE [2:0] 4 lane
{0x3023, 0x01},// MDBIT 12-bit
// {0x3028, 0x94},// VMAX
// {0x3029, 0x11},// VMAX
// {0x302A, 0x00},// VMAX
// {0x3050, 0xFF},// SHR0 [19:0]
{0x30A6, 0x00},// XVS_DRV [1:0] Hi-Z
{0x3081, 0x00},// EXP_GAIN, Reset to 0
{0x3460, 0x21},// -
{0x3478, 0xA1},// -
{0x347C, 0x01},// -
{0x3480, 0x01},// -
{0x3A4E, 0x14},// -
{0x3A52, 0x14},// -
{0x3A56, 0x00},// -
{0x3A5A, 0x00},// -
{0x3A5E, 0x00},// -
{0x3A62, 0x00},// -
{0x3A6A, 0x20},// -
{0x3A6C, 0x42},// -
{0x3A6E, 0xA0},// -
{0x3B2C, 0x0C},// -
{0x3B30, 0x1C},// -
{0x3B34, 0x0C},// -
{0x3B38, 0x1C},// -
{0x3BA0, 0x0C},// -
{0x3BA4, 0x1C},// -
{0x3BA8, 0x0C},// -
{0x3BAC, 0x1C},// -
{0x3D3C, 0x11},// -
{0x3D46, 0x0B},// -
{0x3DE0, 0x3F},// -
{0x3DE1, 0x08},// -
{0x3E14, 0x87},// -
{0x3E16, 0x91},// -
{0x3E18, 0x91},// -
{0x3E1A, 0x87},// -
{0x3E1C, 0x78},// -
{0x3E1E, 0x50},// -
{0x3E20, 0x50},// -
{0x3E22, 0x50},// -
{0x3E24, 0x87},// -
{0x3E26, 0x91},// -
{0x3E28, 0x91},// -
{0x3E2A, 0x87},// -
{0x3E2C, 0x78},// -
{0x3E2E, 0x50},// -
{0x3E30, 0x50},// -
{0x3E32, 0x50},// -
{0x3E34, 0x87},// -
{0x3E36, 0x91},// -
{0x3E38, 0x91},// -
{0x3E3A, 0x87},// -
{0x3E3C, 0x78},// -
{0x3E3E, 0x50},// -
{0x3E40, 0x50},// -
{0x3E42, 0x50},// -
{0x4054, 0x64},// -
{0x4148, 0xFE},// -
{0x4149, 0x05},// -
{0x414A, 0xFF},// -
{0x414B, 0x05},// -
{0x420A, 0x03},// -
{0x4231, 0x08},// -
{0x423D, 0x9C},// -
{0x4242, 0xB4},// -
{0x4246, 0xB4},// -
{0x424E, 0xB4},// -
{0x425C, 0xB4},// -
{0x425E, 0xB6},// -
{0x426C, 0xB4},// -
{0x426E, 0xB6},// -
{0x428C, 0xB4},// -
{0x428E, 0xB6},// -
{0x4708, 0x00},// -
{0x4709, 0x00},// -
{0x470A, 0xFF},// -
{0x470B, 0x03},// -
{0x470C, 0x00},// -
{0x470D, 0x00},// -
{0x470E, 0xFF},// -
{0x470F, 0x03},// -
{0x47EB, 0x1C},// -
{0x47F0, 0xA6},// -
{0x47F2, 0xA6},// -
{0x47F4, 0xA0},// -
{0x47F6, 0x96},// -
{0x4808, 0xA6},// -
{0x480A, 0xA6},// -
{0x480C, 0xA0},// -
{0x480E, 0x96},// -
{0x492C, 0xB2},// -
{0x4930, 0x03},// -
{0x4932, 0x03},// -
{0x4936, 0x5B},// -
{0x4938, 0x82},// -
{0x493E, 0x23},// -
{0x4BA8, 0x1C},// -
{0x4BA9, 0x03},// -
{0x4BAC, 0x1C},// -
{0x4BAD, 0x1C},// -
{0x4BAE, 0x1C},// -
{0x4BAF, 0x1C},// -
{0x4BB0, 0x1C},// -
{0x4BB1, 0x1C},// -
{0x4BB2, 0x1C},// -
{0x4BB3, 0x1C},// -
{0x4BB4, 0x1C},// -
{0x4BB8, 0x03},// -
{0x4BB9, 0x03},// -
{0x4BBA, 0x03},// -
{0x4BBB, 0x03},// -
{0x4BBC, 0x03},// -
{0x4BBD, 0x03},// -
{0x4BBE, 0x03},// -
{0x4BBF, 0x03},// -
{0x4BC0, 0x03},// -
{0x4C14, 0x87},// -
{0x4C16, 0x91},// -
{0x4C18, 0x91},// -
{0x4C1A, 0x87},// -
{0x4C1C, 0x78},// -
{0x4C1E, 0x50},// -
{0x4C20, 0x50},// -
{0x4C22, 0x50},// -
{0x4C24, 0x87},// -
{0x4C26, 0x91},// -
{0x4C28, 0x91},// -
{0x4C2A, 0x87},// -
{0x4C2C, 0x78},// -
{0x4C2E, 0x50},// -
{0x4C30, 0x50},// -
{0x4C32, 0x50},// -
{0x4C34, 0x87},// -
{0x4C36, 0x91},// -
{0x4C38, 0x91},// -
{0x4C3A, 0x87},// -
{0x4C3C, 0x78},// -
{0x4C3E, 0x50},// -
{0x4C40, 0x50},// -
{0x4C42, 0x50},// -
{0x4D12, 0x1F},// -
{0x4D13, 0x1E},// -
{0x4D26, 0x33},// -
{0x4E0E, 0x59},// -
{0x4E14, 0x55},// -
{0x4E16, 0x59},// -
{0x4E1E, 0x3B},// -
{0x4E20, 0x47},// -
{0x4E22, 0x54},// -
{0x4E26, 0x81},// -
{0x4E2C, 0x7D},// -
{0x4E2E, 0x81},// -
{0x4E36, 0x63},// -
{0x4E38, 0x6F},// -
{0x4E3A, 0x7C},// -
{0x4F3A, 0x3C},// -
{0x4F3C, 0x46},// -
{0x4F3E, 0x59},// -
{0x4F42, 0x64},// -
{0x4F44, 0x6E},// -
{0x4F46, 0x81},// -
{0x4F4A, 0x82},// -
{0x4F5A, 0x81},// -
{0x4F62, 0xAA},// -
{0x4F72, 0xA9},// -
{0x4F78, 0x36},// -
{0x4F7A, 0x41},// -
{0x4F7C, 0x61},// -
{0x4F7D, 0x01},// -
{0x4F7E, 0x7C},// -
{0x4F7F, 0x01},// -
{0x4F80, 0x77},// -
{0x4F82, 0x7B},// -
{0x4F88, 0x37},// -
{0x4F8A, 0x40},// -
{0x4F8C, 0x62},// -
{0x4F8D, 0x01},// -
{0x4F8E, 0x76},// -
{0x4F8F, 0x01},// -
{0x4F90, 0x5E},// -
{0x4F91, 0x02},// -
{0x4F92, 0x69},// -
{0x4F93, 0x02},// -
{0x4F94, 0x89},// -
{0x4F95, 0x02},// -
{0x4F96, 0xA4},// -
{0x4F97, 0x02},// -
{0x4F98, 0x9F},// -
{0x4F99, 0x02},// -
{0x4F9A, 0xA3},// -
{0x4F9B, 0x02},// -
{0x4FA0, 0x5F},// -
{0x4FA1, 0x02},// -
{0x4FA2, 0x68},// -
{0x4FA3, 0x02},// -
{0x4FA4, 0x8A},// -
{0x4FA5, 0x02},// -
{0x4FA6, 0x9E},// -
{0x4FA7, 0x02},// -
{0x519E, 0x79},// -
{0x51A6, 0xA1},// -
{0x51F0, 0xAC},// -
{0x51F2, 0xAA},// -
{0x51F4, 0xA5},// -
{0x51F6, 0xA0},// -
{0x5200, 0x9B},// -
{0x5202, 0x91},// -
{0x5204, 0x87},// -
{0x5206, 0x82},// -
{0x5208, 0xAC},// -
{0x520A, 0xAA},// -
{0x520C, 0xA5},// -
{0x520E, 0xA0},// -
{0x5210, 0x9B},// -
{0x5212, 0x91},// -
{0x5214, 0x87},// -
{0x5216, 0x82},// -
{0x5218, 0xAC},// -
{0x521A, 0xAA},// -
{0x521C, 0xA5},// -
{0x521E, 0xA0},// -
{0x5220, 0x9B},// -
{0x5222, 0x91},// -
{0x5224, 0x87},// -
{0x5226, 0x82},// -
{0x3002, 0x00}, // Master mode start
};
/* All pixel 4K60. 12-bit (Normal) */
static const struct imx585_reg mode_4k_regs[] = {
{0x301A, 0x00}, // WDMODE Normal mode
{0x301B, 0x00}, // ADDMODE non-binning
{0x3022, 0x02}, // ADBIT 12-bit
{0x3023, 0x01}, // MDBIT 12-bit
{0x3024, 0x00}, // COMBI_EN no HDR combining
{0x36EF, 0x00}, // CCMP_EN Linear
{0x3069, 0x00}, // Normal mode
{0x3074, 0x64}, // Normal mode
{0x30D5, 0x04}, // DIG_CLP_VSTART non-binning
{0x3930, 0x0c}, // DUR normal mode 12bit
{0x3931, 0x01}, // DUR normal mode 12bit
{0x3A4C, 0x39}, // WAIT_ST0 Normal mode
{0x3A4D, 0x01}, // Normal mode
{0x3A50, 0x48}, // WAIT_ST1 Normal mode
{0x3A51, 0x01}, // Normal mode
{0x3E10, 0x10}, // ADTHEN Normal mode
{0x493C, 0x23}, // ADTHEN Normal mode
{0x4940, 0x41}, // ADTHEN Normal mode
};
/* 2x2 binned 1080p60. 12-bit (Normal) */
static const struct imx585_reg mode_1080_regs[] = {
{0x301A, 0x00}, // WDMODE Normal mode
{0x301B, 0x01}, // ADDMODE binning
{0x3022, 0x00}, // ADBIT 10-bit
{0x3023, 0x01}, // MDBIT 12-bit
{0x3024, 0x00}, // COMBI_EN no HDR combining
{0x36EF, 0x00}, // CCMP_EN Linear
{0x3069, 0x00}, // Normal mode
{0x3074, 0x64}, // Normal mode
{0x30D5, 0x02}, // DIG_CLP_VSTART binning
{0x3930, 0x0c}, // DUR normal mode 12bit
{0x3931, 0x01}, // DUR normal mode 12bit
{0x3A4C, 0x39}, // WAIT_ST0 Normal mode
{0x3A4D, 0x01}, // Normal mode
{0x3A50, 0x48}, // WAIT_ST1 Normal mode
{0x3A51, 0x01}, // Normal mode
{0x3E10, 0x10}, // ADTHEN Normal mode
{0x493C, 0x23}, // ADTHEN Normal mode
{0x4940, 0x41}, // ADTHEN Normal mode
};
/* All pixel 4K30. 12-bit (HDR gradation compression) */
static const struct imx585_reg mode_4k_nonlinear_regs[] = {
{0x301A, 0x10}, // WDMODE Clear HDR
{0x301B, 0x00}, // ADDMODE Non-binning
{0x3022, 0x02}, // ADBIT 12-bit
{0x3023, 0x01}, // MDBIT 12-bit
{0x3024, 0x02}, // COMBI_EN
{0x36EF, 0x01}, // CCMP_EN Non-linear gradation compression
{0x3030, 0x00}, // FDG_SEL0 LCG, HCG:0x01
{0x3069, 0x02}, // for Clear HDR mode
{0x3074, 0x63}, // for Clear HDR
{0x3081, 0x02}, // EXP_GAIN, Clear HDR high gain setting, +12dB
{0x30D5, 0x02}, // DIG_CLP_VSTART Non-binning
{0x3930, 0xE6}, // DUR Clear HDR 12bit
{0x3931, 0x00}, // DUR Clear HDR 12bit
{0x3A4C, 0x61}, // WAIT_ST0 Clear HDR mode
{0x3A4D, 0x02}, // Clear HDR mode
{0x3A50, 0x70}, // WAIT_ST1
{0x3A51, 0x02}, // Clear HDR mode
{0x3E10, 0x17}, // ADTHEN Clear HDR
{0x493C, 0x41}, // WAIT_10_SHF Clear HDR 10-bit 0x0C disable
{0x4940, 0x41}, // WAIT_12_SHF Clear HDR 12-bit 0x41 enable
};
/* All pixel 4K30. 16-bit (Clear HDR) */
static const struct imx585_reg mode_4k_16bit_regs[] = {
{0x301A, 0x10}, // WDMODE Clear HDR
{0x301B, 0x00}, // ADDMODE Non-binning
{0x3022, 0x02}, // ADBIT 12-bit
{0x3023, 0x03}, // MDBIT 16-bit
{0x3024, 0x02}, // COMBI_EN
{0x36EF, 0x00}, // CCMP_EN Linear
{0x3030, 0x00}, // FDG_SEL0 LCG, HCG:0x01
{0x3069, 0x02}, // for Clear HDR mode
{0x3074, 0x63}, // for Clear HDR
{0x3081, 0x02}, // EXP_GAIN, Clear HDR high gain setting, +12dB
{0x30D5, 0x02}, // DIG_CLP_VSTART Non-binning
{0x3930, 0xE6}, // DUR Clear HDR 12bit
{0x3931, 0x00}, // DUR Clear HDR 12bit
{0x3A4C, 0x61}, // WAIT_ST0 Clear HDR mode
{0x3A4D, 0x02}, // Clear HDR mode
{0x3A50, 0x70}, // WAIT_ST1
{0x3A51, 0x02}, // Clear HDR mode
{0x3E10, 0x17}, // ADTHEN Clear HDR
{0x493C, 0x41}, // WAIT_10_SHF Clear HDR 10-bit 0x0C disable
{0x4940, 0x41}, // WAIT_12_SHF Clear HDR 12-bit 0x41 enable
};
/* 2x2 binned 1080p30. 16-bit (Clear HDR) */
static const struct imx585_reg mode_1080_16bit_regs[] = {
{0x301A, 0x10}, // WDMODE Clear HDR
{0x301B, 0x01}, // ADDMODE Binning
{0x3022, 0x02}, // ADBIT 12-bit
{0x3023, 0x03}, // MDBIT 16-bit
{0x3024, 0x02}, // COMBI_EN Built-in HDR combining
{0x36EF, 0x00}, // CCMP_EN Linear
{0x3030, 0x00}, // FDG_SEL0 LCG, HCG:0x01
{0x3069, 0x02}, // for Clear HDR mode
{0x3074, 0x63}, // for Clear HDR
{0x3081, 0x02}, // EXP_GAIN, Clear HDR high gain setting, +12dB
{0x30D5, 0x02}, // DIG_CLP_VSTART
{0x3930, 0xE6}, // DUR Clear HDR 12bit
{0x3931, 0x00}, // DUR Clear HDR 12bit
{0x3A4C, 0x61}, // WAIT_ST0
{0x3A4D, 0x02}, // Clear HDR mode
{0x3A50, 0x70}, // WAIT_ST1
{0x3A51, 0x02}, // Clear HDR mode
{0x3E10, 0x17}, // ADTHEN Clear HDR
{0x493C, 0x41}, // WAIT_10_SHF Clear HDR 10-bit 0x0C disable
{0x4940, 0x41}, // WAIT_12_SHF Clear HDR 12-bit 0x41 enable
};
/* Mode configs */
static const struct imx585_mode supported_modes_12bit[] = {
{
/* 4K60 All pixel */
.width = 3856,
.height = 2180,
.hdr = false,
.linear = true,
.min_HMAX = 550,
.min_VMAX = 2250,
.default_HMAX = 550,
.default_VMAX = 2250,
.min_SHR = 20,
.crop = {
.left = IMX585_PIXEL_ARRAY_LEFT,
.top = IMX585_PIXEL_ARRAY_TOP,
.width = IMX585_PIXEL_ARRAY_WIDTH,
.height = IMX585_PIXEL_ARRAY_HEIGHT,
},
.reg_list = {
.num_of_regs = ARRAY_SIZE(mode_4k_regs),
.regs = mode_4k_regs,
},
},
{
/* 1080p90 2x2 binning */
.width = 1928,
.height = 1090,
.hdr = false,
.linear = true,
.min_HMAX = 366,
.min_VMAX = 2250,
.default_HMAX = 366,
.default_VMAX = 2250,
.min_SHR = 20,
.crop = {
.left = IMX585_PIXEL_ARRAY_LEFT,
.top = IMX585_PIXEL_ARRAY_TOP,
.width = IMX585_PIXEL_ARRAY_WIDTH,
.height = IMX585_PIXEL_ARRAY_HEIGHT,
},
.reg_list = {
.num_of_regs = ARRAY_SIZE(mode_1080_regs),
.regs = mode_1080_regs,
},
},
};
static const struct imx585_mode supported_modes_nonlinear_12bit[] = {
{
/* 4K30 All pixel */
.width = 3856,
.height = 2180,
.hdr = true,
.linear = false,
//.min_HMAX = 760,
.min_HMAX = 550, // Clear HDR original
//.min_VMAX = 2250,
.min_VMAX = 4500, // Clear HDR original
.default_HMAX = 550,
.default_VMAX = 4500,
// .default_HMAX = 550,
// .default_VMAX = 4500,
.min_SHR = 20,
.crop = {
.left = IMX585_PIXEL_ARRAY_LEFT,
.top = IMX585_PIXEL_ARRAY_TOP,
.width = IMX585_PIXEL_ARRAY_WIDTH,
.height = IMX585_PIXEL_ARRAY_HEIGHT,
},
.reg_list = {
.num_of_regs = ARRAY_SIZE(mode_4k_nonlinear_regs),
.regs = mode_4k_nonlinear_regs,
},
},
};
static const struct imx585_mode supported_modes_16bit[] = {
{
/* 1080p30 2x2 binning */
.width = 1928,
.height = 1090,
.hdr = true,
.linear = true,
//.min_HMAX = 760,
.min_HMAX = 550, // Clear HDR original
//.min_VMAX = 2250,
.min_VMAX = 4500, // Clear HDR original
.default_HMAX = 550,
.default_VMAX = 4500,
// .default_HMAX = 550,
// .default_VMAX = 4500,
.min_SHR = 20,
.crop = {
.left = IMX585_PIXEL_ARRAY_LEFT,
.top = IMX585_PIXEL_ARRAY_TOP,
.width = IMX585_PIXEL_ARRAY_WIDTH,
.height = IMX585_PIXEL_ARRAY_HEIGHT,
},
.reg_list = {
.num_of_regs = ARRAY_SIZE(mode_1080_16bit_regs),
.regs = mode_1080_16bit_regs,
},
},
{
/* 4K30 All pixel */
.width = 3856,
.height = 2180,
.hdr = true,
.linear = true,
//.min_HMAX = 760,
.min_HMAX = 550, // Clear HDR original
//.min_VMAX = 2250,
.min_VMAX = 4500, // Clear HDR original
.default_HMAX = 550,
.default_VMAX = 4500,
// .default_HMAX = 550,
// .default_VMAX = 4500,
.min_SHR = 20,
.crop = {
.left = IMX585_PIXEL_ARRAY_LEFT,
.top = IMX585_PIXEL_ARRAY_TOP,
.width = IMX585_PIXEL_ARRAY_WIDTH,
.height = IMX585_PIXEL_ARRAY_HEIGHT,
},
.reg_list = {
.num_of_regs = ARRAY_SIZE(mode_4k_16bit_regs),
.regs = mode_4k_16bit_regs,
},
},
};
/*
* The supported formats.
* This table MUST contain 4 entries per format, to cover the various flip
* combinations in the order
* - no flip
* - h flip
* - v flip
* - h&v flips
*/
static const u32 codes[] = {
/* 16-bit modes. */
MEDIA_BUS_FMT_SRGGB16_1X16,
MEDIA_BUS_FMT_SGRBG16_1X16,
MEDIA_BUS_FMT_SGBRG16_1X16,
MEDIA_BUS_FMT_SBGGR16_1X16,
/* 12-bit modes. */
MEDIA_BUS_FMT_SRGGB12_1X12,
MEDIA_BUS_FMT_SGRBG12_1X12,
MEDIA_BUS_FMT_SGBRG12_1X12,
MEDIA_BUS_FMT_SBGGR12_1X12,
};
static const u32 mono_codes[] = {
/* 16-bit modes. */
MEDIA_BUS_FMT_Y16_1X16,
/* 12-bit modes. */
MEDIA_BUS_FMT_Y12_1X12,
};
/* regulator supplies */
static const char * const imx585_supply_name[] = {
/* Supplies can be enabled in any order */
"VANA", /* Analog (3.3V) supply */
"VDIG", /* Digital Core (1.1V) supply */
"VDDL", /* IF (1.8V) supply */
};
#define imx585_NUM_SUPPLIES ARRAY_SIZE(imx585_supply_name)
/*
* Initialisation delay between XCLR low->high and the moment when the sensor
* can start capture (i.e. can leave software standby)
*/
#define imx585_XCLR_MIN_DELAY_US 500000
#define imx585_XCLR_DELAY_RANGE_US 1000
struct imx585_compatible_data {
unsigned int chip_id;
struct IMX585_reg_list extra_regs;
};
struct imx585 {
struct v4l2_subdev sd;
struct media_pad pad[NUM_PADS];
unsigned int fmt_code;
struct clk *xclk;
u32 xclk_freq;
struct gpio_desc *reset_gpio;
struct regulator_bulk_data supplies[imx585_NUM_SUPPLIES];
struct v4l2_ctrl_handler ctrl_handler;
/* V4L2 Controls */
struct v4l2_ctrl *pixel_rate;
struct v4l2_ctrl *exposure;
struct v4l2_ctrl *vflip;
struct v4l2_ctrl *hflip;
struct v4l2_ctrl *vblank;
struct v4l2_ctrl *hblank;
/* Current mode */
const struct imx585_mode *mode;
/* Mono mode */
bool mono;
uint16_t HMAX;
uint32_t VMAX;
/*
* Mutex for serialized access:
* Protect sensor module set pad format and start/stop streaming safely.
*/
struct mutex mutex;
/* Streaming on/off */
bool streaming;
/* Rewrite common registers on stream on? */
bool common_regs_written;
/* Any extra information related to different compatible sensors */
const struct imx585_compatible_data *compatible_data;
};
static inline struct imx585 *to_imx585(struct v4l2_subdev *_sd)
{
return container_of(_sd, struct imx585, sd);
}
static inline void get_mode_table(struct imx585 *imx585, unsigned int code, enum v4l2_xfer_func transfer_function,
const struct imx585_mode **mode_list,
unsigned int *num_modes)
{
struct i2c_client *client = v4l2_get_subdevdata(&imx585->sd);
if(imx585->mono){
switch (code) {
case MEDIA_BUS_FMT_Y16_1X16:
*mode_list = supported_modes_16bit;
*num_modes = ARRAY_SIZE(supported_modes_16bit);
break;
case MEDIA_BUS_FMT_Y12_1X12:
if ( transfer_function == (enum v4l2_xfer_func)V4L2_XFER_FUNC_GRADATION_COMPRESSION ) {
*mode_list = supported_modes_nonlinear_12bit;
*num_modes = ARRAY_SIZE(supported_modes_nonlinear_12bit);
} else {
*mode_list = supported_modes_12bit;
*num_modes = ARRAY_SIZE(supported_modes_12bit);
}
break;
default:
*mode_list = NULL;
*num_modes = 0;
}
}
else{
switch (code) {
/* 16-bit */
case MEDIA_BUS_FMT_SRGGB16_1X16:
case MEDIA_BUS_FMT_SGRBG16_1X16:
case MEDIA_BUS_FMT_SGBRG16_1X16:
case MEDIA_BUS_FMT_SBGGR16_1X16:
*mode_list = supported_modes_16bit;
*num_modes = ARRAY_SIZE(supported_modes_16bit);
break;
/* 12-bit */
case MEDIA_BUS_FMT_SRGGB12_1X12:
case MEDIA_BUS_FMT_SGRBG12_1X12:
case MEDIA_BUS_FMT_SGBRG12_1X12:
case MEDIA_BUS_FMT_SBGGR12_1X12:
if ( transfer_function == (enum v4l2_xfer_func)V4L2_XFER_FUNC_GRADATION_COMPRESSION ) {
*mode_list = supported_modes_nonlinear_12bit;
*num_modes = ARRAY_SIZE(supported_modes_nonlinear_12bit);
} else {
*mode_list = supported_modes_12bit;
*num_modes = ARRAY_SIZE(supported_modes_12bit);
}
break;
default:
*mode_list = NULL;
*num_modes = 0;
}
}
}
/* Read registers up to 2 at a time */
static int imx585_read_reg(struct imx585 *imx585, u16 reg, u32 len, u32 *val)
{
struct i2c_client *client = v4l2_get_subdevdata(&imx585->sd);
struct i2c_msg msgs[2];
u8 addr_buf[2] = { reg >> 8, reg & 0xff };
u8 data_buf[4] = { 0, };
int ret;
if (len > 4)
return -EINVAL;
/* Write register address */
msgs[0].addr = client->addr;
msgs[0].flags = 0;
msgs[0].len = ARRAY_SIZE(addr_buf);
msgs[0].buf = addr_buf;
/* Read data from register */
msgs[1].addr = client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = len;
msgs[1].buf = &data_buf[4 - len];
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret != ARRAY_SIZE(msgs))
return -EIO;
*val = get_unaligned_be32(data_buf);
return 0;
}
/* Write registers 1 byte at a time */
static int imx585_write_reg_1byte(struct imx585 *imx585, u16 reg, u8 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&imx585->sd);
u8 buf[3];
int ret;
put_unaligned_be16(reg, buf);
buf[2] = val;
ret = i2c_master_send(client, buf, 3);
if ( ret != 3 )
return ret;
return 0;
}
/* Write registers 2 byte at a time */
static int imx585_write_reg_2byte(struct imx585 *imx585, u16 reg, u16 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&imx585->sd);
u8 buf[4];
int ret;
put_unaligned_be16(reg, buf);
buf[2] = val;
buf[3] = val>>8;
ret = i2c_master_send(client, buf, 4);
if ( ret != 4 )
return ret;
return 0;
}
/* Write registers 3 byte at a time */
static int imx585_write_reg_3byte(struct imx585 *imx585, u16 reg, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&imx585->sd);
u8 buf[5];
put_unaligned_be16(reg, buf);
buf[2] = val;
buf[3] = val>>8;
buf[4] = val>>16;
if (i2c_master_send(client, buf, 5) != 5)
return -EIO;
return 0;
}
/* Write a list of 1 byte registers */
static int imx585_write_regs(struct imx585 *imx585,
const struct imx585_reg *regs, u32 len)
{
struct i2c_client *client = v4l2_get_subdevdata(&imx585->sd);
unsigned int i;
int ret;
for (i = 0; i < len; i++) {
ret = imx585_write_reg_1byte(imx585, regs[i].address, regs[i].val);
if (ret) {
dev_err_ratelimited(&client->dev,
"Failed to write reg 0x%4.4x. error = %d\n",
regs[i].address, ret);
return ret;
}
}
return 0;
}
/* Hold register values until hold is disabled */
static inline void imx585_register_hold(struct imx585 *imx585, bool hold)
{
imx585_write_reg_1byte(imx585, 0x3001, hold ? 1 : 0);
}
/* Get bayer order based on flip setting. */
static u32 imx585_get_format_code(struct imx585 *imx585, u32 code)
{
unsigned int i;
lockdep_assert_held(&imx585->mutex);
if(imx585->mono){
for (i = 0; i < ARRAY_SIZE(mono_codes); i++)
if (mono_codes[i] == code)
break;
return mono_codes[i];
}
else{