SPI-60PIN.md

EPD PINOUT (30x2 PIN)

• GDEW1248C63
• GDEW1248T3
• GDEW1248Z95

Reference design

• DESPI-C1248_SCH.pdf

Connector

• FH12-30S-0.5SH

Definition

#	Type	Name	Side	Description	Note
1	I	CS#	M1/M2	(SPI SS) Chip select
2	O	GDR	M1/M2	N-Channel MOS-FET gate drive control
3	P	RESE	M1/M2	Current sense input for control loop	RESE
4	P	VSHR	M1/M2	Positive source driving voltage for RED	Driving voltage
5	O	TSCL		(I2C) Sensor Clock
6	I/O	TSDA		(I2C) Sensor Data
7	I	BS1		Bus selection	BS1
8	O	BUSY#	M1/M2	Busy state output	BUSY
9	I	RST#		Global reset pin	SPI, RES#
10	I	D/C#		(SPI) Data/Command control	SPI, D/C#
11	I	CS#	S1/S2	(SPI SS) Chip select	SPI
12	I	SCL		(SPI SCLK) Serial clock	SPI
13	I/O	SDA		(SPI MOSI) Serial data in	SPI
14	I/O	L/RSYNC	M1/M2	2 + 2 Cascade Sync Signal
15	I/O	M1/M2SYNC	M1/M2	2 + 2 Cascade Sync Signal
16	I/O	M2/M1SYNC	M1/M2	2 + 2 Cascade Sync Signal
17	PWR	VDDIO	M1/M2	(SPI VCC) IO voltage supply
18	PWR	VDD	M1/M2	Corelogic power
19	PWR	VSS	M1/M2	(GND) Digital ground
20	PWR	VDD1.8V	M1/M2	(1.8V) Voltage input & output
21	PWR	VOTP7.5V	M1/M2	(7.5V) OTP program power
22	PWR	VSH	M1/M2	Positive source driving voltage	Driving voltage
23	PWR	VGH	M1/M2	Positive gate driving voltage	Driving voltage
24	PWR	VSL	M1/M2	Negative source driving voltage	Driving voltage
25	PWR	VGL	M1/M2	Negative gate driving voltage	Driving voltage
26	O	VCOM	M1/M2	VCOM output
27	O	BUSY#	S1/S2	Busy state output
28	PWR	VSHR	S1/S2	Positive source driving voltage for RED	Driving voltage
29	PWR	VSH	S1/S2	Positive source driving voltage	Driving voltage
30	PWR	VSL	S1/S2	Positive gate driving voltage	Driving voltage

Cascade

M1	PIN#	PIN#	M2
SCL	12	12	SCL
SDA	13	13	SDA
LSYNC	14	16	M2/M1SYNC
M1/M2SYNC	15	15	M2/M1SYNC
M2/M1SYNC	16	14	RSYNC
VCOM	26	26	VCOM