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jsv.sdc
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jsv.sdc
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#create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
create_clock -period "40.0 MHz" [get_ports MAX10_CLK1_50]
#create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
# SDRAM CLK
create_generated_clock -source [get_pins { sdram|sdram_pll|sd1|pll7|clk[1] }] \
-name clk_dram_ext [get_ports {DRAM_CLK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
#**************************************************************
# suppose +- 100 ps skew
# Board Delay (Data) + Propagation Delay - Board Delay (Clock)
# max 5.4(max) +0.4(trace delay) +0.1 = 5.9
# min 2.7(min) +0.4(trace delay) -0.1 = 3.0
set_input_delay -max -clock clk_dram_ext 5.9 [get_ports DRAM_DQ*]
set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*]
#shift-window
set_multicycle_path -from [get_clocks {clk_dram_ext}] \
-to [get_clocks { sdram|sdram_pll|sd1|pll7|clk[0] }] \
-setup 2