example.parms

// global parameters
global {
	min_data_size = 32       // base reg size
	//base_address = 0x80000000   // block base address
	//use_js_address_alignment = true   // align per jspec reg array and register_set rules
	//suppress_alignment_warnings = true   // inhibit register/regfile base address alignment messages
	//default_base_map_name = "zt"   // default address map name (replaces 'default_name' in cases where no addrmap is specified)
	//debug_mode = "mode1 mode2"       // debug options
	allow_unordered_addresses = false   // attempt to correct order of elements defined in non-descending order
}

// jspec input parameters
input jspec {
	root_regset_is_addrmap = true   // root component will be created as an addrmap rather than a regfile/regset
	//process_typedef = "ea_fo"   // process this typedef 
}

// rdl input parameters  
input rdl {
	//process_component = "yt_fabio_map"   // process this component
    //process_component = "zt_fabio_switch_sopcf0"
    resolve_reg_category = true    // try to determine category from rdl properties if not specified
    //restrict_defined_property_names = true  // user defined rdl properties should always start with 'p_'
    //default_rw_hw_access = true  // default field hw access is rw rather than r
}

// systemverilog output parameters
output systemverilog {
	leaf_address_size = 40             // leaf address bits
	//root_has_leaf_interface = true     // does root module talk directly to leaf  DEPRECATED
    root_decoder_interface = parallel      // parallel | parallel_pulsed | leaf | serial8 | ring8 | ring16 | ring32 | spi_PIO
    //secondary_decoder_interface = serial8      // parallel | parallel_pulsed | serial8 | ring8 | ring16 | ring32 | spi_PIO | none
    //secondary_base_address = 0x40  // base address as viewed from driver of secondary decoder interface 
    //secondary_low_address = 0x50   // low valid address on secondary decoder interfaces
    //secondary_high_address = 0x5f  // high valid address on secondary decoder interfaces
    //secondary_on_child_addrmaps = true  // add secondary interface to child decoders also
	base_addr_is_parameter = false     // base address parameter will be added to top module
	//module_tag = "_version1"         // tag to be added to generated module names
	use_gated_logic_clock = true       // use separate gated clock for registers and generate a clk enable output
	gated_logic_access_delay = 2     // number of clocks after clk enable before gated logic is accessed
	//use_external_select = true         // use an externally generated block select  DEPRECATED
	block_select_mode = always       // is block select generated internally, externally or always
	//export_start_end = true           // create addr_start, addr_end outputs 
	always_generate_iwrap = true     // create int wrapper mod even if none specified in rdl
	suppress_no_reset_warnings = true   // inhibit field no reset messages
	generate_child_addrmaps = true   // generate child address maps
	ring_inter_node_delay = 2             // delay stages added between r16 clients 
	//bbv5_timeout_input = true         // add input port(s) for bb root interface timeout
	include_default_coverage = true   // include default cover points in rtl
	pulse_intr_on_clear = true    // pulse interrupt output low if any child in intr tree is cleared
	reuse_iwrap_structures = true    // reuse similar interface/struct definitions in iwrap
	optimize_parallel_externals = true    // eliminate nack/size/r/w io where possible in parallel external intfs
	use_async_resets = true          // registers will use asynchronous reset
    //nack_partial_writes = true     // issue nack for writes of size less than target
    //write_enable_size = 0          // size of data affected by each write enable in bits
    max_internal_reg_reps = 4096     // maximum allowed replications allowed on an internal register 
    //wrapper_info {
       //add_sync_stages "*intr_o" 1 // add sync delays to these outputs (use default clock)
       //add_sync_stages "*_o" 2 newClk // add 2 stage syncronizer to these outputs w/ new clock
       //add_sync_stages "*_o" 2 newClk mySyncModule // add 2 stage syncronizer to these outputs w/ new clock and module override
    //}
    //separate_iwrap_encap_files = true // generate a separate file for each wrap encap (interface/struct) type
    generate_dv_bind_modules = true   // if true generate diagnostic dv bind modules 
    use_global_dv_bind_controls = false   // if true diagnostic dv bind module settings will be controlled by global packages 
    //include_addr_monitor = true       // generate io to monitor decoder transactions to a specified address range 
    generate_iwrap_xform_modules = false // generate common wrapper transform modules
    //include_sequential_assign_delays = true // include #1 delay on sequential assigns
}

// jspec output parameters
output jspec {
	root_regset_is_instanced = true    // instance the root or make it a typedef?
	//external_decode_is_root = true     // external_decode will be converted to root=true?    DEPRECATED
	//add_js_include = "$ENV{WORKAREA}/$ENV{GENMACROS}/protect/design_spec/func/jspec/protect.jjs" 
    //root_typedef_name="new_typedef"    // override name of root typedef
    //root_instance_name="new_instance"  // override name of root instance
    //root_instance_repeat=3             // override repeat count in root instance
    add_user_param_defines = true     // add user-defined parameter defines to the output
    keep_fset_hierarchy = true     // include fieldset hierarchy in output
}

// pydrvmod output parameters
output pydrvmod {
	default_tag_name = "VER_0"    // override the tag used for default model case (if not specified, root instance name is used)
}

// rdl output parameters  
output rdl {
	root_component_is_instanced = true   // instance the root addrmap/regset or make it a comp definition (not if multi-typedef)?
	output_jspec_attributes = true       // pass attribute definitions from jspec input as-is
	no_root_enum_defs = true             // do not output any enum components defined at root level
}

// reglist output parameters
output reglist {
	display_external_regs = true       // include external regs in output?
	show_reg_type = true              // show int/ext type for each reg?
	//match_instance = "sopf_ints"           // show only regs with matching instance names
	show_fields = false                // show field info for each reg
}

// uvmregs output parameters
output uvmregs {
	//is_mem_threshold = 512   // make replicated regs uvm_mem if reps greater-equal to threshold
	suppress_no_category_warnings = true   // inhibit reg no category messages
	//include_address_coverage = true      // include address coverage in model
	max_reg_coverage_bins = 64   // limit address coverage bins for replicated regs
	reuse_uvm_classes = false     // allow reuse of classes in model
	//skip_no_reset_db_update = false   // bypass uvm_resource_db update for fields with no reset
	//uvm_model_mode = native        // set uvm model type (heavy | lite1 | native)
    //regs_use_factory = true       // registers will be created by and registered with the factory
    //use_numeric_uvm_class_names = true // block and reg class names will use unique int rather than catenated path
	//uvm_mem_strategy = mimic_reg_api   // set uvm_mem modeling strategy (basic | block_wrapped | mimic_reg_api)
	base_address_override = 0x82000000   // model base address override
	use_module_path_defines = true   // use defines for setting root module paths
}

// xml output parameters
output xml {
	include_field_hw_info = true   // include field hw characteristics 
	include_component_info = false   // include component type info in xml output for each instance 
}

// model annotation commands
annotate {
  //set_reg_property cppmod_prune = "true" instances "foo.bar.*" // set parameter on all matching registers
  //set_field_property cppmod_prune = "true" instances "ltpn"      // set parameter on all matching fields
  //set_reg_property external = "DEFAULT" instances "sram" // set parameter on all matching registers
  //set_reg_property js_superset_check = "SS_VALUE" instances "*" // set parameter on all matching registers
  //set_reg_property uvmreg_prune = "true" instances "cntl" // set parameter on all register instances named cntl
  //set_reg_property uvmreg_prune = "true" instances "base_map.eng1.**" // set parameter on all register instances under eng1 instance
  //set_reg_property uvmreg_prune = "true" instances "*.eng1.**" // set parameter on all register instances under eng1 instance 
  //set_regset_property desc = "stuff" instances "fo.str"
  //set_regset_property default uvmreg_prune = "true" components "assist_engine_1" // set parameter on all register instances with component name assist_engine_1
  //set_reg_property uvmreg_prune = "true" components "*.assist_engine_1.**" // set parameter on all register instances with component path *.assist_engine_1.** 
  //set_fieldset_property use_new_interface = "true" instances "foo.blabla.*" // set parameter on all matching fieldsets
}

// testbench output parameters
output bench {
//  add_test_command = "write 32 0x0 0x12345678"  // add a test command to the output bench
//  total_test_time = 10000               // test run time
}