fuse.log

Running: X:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o X:/Xilinx/logicProjectP2V1/final_project_faze1_version2/module_3_4/test_bench_isim_beh.exe -prj X:/Xilinx/logicProjectP2V1/final_project_faze1_version2/module_3_4/test_bench_beh.prj work.test_bench work.glbl 
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Analyzing Verilog file "X:/Xilinx/logicProjectP2V1/final_project_faze1_version2/module_3_4/register.v" into library work
Analyzing Verilog file "X:/Xilinx/logicProjectP2V1/final_project_faze1_version2/module_3_4/controller.v" into library work
Analyzing Verilog file "X:/Xilinx/logicProjectP2V1/final_project_faze1_version2/module_3_4/test_bench.v" into library work
Analyzing Verilog file "X:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Compiling module register
Compiling module controller
Compiling module test_bench
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 4 Verilog Units
Built simulation executable X:/Xilinx/logicProjectP2V1/final_project_faze1_version2/module_3_4/test_bench_isim_beh.exe
Fuse Memory Usage: 27928 KB
Fuse CPU Usage: 2030 ms