There are two ways
- run scripts/build-linux-xlnx-v2020.1-zynqmp-fpga.sh (easy)
- run this chapter step-by-step (annoying)
shell$ git clone https://github.com/Avnet/u96v2-wilc-driver.git
shell$ git clone --depth 1 -b xilinx-v2020.1 https://github.com/Xilinx/linux-xlnx.git linux-xlnx-v2020.1-zynqmp-fpga
shell$ cd linux-xlnx-v2020.1-zynqmp-fpga
shell$ git checkout -b linux-xlnx-v2020.1-zynqmp-fpga refs/tags/xilinx-v2020.1
shell$ patch -p1 < ../files/linux-xlnx-v2020.1-zynqmp-fpga.diff
shell$ git add --update
shell$ git add arch/arm64/boot/dts/xilinx/zynqmp-uz3eg-iocc.dts
shell$ git commit -m "[patch] for linux-xlnx-v2020.1-zynqmp-fpga."
shell$ patch -p1 < ../files/linux-xlnx-v2020.1-builddeb.diff
shell$ git add --update
shell$ git commit -m "[update] scripts/package/builddeb to add tools/include and postinst script to header package."
shell$ patch -p1 < ../files/linux-xlnx-v2020.1-zynqmp-fpga-xilinx_uartps.diff
shell$ git add --update
shell$ git commit -m "[fix] the problem that only the first port that xilinx_uartps.c found was the console."
shell$ cp -r ../u96v2-wilc-driver/wilc drivers/staging/wilc3000/
shell$ patch -p1 < ../files/linux-xlnx-v2020.1-zynqmp-fpga-wilc3000.diff
shell$ git add --update
shell$ git add drivers/staging/wilc3000
shell$ git commit -m "[add] drivers/staging/wilc3000"
shell$ patch -p1 < ../files/linux-xlnx-v2020.1-zynqmp-fpga-ultra96v2.diff
shell$ git add --update
shell$ git add arch/arm64/boot/dts/xilinx/avnet-ultra96v2-rev1.dts
shell$ git commit -m "[add] devicetree for Ultra96-V2."
shell$ patch -p1 < ../files/linux-xlnx-v2020.1-zynqmp-fpga-apf.diff
shell$ git add --update
shell$ git commit -m "[add] Xilinx APF driver."
shell$ git tag -a xilinx-v2020.1-zynqmp-fpga-1 -m "release xilinx-v2020.1-zynqmp-fpga-1"
shell$ echo 1 > .version
shell$ cd linux-xlnx-v2020.1-zynqmp-fpga
shell$ export ARCH=arm64
shell$ export CROSS_COMPILE=aarch64-linux-gnu-
shell$ make xilinx_zynqmp_defconfig
shell$ export DTC_FLAGS=--symbols
shell$ make deb-pkg
shell$ cp arch/arm64/boot/Image ../target/UltraZed-EG-IOCC/boot/image-5.4.0-xlnx-v2020.1-zynqmp-fpga
shell$ cp arch/arm64/boot/dts/xilinx/zynqmp-uz3eg-iocc.dtb ../target/UltraZed-EG-IOCC/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-uz3eg-iocc.dtb
shell$ ./scripts/dtc/dtc -I dtb -O dts --symbols -o ../target/UltraZed-EG-IOCC/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-uz3eg-iocc.dts ../target/UltraZed-EG-IOCC/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-uz3eg-iocc.dtb
shell$ cp arch/arm64/boot/Image ../target/Ultra96/boot/image-5.4.0-xlnx-v2020.1-zynqmp-fpga
shell$ cp arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dtb ../target/Ultra96/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-ultra96.dtb
shell$ ./scripts/dtc/dtc -I dtb -O dts --symbols -o ../target/Ultra96/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-ultra96.dts ../target/Ultra96/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-ultra96.dtb
shell$ cp arch/arm64/boot/Image ../target/Ultra96-V2/boot/image-5.4.0-xlnx-v2020.1-zynqmp-fpga
shell$ cp arch/arm64/boot/dts/xilinx/avnet-ultra96v2-rev1.dtb ../target/Ultra96-V2/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-ultra96v2.dtb
shell$ ./scripts/dtc/dtc -I dtb -O dts --symbols -o ../target/Ultra96-V2/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-ultra96v2.dts ../target/Ultra96-V2/boot/devicetree-5.4.0-xlnx-v2020.1-zynqmp-fpga-ultra96v2.dtb