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PROJECT.flow.rpt
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PROJECT.flow.rpt
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Flow report for PROJECT
Mon Nov 26 11:05:54 2018
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Mon Nov 26 11:05:54 2018 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; PROJECT ;
; Top-level Entity Name ; PROJECT ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Total logic elements ; 3,554 / 33,216 ( 11 % ) ;
; Total combinational functions ; 3,453 / 33,216 ( 10 % ) ;
; Dedicated logic registers ; 1,537 / 33,216 ( 5 % ) ;
; Total registers ; 1537 ;
; Total pins ; 165 / 475 ( 35 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 14,336 / 483,840 ( 3 % ) ;
; Embedded Multiplier 9-bit elements ; 41 / 70 ( 59 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+-------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 11/26/2018 11:04:59 ;
; Main task ; Compilation ;
; Revision Name ; PROJECT ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 58232437182243.154324829814048 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
; VERILOG_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 4666 MB ; 00:00:20 ;
; Fitter ; 00:00:19 ; 1.0 ; 4896 MB ; 00:00:19 ;
; Assembler ; 00:00:03 ; 1.0 ; 4588 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 4597 MB ; 00:00:03 ;
; EDA Netlist Writer ; 00:00:03 ; 1.0 ; 4573 MB ; 00:00:03 ;
; Total ; 00:00:49 ; -- ; -- ; 00:00:47 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-6JKQ8LV ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-6JKQ8LV ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-6JKQ8LV ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-6JKQ8LV ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; DESKTOP-6JKQ8LV ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off PROJECT -c PROJECT
quartus_fit --read_settings_files=off --write_settings_files=off PROJECT -c PROJECT
quartus_asm --read_settings_files=off --write_settings_files=off PROJECT -c PROJECT
quartus_sta PROJECT -c PROJECT
quartus_eda --read_settings_files=off --write_settings_files=off PROJECT -c PROJECT