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PROJECT.sta.rpt
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PROJECT.sta.rpt
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TimeQuest Timing Analyzer report for PROJECT
Mon Nov 26 11:05:50 2018
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow Model Fmax Summary
6. Slow Model Setup Summary
7. Slow Model Hold Summary
8. Slow Model Recovery Summary
9. Slow Model Removal Summary
10. Slow Model Minimum Pulse Width Summary
11. Slow Model Setup: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]'
12. Slow Model Setup: 'CLOCK_50_I'
13. Slow Model Hold: 'CLOCK_50_I'
14. Slow Model Hold: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]'
15. Slow Model Minimum Pulse Width: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]'
16. Slow Model Minimum Pulse Width: 'CLOCK_50_I'
17. Setup Times
18. Hold Times
19. Clock to Output Times
20. Minimum Clock to Output Times
21. Propagation Delay
22. Minimum Propagation Delay
23. Output Enable Times
24. Minimum Output Enable Times
25. Output Disable Times
26. Minimum Output Disable Times
27. Fast Model Setup Summary
28. Fast Model Hold Summary
29. Fast Model Recovery Summary
30. Fast Model Removal Summary
31. Fast Model Minimum Pulse Width Summary
32. Fast Model Setup: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]'
33. Fast Model Setup: 'CLOCK_50_I'
34. Fast Model Hold: 'CLOCK_50_I'
35. Fast Model Hold: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]'
36. Fast Model Minimum Pulse Width: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]'
37. Fast Model Minimum Pulse Width: 'CLOCK_50_I'
38. Setup Times
39. Hold Times
40. Clock to Output Times
41. Minimum Clock to Output Times
42. Propagation Delay
43. Minimum Propagation Delay
44. Output Enable Times
45. Minimum Output Enable Times
46. Output Disable Times
47. Minimum Output Disable Times
48. Multicorner Timing Analysis Summary
49. Setup Times
50. Hold Times
51. Clock to Output Times
52. Minimum Clock to Output Times
53. Progagation Delay
54. Minimum Progagation Delay
55. Setup Transfers
56. Hold Transfers
57. Report TCCS
58. Report RSKM
59. Unconstrained Paths
60. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name ; PROJECT ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+----------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+------------------------------------------------------------+--------------------------------------------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+----------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+------------------------------------------------------------+--------------------------------------------------------------+
; CLOCK_50_I ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50_I } ;
; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Generated ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; 50.00 ; 1 ; 2 ; ; ; ; ; false ; CLOCK_50_I ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|inclk[0] ; { SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] } ;
+----------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+------------------------------------------------------------+--------------------------------------------------------------+
+-------------------------------------------------+
; Slow Model Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 62.29 MHz ; 62.29 MHz ; CLOCK_50_I ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+----------------------------------------------------------------------------------+
; Slow Model Setup Summary ;
+----------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; 2.096 ; 0.000 ;
; CLOCK_50_I ; 3.946 ; 0.000 ;
+----------------------------------------------------------+-------+---------------+
+----------------------------------------------------------------------------------+
; Slow Model Hold Summary ;
+----------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; CLOCK_50_I ; 0.391 ; 0.000 ;
; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; 7.674 ; 0.000 ;
+----------------------------------------------------------+-------+---------------+
-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.
------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.
+----------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary ;
+----------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; 4.000 ; 0.000 ;
; CLOCK_50_I ; 7.500 ; 0.000 ;
+----------------------------------------------------------+-------+---------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]' ;
+-------+------------+---------------------------------------+--------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------+---------------------------------------+--------------+----------------------------------------------------------+--------------+------------+------------+
; 2.096 ; CLOCK_50_I ; SRAM_Controller:SRAM_unit|SRAM_LB_N_O ; CLOCK_50_I ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; 5.000 ; 0.256 ; 3.196 ;
; 2.096 ; CLOCK_50_I ; SRAM_Controller:SRAM_unit|SRAM_LB_N_O ; CLOCK_50_I ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; 5.000 ; 0.256 ; 3.196 ;
+-------+------------+---------------------------------------+--------------+----------------------------------------------------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLOCK_50_I' ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 3.946 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.074 ; 16.016 ;
; 3.946 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.074 ; 16.016 ;
; 3.946 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.074 ; 16.016 ;
; 3.946 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.074 ; 16.016 ;
; 3.946 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.074 ; 16.016 ;
; 3.946 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.074 ; 16.016 ;
; 3.946 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.074 ; 16.016 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_we_reg ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 3.985 ; Milestone_2:M2_unit|dual_port_RAM1:dual_port_RAM_inst1|altsyncram:altsyncram_component|altsyncram_uq92:auto_generated|ram_block1a0~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[3][26] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.067 ; 15.984 ;
; 4.287 ; Milestone_1:M1_unit|Y_RGB[7] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|R_buff[0] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.021 ; 15.728 ;
; 4.291 ; Milestone_1:M1_unit|Y_RGB[7] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|B_buff[1] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.021 ; 15.724 ;
; 4.328 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.093 ; 15.615 ;
; 4.328 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.093 ; 15.615 ;
; 4.328 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.093 ; 15.615 ;
; 4.328 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.093 ; 15.615 ;
; 4.328 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.093 ; 15.615 ;
; 4.328 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.093 ; 15.615 ;
; 4.328 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.093 ; 15.615 ;
; 4.363 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.054 ; 15.619 ;
; 4.363 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.054 ; 15.619 ;
; 4.363 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.054 ; 15.619 ;
; 4.363 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.054 ; 15.619 ;
; 4.363 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.054 ; 15.619 ;
; 4.363 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.054 ; 15.619 ;
; 4.363 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.054 ; 15.619 ;
; 4.375 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.110 ; 15.551 ;
; 4.375 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.110 ; 15.551 ;
; 4.375 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.110 ; 15.551 ;
; 4.375 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.110 ; 15.551 ;
; 4.375 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.110 ; 15.551 ;
; 4.375 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.110 ; 15.551 ;
; 4.375 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.110 ; 15.551 ;
; 4.377 ; Milestone_1:M1_unit|V_RGB[7] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|R_buff[0] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; 0.025 ; 15.684 ;
; 4.381 ; Milestone_1:M1_unit|V_RGB[7] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|B_buff[1] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; 0.025 ; 15.680 ;
; 4.460 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.066 ; 15.510 ;
; 4.460 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.066 ; 15.510 ;
; 4.460 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.066 ; 15.510 ;
; 4.460 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.066 ; 15.510 ;
; 4.460 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.066 ; 15.510 ;
; 4.460 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.066 ; 15.510 ;
; 4.460 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][29] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.066 ; 15.510 ;
; 4.461 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.059 ; 15.516 ;
; 4.461 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.059 ; 15.516 ;
; 4.461 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.059 ; 15.516 ;
; 4.461 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.059 ; 15.516 ;
; 4.461 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.059 ; 15.516 ;
; 4.461 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.059 ; 15.516 ;
; 4.461 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.059 ; 15.516 ;
; 4.474 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.053 ; 15.509 ;
; 4.474 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.053 ; 15.509 ;
; 4.474 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.053 ; 15.509 ;
; 4.474 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.053 ; 15.509 ;
; 4.474 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.053 ; 15.509 ;
; 4.474 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.053 ; 15.509 ;
; 4.474 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.053 ; 15.509 ;
; 4.504 ; Milestone_1:M1_unit|V_RGB[8] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|R_buff[0] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; 0.025 ; 15.557 ;
; 4.508 ; Milestone_1:M1_unit|V_RGB[8] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|B_buff[1] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; 0.025 ; 15.553 ;
; 4.520 ; Milestone_1:M1_unit|Y_RGB[4] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|R_buff[0] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.007 ; 15.509 ;
; 4.524 ; Milestone_1:M1_unit|Y_RGB[4] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|B_buff[1] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.007 ; 15.505 ;
; 4.539 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.083 ; 15.414 ;
; 4.539 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.083 ; 15.414 ;
; 4.539 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.083 ; 15.414 ;
; 4.539 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.083 ; 15.414 ;
; 4.539 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.083 ; 15.414 ;
; 4.539 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.083 ; 15.414 ;
; 4.539 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~portb_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[2][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.083 ; 15.414 ;
; 4.548 ; Milestone_1:M1_unit|Y_RGB[7] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|R_buff[5] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.018 ; 15.470 ;
; 4.551 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.049 ; 15.436 ;
; 4.551 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.049 ; 15.436 ;
; 4.551 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.049 ; 15.436 ;
; 4.551 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.049 ; 15.436 ;
; 4.551 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.049 ; 15.436 ;
; 4.551 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.049 ; 15.436 ;
; 4.551 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][31] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.049 ; 15.436 ;
; 4.555 ; Milestone_1:M1_unit|Y_RGB[7] ; Milestone_1:M1_unit|RGB_Converter:RGB_unit|R_buff[4] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.018 ; 15.463 ;
; 4.558 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.071 ; 15.407 ;
; 4.558 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.071 ; 15.407 ;
; 4.558 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.071 ; 15.407 ;
; 4.558 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.071 ; 15.407 ;
; 4.558 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.071 ; 15.407 ;
; 4.558 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.071 ; 15.407 ;
; 4.558 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.071 ; 15.407 ;
; 4.569 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[1][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.045 ; 15.422 ;
; 4.569 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[1][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.045 ; 15.422 ;
; 4.569 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[1][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.045 ; 15.422 ;
; 4.569 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[1][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.045 ; 15.422 ;
; 4.569 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[1][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.045 ; 15.422 ;
; 4.569 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg5 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[1][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.045 ; 15.422 ;
; 4.569 ; Milestone_2:M2_unit|dual_port_RAM2:dual_port_RAM_inst2|altsyncram:altsyncram_component|altsyncram_vq92:auto_generated|ram_block1a0~porta_address_reg6 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|product[1][30] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.045 ; 15.422 ;
; 4.571 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg0 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.065 ; 15.400 ;
; 4.571 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg1 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.065 ; 15.400 ;
; 4.571 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.065 ; 15.400 ;
; 4.571 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg3 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.065 ; 15.400 ;
; 4.571 ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a4~porta_address_reg4 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|product[0][28] ; CLOCK_50_I ; CLOCK_50_I ; 20.000 ; -0.065 ; 15.400 ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLOCK_50_I' ;
+-------+------------------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.391 ; Milestone_1:M1_unit|read_end_Y ; Milestone_1:M1_unit|read_end_Y ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|M1_done ; Milestone_1:M1_unit|M1_done ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; M2_start ; M2_start ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|state.S_M2_IDLE ; Milestone_2:M2_unit|state.S_M2_IDLE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|WS_done ; Milestone_2:M2_unit|WS:WS_unit|WS_done ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; state.S_TOP_IDLE ; state.S_TOP_IDLE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|first_run ; Milestone_2:M2_unit|Milestone_3:M3_unit|first_run ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|common_case ; Milestone_1:M1_unit|common_case ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|enable_RGB ; Milestone_1:M1_unit|enable_RGB ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|line_start ; Milestone_1:M1_unit|line_start ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|FIR:FIR_unit|sel_mul_in.01 ; Milestone_1:M1_unit|FIR:FIR_unit|sel_mul_in.01 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|FIR:FIR_unit|sel_mul_in.10 ; Milestone_1:M1_unit|FIR:FIR_unit|sel_mul_in.10 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|FIR:FIR_unit|sel_mul_in.11 ; Milestone_1:M1_unit|FIR:FIR_unit|sel_mul_in.11 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|FIR:FIR_unit|U_V ; Milestone_1:M1_unit|FIR:FIR_unit|U_V ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|clear_SReg ; Milestone_1:M1_unit|clear_SReg ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|line_end ; Milestone_1:M1_unit|line_end ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|read_U_0 ; Milestone_1:M1_unit|read_U_0 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|enable_V ; Milestone_1:M1_unit|enable_V ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|read_V_0 ; Milestone_1:M1_unit|read_V_0 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|cycle ; Milestone_1:M1_unit|cycle ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|load_U_buffer ; Milestone_1:M1_unit|load_U_buffer ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|first_run ; Milestone_2:M2_unit|WS:WS_unit|first_run ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_1:M1_unit|SRAM_we_n ; Milestone_1:M1_unit|SRAM_we_n ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_SReg[3] ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_SReg[3] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_SReg[4] ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_SReg[4] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_SReg[47] ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_SReg[47] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[5] ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[5] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[4] ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[4] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[3] ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[3] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[2] ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[2] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[0] ; Milestone_2:M2_unit|Milestone_3:M3_unit|ZZ_position[0] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_READ_DEAD ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_READ_DEAD ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|Num_write_cycles[0] ; Milestone_2:M2_unit|Milestone_3:M3_unit|Num_write_cycles[0] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|Num_write_cycles[1] ; Milestone_2:M2_unit|Milestone_3:M3_unit|Num_write_cycles[1] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|Num_write_cycles[2] ; Milestone_2:M2_unit|Milestone_3:M3_unit|Num_write_cycles[2] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_READ_BEEF ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_READ_BEEF ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|Q_matrix ; Milestone_2:M2_unit|Milestone_3:M3_unit|Q_matrix ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[14] ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[14] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|first_run ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|first_run ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|state.S_MM_CC ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|state.S_MM_CC ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|first_run ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|first_run ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[2] ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[2] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[1] ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[1] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[0] ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[0] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_enable ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_enable ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[13] ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[13] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[10] ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[10] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[4] ; Milestone_2:M2_unit|Milestone_3:M3_unit|RAM3_write_data[4] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|P_write_enable ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|P_write_enable ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|P_write_enable ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|P_write_enable ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_READ_WIDTH ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_READ_WIDTH ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|SReg_end[4] ; Milestone_2:M2_unit|Milestone_3:M3_unit|SReg_end[4] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_done ; Milestone_2:M2_unit|Milestone_3:M3_unit|M3_done ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|state.S_CS ; Milestone_2:M2_unit|state.S_CS ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|M3_start ; Milestone_2:M2_unit|M3_start ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_IDLE ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_IDLE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|state.S_MM_IDLE ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|state.S_MM_IDLE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|state.S_MM_LO_2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|state.S_MM_LO_2 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|MM_done ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CT|MM_done ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MM_CS_start ; Milestone_2:M2_unit|MM_CS_start ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|state.S_MM_CC ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|state.S_MM_CC ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|state.S_MM_LO_2 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|state.S_MM_LO_2 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|state.S_MM_IDLE ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|state.S_MM_IDLE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|MM_done ; Milestone_2:M2_unit|MATRIX_MULTIPLIER:MM_unit_CS|MM_done ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|state.S_FS ; Milestone_2:M2_unit|state.S_FS ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS_start ; Milestone_2:M2_unit|WS_start ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|state.S_WS_IDLE ; Milestone_2:M2_unit|WS:WS_unit|state.S_WS_IDLE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|RB[1] ; Milestone_2:M2_unit|WS:WS_unit|RB[1] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|C_END[4] ; Milestone_2:M2_unit|WS:WS_unit|C_END[4] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|CB[0] ; Milestone_2:M2_unit|WS:WS_unit|CB[0] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|Base_address[13] ; Milestone_2:M2_unit|WS:WS_unit|Base_address[13] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|Base_address[10] ; Milestone_2:M2_unit|WS:WS_unit|Base_address[10] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|Base_address[15] ; Milestone_2:M2_unit|WS:WS_unit|Base_address[15] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|WS:WS_unit|WS_memory_end ; Milestone_2:M2_unit|WS:WS_unit|WS_memory_end ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; Milestone_2:M2_unit|M2_done ; Milestone_2:M2_unit|M2_done ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; state.S_TOP_M2 ; state.S_TOP_M2 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; start_counter[0] ; start_counter[0] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; start_counter[1] ; start_counter[1] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; start_counter[2] ; start_counter[2] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; start_counter[3] ; start_counter[3] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; state.S_TOP_M1 ; state.S_TOP_M1 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; M1_start ; M1_start ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_STRIP_FILE_HEADER_2 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_STRIP_FILE_HEADER_2 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_STRIP_FILE_HEADER_1 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_STRIP_FILE_HEADER_1 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_START_FIRST_BYTE_RECEIVE ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_START_FIRST_BYTE_RECEIVE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_WRITE_FIRST_BYTE ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_WRITE_FIRST_BYTE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_START_SECOND_BYTE_RECEIVE ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_START_SECOND_BYTE_RECEIVE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_IDLE ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_IDLE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_rx_unload_data ; UART_SRAM_interface:UART_unit|UART_rx_unload_data ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_Receive_Controller:UART_RX|Empty ; UART_SRAM_interface:UART_unit|UART_Receive_Controller:UART_RX|Empty ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_WRITE_SECOND_BYTE ; UART_SRAM_interface:UART_unit|UART_SRAM_state.S_US_WRITE_SECOND_BYTE ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; VGA_SRAM_interface:VGA_unit|VGA_Controller:VGA_unit|counter_enable ; VGA_SRAM_interface:VGA_unit|VGA_Controller:VGA_unit|counter_enable ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; VGA_SRAM_interface:VGA_unit|VGA_SRAM_state.S_VS_WAIT_NEW_PIXEL_ROW ; VGA_SRAM_interface:VGA_unit|VGA_SRAM_state.S_VS_WAIT_NEW_PIXEL_ROW ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; VGA_SRAM_interface:VGA_unit|VGA_Controller:VGA_unit|oVGA_V_SYNC ; VGA_SRAM_interface:VGA_unit|VGA_Controller:VGA_unit|oVGA_V_SYNC ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.391 ; VGA_SRAM_interface:VGA_unit|VGA_blue[0] ; VGA_SRAM_interface:VGA_unit|VGA_blue[0] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.657 ;
; 0.517 ; Milestone_1:M1_unit|FIR:FIR_unit|FIR_BUFF_U[23] ; Milestone_1:M1_unit|U_RGB[23] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.783 ;
; 0.517 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_LI_2 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_LI_3 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.783 ;
; 0.517 ; VGA_SRAM_interface:VGA_unit|VGA_blue[0] ; VGA_SRAM_interface:VGA_unit|VGA_Controller:VGA_unit|oVGA_R[0] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.783 ;
; 0.519 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_LI_H2 ; Milestone_2:M2_unit|Milestone_3:M3_unit|state.S_M3_LI_H3 ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.785 ;
; 0.520 ; Milestone_1:M1_unit|FIR:FIR_unit|U_in_buffer[0][6] ; Milestone_1:M1_unit|FIR:FIR_unit|U_SReg[0][6] ; CLOCK_50_I ; CLOCK_50_I ; 0.000 ; 0.000 ; 0.786 ;
+-------+------------------------------------------------------------------------------+------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]' ;
+-------+------------+---------------------------------------+--------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------+---------------------------------------+--------------+----------------------------------------------------------+--------------+------------+------------+
; 7.674 ; CLOCK_50_I ; SRAM_Controller:SRAM_unit|SRAM_LB_N_O ; CLOCK_50_I ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; -5.000 ; 0.256 ; 3.196 ;
; 7.674 ; CLOCK_50_I ; SRAM_Controller:SRAM_unit|SRAM_LB_N_O ; CLOCK_50_I ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; -5.000 ; 0.256 ; 3.196 ;
+-------+------------+---------------------------------------+--------------+----------------------------------------------------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0]' ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------+
; 4.000 ; 5.000 ; 1.000 ; High Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Fall ; SRAM_Controller:SRAM_unit|SRAM_LB_N_O ;
; 4.000 ; 5.000 ; 1.000 ; Low Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Fall ; SRAM_Controller:SRAM_unit|SRAM_LB_N_O ;
; 5.000 ; 5.000 ; 0.000 ; High Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Rise ; SRAM_unit|Clock_100_PLL_inst|altpll_component|_clk0~clkctrl|inclk[0] ;
; 5.000 ; 5.000 ; 0.000 ; Low Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Rise ; SRAM_unit|Clock_100_PLL_inst|altpll_component|_clk0~clkctrl|inclk[0] ;
; 5.000 ; 5.000 ; 0.000 ; High Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Rise ; SRAM_unit|Clock_100_PLL_inst|altpll_component|_clk0~clkctrl|outclk ;
; 5.000 ; 5.000 ; 0.000 ; Low Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Rise ; SRAM_unit|Clock_100_PLL_inst|altpll_component|_clk0~clkctrl|outclk ;
; 5.000 ; 5.000 ; 0.000 ; High Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Rise ; SRAM_unit|SRAM_LB_N_O|clk ;
; 5.000 ; 5.000 ; 0.000 ; Low Pulse Width ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ; Rise ; SRAM_unit|SRAM_LB_N_O|clk ;
+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+----------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLOCK_50_I' ;
+-------+--------------+----------------+------------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+-------+--------------+----------------+------------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_address_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg16 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg16 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg17 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg17 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg7 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg7 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg8 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg8 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg9 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_datain_reg9 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_memory_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~porta_memory_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_address_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg0 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg1 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg10 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg10 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg11 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg11 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg12 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg12 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg13 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg13 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg14 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg14 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg15 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg15 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg16 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg16 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg17 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg17 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg2 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg3 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg4 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg5 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg6 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg7 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg7 ;
; 7.500 ; 10.000 ; 2.500 ; High Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg8 ;
; 7.500 ; 10.000 ; 2.500 ; Low Pulse Width ; CLOCK_50_I ; Rise ; Milestone_2:M2_unit|Milestone_3:M3_unit|dual_port_RAM3:dual_port_RAM_inst3|altsyncram:altsyncram_component|altsyncram_0r92:auto_generated|ram_block1a0~portb_datain_reg8 ;
+-------+--------------+----------------+------------------+------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Setup Times ;
+-------------------+------------+-------+-------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-------------------+------------+-------+-------+------------+----------------------------------------------------------+
; SRAM_DATA_IO[*] ; CLOCK_50_I ; 4.412 ; 4.412 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; 4.320 ; 4.320 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; 4.031 ; 4.031 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; 4.394 ; 4.394 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; 4.000 ; 4.000 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; 3.743 ; 3.743 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; 4.064 ; 4.064 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; 4.019 ; 4.019 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; 3.797 ; 3.797 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; 3.845 ; 3.845 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[9] ; CLOCK_50_I ; 3.814 ; 3.814 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[10] ; CLOCK_50_I ; 4.073 ; 4.073 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[11] ; CLOCK_50_I ; 4.194 ; 4.194 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[12] ; CLOCK_50_I ; 4.166 ; 4.166 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[13] ; CLOCK_50_I ; 4.058 ; 4.058 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[14] ; CLOCK_50_I ; 4.412 ; 4.412 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[15] ; CLOCK_50_I ; 4.116 ; 4.116 ; Rise ; CLOCK_50_I ;
; SWITCH_I[*] ; CLOCK_50_I ; 9.042 ; 9.042 ; Rise ; CLOCK_50_I ;
; SWITCH_I[17] ; CLOCK_50_I ; 9.042 ; 9.042 ; Rise ; CLOCK_50_I ;
; CLOCK_50_I ; CLOCK_50_I ; 2.904 ; 2.904 ; Fall ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ;
+-------------------+------------+-------+-------+------------+----------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Hold Times ;
+-------------------+------------+--------+--------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-------------------+------------+--------+--------+------------+----------------------------------------------------------+
; SRAM_DATA_IO[*] ; CLOCK_50_I ; -3.513 ; -3.513 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; -4.090 ; -4.090 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; -3.801 ; -3.801 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; -4.164 ; -4.164 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; -3.770 ; -3.770 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; -3.513 ; -3.513 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; -3.834 ; -3.834 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; -3.789 ; -3.789 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; -3.567 ; -3.567 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; -3.615 ; -3.615 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[9] ; CLOCK_50_I ; -3.584 ; -3.584 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[10] ; CLOCK_50_I ; -3.843 ; -3.843 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[11] ; CLOCK_50_I ; -3.964 ; -3.964 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[12] ; CLOCK_50_I ; -3.936 ; -3.936 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[13] ; CLOCK_50_I ; -3.828 ; -3.828 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[14] ; CLOCK_50_I ; -4.182 ; -4.182 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[15] ; CLOCK_50_I ; -3.886 ; -3.886 ; Rise ; CLOCK_50_I ;
; SWITCH_I[*] ; CLOCK_50_I ; -5.894 ; -5.894 ; Rise ; CLOCK_50_I ;
; SWITCH_I[17] ; CLOCK_50_I ; -5.894 ; -5.894 ; Rise ; CLOCK_50_I ;
; CLOCK_50_I ; CLOCK_50_I ; -2.674 ; -2.674 ; Fall ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ;
+-------------------+------------+--------+--------+------------+----------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------+------------+--------+--------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+--------------------------+------------+--------+--------+------------+----------------------------------------------------------+
; SEVEN_SEGMENT_N_O[0][*] ; CLOCK_50_I ; 15.354 ; 15.354 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][0] ; CLOCK_50_I ; 15.354 ; 15.354 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][1] ; CLOCK_50_I ; 15.298 ; 15.298 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][2] ; CLOCK_50_I ; 15.310 ; 15.310 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][3] ; CLOCK_50_I ; 15.071 ; 15.071 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][4] ; CLOCK_50_I ; 15.120 ; 15.120 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][5] ; CLOCK_50_I ; 15.032 ; 15.032 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][6] ; CLOCK_50_I ; 15.070 ; 15.070 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][*] ; CLOCK_50_I ; 16.177 ; 16.177 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][0] ; CLOCK_50_I ; 16.177 ; 16.177 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][1] ; CLOCK_50_I ; 15.263 ; 15.263 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][2] ; CLOCK_50_I ; 15.679 ; 15.679 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][3] ; CLOCK_50_I ; 14.962 ; 14.962 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][4] ; CLOCK_50_I ; 15.501 ; 15.501 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][5] ; CLOCK_50_I ; 15.227 ; 15.227 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][6] ; CLOCK_50_I ; 15.736 ; 15.736 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][*] ; CLOCK_50_I ; 15.917 ; 15.917 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][0] ; CLOCK_50_I ; 14.560 ; 14.560 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][1] ; CLOCK_50_I ; 15.917 ; 15.917 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][2] ; CLOCK_50_I ; 14.828 ; 14.828 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][3] ; CLOCK_50_I ; 14.796 ; 14.796 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][4] ; CLOCK_50_I ; 15.622 ; 15.622 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][5] ; CLOCK_50_I ; 14.833 ; 14.833 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][6] ; CLOCK_50_I ; 15.448 ; 15.448 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][*] ; CLOCK_50_I ; 15.084 ; 15.084 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][0] ; CLOCK_50_I ; 15.077 ; 15.077 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][2] ; CLOCK_50_I ; 14.780 ; 14.780 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][3] ; CLOCK_50_I ; 15.084 ; 15.084 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][4] ; CLOCK_50_I ; 14.416 ; 14.416 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][5] ; CLOCK_50_I ; 14.663 ; 14.663 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][6] ; CLOCK_50_I ; 11.824 ; 11.824 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][*] ; CLOCK_50_I ; 9.719 ; 9.719 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][0] ; CLOCK_50_I ; 9.460 ; 9.460 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][1] ; CLOCK_50_I ; 9.719 ; 9.719 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][2] ; CLOCK_50_I ; 9.619 ; 9.619 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][3] ; CLOCK_50_I ; 9.678 ; 9.678 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][4] ; CLOCK_50_I ; 9.440 ; 9.440 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][5] ; CLOCK_50_I ; 9.588 ; 9.588 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][6] ; CLOCK_50_I ; 9.327 ; 9.327 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][*] ; CLOCK_50_I ; 8.643 ; 8.643 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][0] ; CLOCK_50_I ; 8.390 ; 8.390 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][1] ; CLOCK_50_I ; 8.621 ; 8.621 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][2] ; CLOCK_50_I ; 8.624 ; 8.624 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][3] ; CLOCK_50_I ; 8.269 ; 8.269 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][4] ; CLOCK_50_I ; 8.067 ; 8.067 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][5] ; CLOCK_50_I ; 8.074 ; 8.074 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][6] ; CLOCK_50_I ; 8.643 ; 8.643 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][*] ; CLOCK_50_I ; 9.298 ; 9.298 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][0] ; CLOCK_50_I ; 8.700 ; 8.700 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][1] ; CLOCK_50_I ; 8.444 ; 8.444 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][2] ; CLOCK_50_I ; 8.458 ; 8.458 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][3] ; CLOCK_50_I ; 8.883 ; 8.883 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][4] ; CLOCK_50_I ; 9.298 ; 9.298 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][5] ; CLOCK_50_I ; 9.034 ; 9.034 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][6] ; CLOCK_50_I ; 9.068 ; 9.068 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][*] ; CLOCK_50_I ; 11.824 ; 11.824 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][0] ; CLOCK_50_I ; 10.818 ; 10.818 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][1] ; CLOCK_50_I ; 10.268 ; 10.268 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][2] ; CLOCK_50_I ; 11.824 ; 11.824 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][3] ; CLOCK_50_I ; 10.317 ; 10.317 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][4] ; CLOCK_50_I ; 10.522 ; 10.522 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][5] ; CLOCK_50_I ; 10.348 ; 10.348 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][6] ; CLOCK_50_I ; 10.980 ; 10.980 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[*] ; CLOCK_50_I ; 9.158 ; 9.158 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[0] ; CLOCK_50_I ; 9.158 ; 9.158 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[1] ; CLOCK_50_I ; 8.801 ; 8.801 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[2] ; CLOCK_50_I ; 8.505 ; 8.505 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[3] ; CLOCK_50_I ; 8.471 ; 8.471 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[4] ; CLOCK_50_I ; 8.749 ; 8.749 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[5] ; CLOCK_50_I ; 8.805 ; 8.805 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[6] ; CLOCK_50_I ; 8.175 ; 8.175 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[7] ; CLOCK_50_I ; 8.496 ; 8.496 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[8] ; CLOCK_50_I ; 8.274 ; 8.274 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[9] ; CLOCK_50_I ; 9.035 ; 9.035 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[10] ; CLOCK_50_I ; 8.247 ; 8.247 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[11] ; CLOCK_50_I ; 8.947 ; 8.947 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[12] ; CLOCK_50_I ; 8.748 ; 8.748 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[13] ; CLOCK_50_I ; 8.990 ; 8.990 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[14] ; CLOCK_50_I ; 7.832 ; 7.832 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[15] ; CLOCK_50_I ; 8.437 ; 8.437 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[16] ; CLOCK_50_I ; 9.044 ; 9.044 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[17] ; CLOCK_50_I ; 9.001 ; 9.001 ; Rise ; CLOCK_50_I ;
; SRAM_CE_N_O ; CLOCK_50_I ; 8.398 ; 8.398 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[*] ; CLOCK_50_I ; 8.712 ; 8.712 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; 8.562 ; 8.562 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; 8.542 ; 8.542 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; 8.205 ; 8.205 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; 8.474 ; 8.474 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; 8.387 ; 8.387 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; 8.398 ; 8.398 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; 8.359 ; 8.359 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; 8.264 ; 8.264 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; 8.262 ; 8.262 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[9] ; CLOCK_50_I ; 8.289 ; 8.289 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[10] ; CLOCK_50_I ; 8.081 ; 8.081 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[11] ; CLOCK_50_I ; 8.712 ; 8.712 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[12] ; CLOCK_50_I ; 8.604 ; 8.604 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[13] ; CLOCK_50_I ; 8.639 ; 8.639 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[14] ; CLOCK_50_I ; 8.352 ; 8.352 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[15] ; CLOCK_50_I ; 8.349 ; 8.349 ; Rise ; CLOCK_50_I ;
; SRAM_OE_N_O ; CLOCK_50_I ; 8.398 ; 8.398 ; Rise ; CLOCK_50_I ;
; SRAM_WE_N_O ; CLOCK_50_I ; 7.872 ; 7.872 ; Rise ; CLOCK_50_I ;
; VGA_BLANK_O ; CLOCK_50_I ; 9.099 ; 9.099 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[*] ; CLOCK_50_I ; 7.910 ; 7.910 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[0] ; CLOCK_50_I ; 7.272 ; 7.272 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[1] ; CLOCK_50_I ; 7.275 ; 7.275 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[2] ; CLOCK_50_I ; 7.504 ; 7.504 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[3] ; CLOCK_50_I ; 7.489 ; 7.489 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[4] ; CLOCK_50_I ; 7.910 ; 7.910 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[5] ; CLOCK_50_I ; 7.555 ; 7.555 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[6] ; CLOCK_50_I ; 7.543 ; 7.543 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[7] ; CLOCK_50_I ; 7.538 ; 7.538 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[8] ; CLOCK_50_I ; 7.746 ; 7.746 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[9] ; CLOCK_50_I ; 7.746 ; 7.746 ; Rise ; CLOCK_50_I ;
; VGA_CLOCK_O ; CLOCK_50_I ; 6.464 ; 6.464 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[*] ; CLOCK_50_I ; 7.948 ; 7.948 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[0] ; CLOCK_50_I ; 7.526 ; 7.526 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[1] ; CLOCK_50_I ; 7.507 ; 7.507 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[2] ; CLOCK_50_I ; 7.814 ; 7.814 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[3] ; CLOCK_50_I ; 7.813 ; 7.813 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[4] ; CLOCK_50_I ; 7.377 ; 7.377 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[5] ; CLOCK_50_I ; 7.948 ; 7.948 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[6] ; CLOCK_50_I ; 7.565 ; 7.565 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[7] ; CLOCK_50_I ; 7.603 ; 7.603 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[8] ; CLOCK_50_I ; 7.611 ; 7.611 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[9] ; CLOCK_50_I ; 7.295 ; 7.295 ; Rise ; CLOCK_50_I ;
; VGA_HSYNC_O ; CLOCK_50_I ; 8.286 ; 8.286 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[*] ; CLOCK_50_I ; 8.186 ; 8.186 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[0] ; CLOCK_50_I ; 7.957 ; 7.957 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[1] ; CLOCK_50_I ; 7.946 ; 7.946 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[2] ; CLOCK_50_I ; 8.015 ; 8.015 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[3] ; CLOCK_50_I ; 8.186 ; 8.186 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[4] ; CLOCK_50_I ; 7.959 ; 7.959 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[5] ; CLOCK_50_I ; 7.760 ; 7.760 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[6] ; CLOCK_50_I ; 7.782 ; 7.782 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[7] ; CLOCK_50_I ; 7.791 ; 7.791 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[8] ; CLOCK_50_I ; 7.730 ; 7.730 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[9] ; CLOCK_50_I ; 7.756 ; 7.756 ; Rise ; CLOCK_50_I ;
; VGA_VSYNC_O ; CLOCK_50_I ; 8.275 ; 8.275 ; Rise ; CLOCK_50_I ;
; VGA_CLOCK_O ; CLOCK_50_I ; 6.464 ; 6.464 ; Fall ; CLOCK_50_I ;
; SRAM_LB_N_O ; CLOCK_50_I ; 5.891 ; 5.891 ; Fall ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ;
; SRAM_UB_N_O ; CLOCK_50_I ; 5.891 ; 5.891 ; Fall ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ;
+--------------------------+------------+--------+--------+------------+----------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------+------------+--------+--------+------------+----------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+--------------------------+------------+--------+--------+------------+----------------------------------------------------------+
; SEVEN_SEGMENT_N_O[0][*] ; CLOCK_50_I ; 9.346 ; 9.346 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][0] ; CLOCK_50_I ; 9.641 ; 9.641 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][1] ; CLOCK_50_I ; 9.582 ; 9.582 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][2] ; CLOCK_50_I ; 9.595 ; 9.595 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][3] ; CLOCK_50_I ; 9.368 ; 9.368 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][4] ; CLOCK_50_I ; 9.421 ; 9.421 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][5] ; CLOCK_50_I ; 9.346 ; 9.346 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[0][6] ; CLOCK_50_I ; 9.362 ; 9.362 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][*] ; CLOCK_50_I ; 10.068 ; 10.068 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][0] ; CLOCK_50_I ; 11.284 ; 11.284 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][1] ; CLOCK_50_I ; 10.361 ; 10.361 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][2] ; CLOCK_50_I ; 10.802 ; 10.802 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][3] ; CLOCK_50_I ; 10.068 ; 10.068 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][4] ; CLOCK_50_I ; 10.609 ; 10.609 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][5] ; CLOCK_50_I ; 10.336 ; 10.336 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[1][6] ; CLOCK_50_I ; 10.830 ; 10.830 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][*] ; CLOCK_50_I ; 9.591 ; 9.591 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][0] ; CLOCK_50_I ; 9.591 ; 9.591 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][1] ; CLOCK_50_I ; 10.932 ; 10.932 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][2] ; CLOCK_50_I ; 9.804 ; 9.804 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][3] ; CLOCK_50_I ; 9.810 ; 9.810 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][4] ; CLOCK_50_I ; 10.635 ; 10.635 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][5] ; CLOCK_50_I ; 9.832 ; 9.832 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[2][6] ; CLOCK_50_I ; 10.455 ; 10.455 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][*] ; CLOCK_50_I ; 9.445 ; 9.445 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][0] ; CLOCK_50_I ; 10.609 ; 10.609 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][2] ; CLOCK_50_I ; 10.317 ; 10.317 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][3] ; CLOCK_50_I ; 10.616 ; 10.616 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][4] ; CLOCK_50_I ; 9.705 ; 9.705 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][5] ; CLOCK_50_I ; 10.200 ; 10.200 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[3][6] ; CLOCK_50_I ; 9.445 ; 9.445 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][*] ; CLOCK_50_I ; 7.937 ; 7.937 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][0] ; CLOCK_50_I ; 8.063 ; 8.063 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][1] ; CLOCK_50_I ; 8.319 ; 8.319 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][2] ; CLOCK_50_I ; 8.217 ; 8.217 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][3] ; CLOCK_50_I ; 8.277 ; 8.277 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][4] ; CLOCK_50_I ; 8.040 ; 8.040 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][5] ; CLOCK_50_I ; 8.185 ; 8.185 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[4][6] ; CLOCK_50_I ; 7.937 ; 7.937 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][*] ; CLOCK_50_I ; 7.724 ; 7.724 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][0] ; CLOCK_50_I ; 8.047 ; 8.047 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][1] ; CLOCK_50_I ; 8.278 ; 8.278 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][2] ; CLOCK_50_I ; 8.281 ; 8.281 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][3] ; CLOCK_50_I ; 7.927 ; 7.927 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][4] ; CLOCK_50_I ; 7.724 ; 7.724 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][5] ; CLOCK_50_I ; 7.732 ; 7.732 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[5][6] ; CLOCK_50_I ; 8.300 ; 8.300 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][*] ; CLOCK_50_I ; 8.209 ; 8.209 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][0] ; CLOCK_50_I ; 8.451 ; 8.451 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][1] ; CLOCK_50_I ; 8.209 ; 8.209 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][2] ; CLOCK_50_I ; 8.212 ; 8.212 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][3] ; CLOCK_50_I ; 8.647 ; 8.647 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][4] ; CLOCK_50_I ; 9.027 ; 9.027 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][5] ; CLOCK_50_I ; 8.810 ; 8.810 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[6][6] ; CLOCK_50_I ; 8.846 ; 8.846 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][*] ; CLOCK_50_I ; 8.575 ; 8.575 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][0] ; CLOCK_50_I ; 9.111 ; 9.111 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][1] ; CLOCK_50_I ; 8.575 ; 8.575 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][2] ; CLOCK_50_I ; 10.125 ; 10.125 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][3] ; CLOCK_50_I ; 8.635 ; 8.635 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][4] ; CLOCK_50_I ; 8.827 ; 8.827 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][5] ; CLOCK_50_I ; 8.660 ; 8.660 ; Rise ; CLOCK_50_I ;
; SEVEN_SEGMENT_N_O[7][6] ; CLOCK_50_I ; 9.292 ; 9.292 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[*] ; CLOCK_50_I ; 7.832 ; 7.832 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[0] ; CLOCK_50_I ; 9.158 ; 9.158 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[1] ; CLOCK_50_I ; 8.801 ; 8.801 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[2] ; CLOCK_50_I ; 8.505 ; 8.505 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[3] ; CLOCK_50_I ; 8.471 ; 8.471 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[4] ; CLOCK_50_I ; 8.749 ; 8.749 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[5] ; CLOCK_50_I ; 8.805 ; 8.805 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[6] ; CLOCK_50_I ; 8.175 ; 8.175 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[7] ; CLOCK_50_I ; 8.496 ; 8.496 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[8] ; CLOCK_50_I ; 8.274 ; 8.274 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[9] ; CLOCK_50_I ; 9.035 ; 9.035 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[10] ; CLOCK_50_I ; 8.247 ; 8.247 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[11] ; CLOCK_50_I ; 8.947 ; 8.947 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[12] ; CLOCK_50_I ; 8.748 ; 8.748 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[13] ; CLOCK_50_I ; 8.990 ; 8.990 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[14] ; CLOCK_50_I ; 7.832 ; 7.832 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[15] ; CLOCK_50_I ; 8.437 ; 8.437 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[16] ; CLOCK_50_I ; 9.044 ; 9.044 ; Rise ; CLOCK_50_I ;
; SRAM_ADDRESS_O[17] ; CLOCK_50_I ; 9.001 ; 9.001 ; Rise ; CLOCK_50_I ;
; SRAM_CE_N_O ; CLOCK_50_I ; 8.398 ; 8.398 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[*] ; CLOCK_50_I ; 8.081 ; 8.081 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; 8.562 ; 8.562 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; 8.542 ; 8.542 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; 8.205 ; 8.205 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; 8.474 ; 8.474 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; 8.387 ; 8.387 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; 8.398 ; 8.398 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; 8.359 ; 8.359 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; 8.264 ; 8.264 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; 8.262 ; 8.262 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[9] ; CLOCK_50_I ; 8.289 ; 8.289 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[10] ; CLOCK_50_I ; 8.081 ; 8.081 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[11] ; CLOCK_50_I ; 8.712 ; 8.712 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[12] ; CLOCK_50_I ; 8.604 ; 8.604 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[13] ; CLOCK_50_I ; 8.639 ; 8.639 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[14] ; CLOCK_50_I ; 8.352 ; 8.352 ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[15] ; CLOCK_50_I ; 8.349 ; 8.349 ; Rise ; CLOCK_50_I ;
; SRAM_OE_N_O ; CLOCK_50_I ; 8.398 ; 8.398 ; Rise ; CLOCK_50_I ;
; SRAM_WE_N_O ; CLOCK_50_I ; 7.872 ; 7.872 ; Rise ; CLOCK_50_I ;
; VGA_BLANK_O ; CLOCK_50_I ; 8.767 ; 8.767 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[*] ; CLOCK_50_I ; 7.272 ; 7.272 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[0] ; CLOCK_50_I ; 7.272 ; 7.272 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[1] ; CLOCK_50_I ; 7.275 ; 7.275 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[2] ; CLOCK_50_I ; 7.504 ; 7.504 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[3] ; CLOCK_50_I ; 7.489 ; 7.489 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[4] ; CLOCK_50_I ; 7.910 ; 7.910 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[5] ; CLOCK_50_I ; 7.555 ; 7.555 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[6] ; CLOCK_50_I ; 7.543 ; 7.543 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[7] ; CLOCK_50_I ; 7.538 ; 7.538 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[8] ; CLOCK_50_I ; 7.746 ; 7.746 ; Rise ; CLOCK_50_I ;
; VGA_BLUE_O[9] ; CLOCK_50_I ; 7.746 ; 7.746 ; Rise ; CLOCK_50_I ;
; VGA_CLOCK_O ; CLOCK_50_I ; 6.464 ; 6.464 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[*] ; CLOCK_50_I ; 7.295 ; 7.295 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[0] ; CLOCK_50_I ; 7.526 ; 7.526 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[1] ; CLOCK_50_I ; 7.507 ; 7.507 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[2] ; CLOCK_50_I ; 7.814 ; 7.814 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[3] ; CLOCK_50_I ; 7.813 ; 7.813 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[4] ; CLOCK_50_I ; 7.377 ; 7.377 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[5] ; CLOCK_50_I ; 7.948 ; 7.948 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[6] ; CLOCK_50_I ; 7.565 ; 7.565 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[7] ; CLOCK_50_I ; 7.603 ; 7.603 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[8] ; CLOCK_50_I ; 7.611 ; 7.611 ; Rise ; CLOCK_50_I ;
; VGA_GREEN_O[9] ; CLOCK_50_I ; 7.295 ; 7.295 ; Rise ; CLOCK_50_I ;
; VGA_HSYNC_O ; CLOCK_50_I ; 8.286 ; 8.286 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[*] ; CLOCK_50_I ; 7.730 ; 7.730 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[0] ; CLOCK_50_I ; 7.957 ; 7.957 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[1] ; CLOCK_50_I ; 7.946 ; 7.946 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[2] ; CLOCK_50_I ; 8.015 ; 8.015 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[3] ; CLOCK_50_I ; 8.186 ; 8.186 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[4] ; CLOCK_50_I ; 7.959 ; 7.959 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[5] ; CLOCK_50_I ; 7.760 ; 7.760 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[6] ; CLOCK_50_I ; 7.782 ; 7.782 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[7] ; CLOCK_50_I ; 7.791 ; 7.791 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[8] ; CLOCK_50_I ; 7.730 ; 7.730 ; Rise ; CLOCK_50_I ;
; VGA_RED_O[9] ; CLOCK_50_I ; 7.756 ; 7.756 ; Rise ; CLOCK_50_I ;
; VGA_VSYNC_O ; CLOCK_50_I ; 8.275 ; 8.275 ; Rise ; CLOCK_50_I ;
; VGA_CLOCK_O ; CLOCK_50_I ; 6.464 ; 6.464 ; Fall ; CLOCK_50_I ;
; SRAM_LB_N_O ; CLOCK_50_I ; 5.891 ; 5.891 ; Fall ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ;
; SRAM_UB_N_O ; CLOCK_50_I ; 5.891 ; 5.891 ; Fall ; SRAM_unit|Clock_100_PLL_inst|altpll_component|pll|clk[0] ;
+--------------------------+------------+--------+--------+------------+----------------------------------------------------------+
+--------------------------------------------------------+
; Propagation Delay ;
+--------------+-------------+----+--------+--------+----+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+--------------+-------------+----+--------+--------+----+
; SWITCH_I[17] ; resetn ; ; 11.929 ; 11.929 ; ;
+--------------+-------------+----+--------+--------+----+
+--------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------+-------------+----+--------+--------+----+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+--------------+-------------+----+--------+--------+----+
; SWITCH_I[17] ; resetn ; ; 11.929 ; 11.929 ; ;
+--------------+-------------+----+--------+--------+----+
+------------------------------------------------------------------------------+
; Output Enable Times ;
+-------------------+------------+-------+------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-------------------+------------+-------+------+------------+-----------------+
; SRAM_DATA_IO[*] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; 8.610 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; 8.620 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; 8.588 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; 8.568 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; 8.263 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; 8.313 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[9] ; CLOCK_50_I ; 8.313 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[10] ; CLOCK_50_I ; 8.086 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[11] ; CLOCK_50_I ; 8.086 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[12] ; CLOCK_50_I ; 8.076 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[13] ; CLOCK_50_I ; 8.076 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[14] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[15] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
+-------------------+------------+-------+------+------------+-----------------+
+------------------------------------------------------------------------------+
; Minimum Output Enable Times ;
+-------------------+------------+-------+------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-------------------+------------+-------+------+------------+-----------------+
; SRAM_DATA_IO[*] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; 8.610 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; 8.620 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; 8.588 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; 8.568 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; 8.263 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; 8.313 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[9] ; CLOCK_50_I ; 8.313 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[10] ; CLOCK_50_I ; 8.086 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[11] ; CLOCK_50_I ; 8.086 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[12] ; CLOCK_50_I ; 8.076 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[13] ; CLOCK_50_I ; 8.076 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[14] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[15] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
+-------------------+------------+-------+------+------------+-----------------+
+---------------------------------------------------------------------------------------+
; Output Disable Times ;
+-------------------+------------+-----------+-----------+------------+-----------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+-------------------+------------+-----------+-----------+------------+-----------------+
; SRAM_DATA_IO[*] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; 8.610 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; 8.620 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; 8.588 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; 8.568 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; 8.263 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; 8.313 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[9] ; CLOCK_50_I ; 8.313 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[10] ; CLOCK_50_I ; 8.086 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[11] ; CLOCK_50_I ; 8.086 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[12] ; CLOCK_50_I ; 8.076 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[13] ; CLOCK_50_I ; 8.076 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[14] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[15] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
+-------------------+------------+-----------+-----------+------------+-----------------+
+---------------------------------------------------------------------------------------+
; Minimum Output Disable Times ;
+-------------------+------------+-----------+-----------+------------+-----------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ;
+-------------------+------------+-----------+-----------+------------+-----------------+
; SRAM_DATA_IO[*] ; CLOCK_50_I ; 8.062 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[0] ; CLOCK_50_I ; 8.610 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[1] ; CLOCK_50_I ; 8.620 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[2] ; CLOCK_50_I ; 8.588 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[3] ; CLOCK_50_I ; 8.568 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[4] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[5] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[6] ; CLOCK_50_I ; 8.275 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[7] ; CLOCK_50_I ; 8.263 ; ; Rise ; CLOCK_50_I ;
; SRAM_DATA_IO[8] ; CLOCK_50_I ; 8.313 ; ; Rise ; CLOCK_50_I ;