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PROJECT.v.bak
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PROJECT.v.bak
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/*
Copyright by Henry Ko and Nicola Nicolici
Developed for the Digital Systems Design course (COE3DQ4)
Department of Electrical and Computer Engineering
McMaster University
Ontario, Canada
*/
`timescale 1ns/100ps
`default_nettype none
`include "define_state.h"
// This is the top module
// It connects the SRAM and VGA together
// It will first write RGB data of an image with 8x8 rectangles of size 40x30 pixels into the SRAM
// The VGA will then read the SRAM and display the image
module PROJECT (
/////// board clocks ////////////
input logic CLOCK_50_I, // 50 MHz clock
/////// pushbuttons/switches ////////////
input logic[3:0] PUSH_BUTTON_I, // pushbuttons
input logic[17:0] SWITCH_I, // toggle switches
/////// SRAM Interface ////////////
inout wire[15:0] SRAM_DATA_IO, // SRAM data bus 16 bits
output logic[17:0] SRAM_ADDRESS_O, // SRAM address bus 18 bits
output logic SRAM_UB_N_O, // SRAM high-byte data mask
output logic SRAM_LB_N_O, // SRAM low-byte data mask
output logic SRAM_WE_N_O, // SRAM write enable
output logic SRAM_CE_N_O, // SRAM chip enable
output logic SRAM_OE_N_O // SRAM output logic enable
);
parameter NUM_ROW_RECTANGLE = 8,
NUM_COL_RECTANGLE = 8,
RECT_WIDTH = 40,
RECT_HEIGHT = 30,
VIEW_AREA_LEFT = 160,
VIEW_AREA_RIGHT = 480,
VIEW_AREA_TOP = 120,
VIEW_AREA_BOTTOM = 360;
state_type state;
// For Push button
logic [3:0] PB_pushed;
logic resetn;
// For SRAM
logic [17:0] SRAM_address;
logic [15:0] SRAM_write_data;
logic SRAM_we_n;
logic [15:0] SRAM_read_data;
logic SRAM_ready;
logic [2:0] rect_row_count; // Number of rectangles in a row
logic [2:0] rect_col_count; // Number of rectangles in a column
logic [5:0] rect_width_count; // Width of each rectangle
logic [4:0] rect_height_count; // Height of each rectangle
logic [2:0] color;
assign resetn = ~SWITCH_I[17] && SRAM_ready;
// Push Button unit
PB_Controller PB_unit (
.Clock_50(CLOCK_50_I),
.Resetn(resetn),
.PB_signal(PUSH_BUTTON_I),
.PB_pushed(PB_pushed)
);
// SRAM unit
SRAM_Controller SRAM_unit (
.Clock_50(CLOCK_50_I),
.Resetn(~SWITCH_I[17]),
.SRAM_address(SRAM_address),
.SRAM_write_data(SRAM_write_data),
.SRAM_we_n(SRAM_we_n),
.SRAM_read_data(SRAM_read_data),
.SRAM_ready(SRAM_ready),
// To the SRAM pins
.SRAM_DATA_IO(SRAM_DATA_IO),
.SRAM_ADDRESS_O(SRAM_ADDRESS_O),
.SRAM_UB_N_O(SRAM_UB_N_O),
.SRAM_LB_N_O(SRAM_LB_N_O),
.SRAM_WE_N_O(SRAM_WE_N_O),
.SRAM_CE_N_O(SRAM_CE_N_O),
.SRAM_OE_N_O(SRAM_OE_N_O)
);
// Each rectangle will have different color
assign color = rect_col_count + rect_row_count;
always_ff @ (posedge CLOCK_50_I or negedge resetn) begin
if (resetn == 1'b0) begin
state <= S_IDLE;
SRAM_we_n <= 1'b1;
SRAM_write_data <= 16'd0;
SRAM_address <= 18'd0;
end else begin
case (state)
default: state <= S_IDLE;
endcase
end
end
endmodule