How to disable logic optimization after placement with OpenROAD-flow-scripts?

[dearmrlv]

Does anybody know how to disable timing optimization after placement stage with OpenROAD-flow-scripts? Or limit timing optimization by buffer insertion only?
In CTS stage some buffers may be inserted, and I found that after some stages (may be detailed routing?), some of the logic paths will be changed.
Are there ways to limit the timing optimization after placement using buffer insertion only?
Thanks!

[maliberty]

See https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rsz#repair-timing -skip_gate_cloning -skip_pin_swap.

I'm curious why you want to avoid them?

[dearmrlv]

Thanks and I'll try it!
I do this because I want to compare the performance of different timing optimization techniques.