Choose net name for Clock Tree synthesis

[vijayank88]

Hi OR Team/@maliberty,

I have top module clock wb_clk_i
Inside another module register and it has clk_i

Now I want to use register.clk_i as my clock tree synthesis net name.
Which variable to add or modify in constraint.sdc wrt to ORFS flow?

Thanks in advance.

[maliberty]

There is no control for the net name prefix currently. What is your goal in choosing the name?

[vijayank88]

@maliberty
I'm testing OpenLane designs with ORFS flow.
In the following example https://github.com/jaquerinte/caravel_radiation_harden/blob/main/openlane/user_proj_example/config.tcl#L32
User skipped STA and using CLOCK_NET variable for CTS stage only.
So how do I use ORFS constraint.sdc to mimic the same.

[maliberty]

I don't see CLOCK_NET doing anything besides being used in a puts. Does it actually appear in the OL SDC?

[vijayank88]

@maliberty
just found your OL Issue: The-OpenROAD-Project/OpenLane#769

In cts.tcl you have:
clock_tree_synthesis {*}arg_list
...
-clk_nets $::env(CLOCK_NET)\

-clk_nets isn't needed if the clocks are defined in SDC. CTS will automatically find the clock nets from STA.

Just defining clock port name is enough