diff --git a/README.md b/README.md
index ad8229b..d3d0bf7 100644
--- a/README.md
+++ b/README.md
@@ -11,7 +11,7 @@
 - [x] 系统 Ⅰ lab5-1/lab5-2：单周期 CPU
 - [x] extra：单周期 CPU with 特权指令/异常处理
 - [x] 系统 Ⅱ lab1：流水线 CPU (stall)
-- [ ] 系统 Ⅱ lab2：流水线 CPU (forwarding)
+- [x] 系统 Ⅱ lab2：流水线 CPU (forwarding)
 - [ ] 系统 Ⅱ lab7：流水线 CPU with 特权指令/异常处理
 - [ ] 系统 Ⅲ lab1：流水线 CPU with 动态分支预测
 - [ ] 系统 Ⅲ lab2：流水线 CPU with Cache
diff --git a/src/CPU.v b/src/CPU.v
index 785b8e0..55323c3 100644
--- a/src/CPU.v
+++ b/src/CPU.v
@@ -22,15 +22,21 @@ module CPU(
     wire    [3:0]   alu_op;
     wire    [1:0]   pc_src, mem_to_reg;
     wire            reg_write, alu_src, branch, b_type, auipc, mem_write_;
+    wire            mem_read, bubble_stop, jump;
     reg     [31:0]  ID_EX_data1, ID_EX_data2;
     reg     [31:0]  ID_EX_pc, ID_EX_imm;
+    reg     [4:0]   ID_EX_rs1, ID_EX_rs2;
     reg     [4:0]   ID_EX_write_addr;
     reg     [3:0]   ID_EX_alu_op;
     reg     [1:0]   ID_EX_pc_src, ID_EX_mem_to_reg;
     reg             ID_EX_reg_write, ID_EX_alu_src, ID_EX_branch, ID_EX_b_type, ID_EX_auipc, ID_EX_mem_write;
+    reg             ID_EX_mem_read;
 
     wire    [31:0]  alu_data1, alu_data2, alu_result;
     wire            alu_zero;
+    wire    [2:0]   forwardA, forwardB;
+    wire    [1:0]   forwardC;
+    wire    [31:0]  ex_mem_data2;
     reg     [31:0]  EX_MEM_alu_result, EX_MEM_pc, EX_MEM_imm;
     reg     [31:0]  EX_MEM_data2;
     reg     [4:0]   EX_MEM_write_addr;
@@ -66,6 +72,9 @@ module CPU(
             ID_EX_b_type <= 1'b0;
             ID_EX_auipc <= 1'b0;
             ID_EX_mem_write <= 1'b0;
+            ID_EX_mem_read <= 1'b0;
+            ID_EX_rs1 <= 5'b0;
+            ID_EX_rs2 <= 5'b0;
             EX_MEM_alu_result <= 32'b0;
             EX_MEM_pc <= 32'b0;
             EX_MEM_imm <= 32'b0;
@@ -85,30 +94,63 @@ module CPU(
             MEM_WB_mem_to_reg <= 2'b0;
             MEM_WB_reg_write <= 1'b0;
         end
-        else begin
-            pc <= pc_next;
+        else begin 
+            if (bubble_stop) begin
+                ID_EX_alu_op <= 4'b0;
+                ID_EX_pc_src <= 2'b0;
+                ID_EX_mem_to_reg <= 2'b0;
+                ID_EX_reg_write <= 1'b0;
+                ID_EX_alu_src <= 1'b0;
+                ID_EX_branch <= 1'b0;
+                ID_EX_b_type <= 1'b0;
+                ID_EX_auipc <= 1'b0;
+                ID_EX_mem_write <= 1'b0;
+                ID_EX_mem_read <= 1'b0;
+            end else if (jump) begin
+                pc <= pc_next;
 
-            IF_ID_pc <= pc;
-            IF_ID_inst <= inst;
+                IF_ID_pc <= pc;
+                IF_ID_inst <= 32'h00000013;
+                
+                ID_EX_pc_src <= pc_src;
+                ID_EX_mem_to_reg <= mem_to_reg;
+                ID_EX_reg_write <= reg_write;
+                ID_EX_alu_src <= alu_src;
+                ID_EX_branch <= branch;
+                ID_EX_b_type <= b_type;
+                ID_EX_auipc <= auipc;
+                ID_EX_alu_op <= alu_op;
+                ID_EX_mem_write <= mem_write_;
+                ID_EX_mem_read <= mem_read;
+            end else begin 
+                pc <= pc_next;
 
+                IF_ID_pc <= pc;
+                IF_ID_inst <= inst;
+
+                ID_EX_pc_src <= pc_src;
+                ID_EX_mem_to_reg <= mem_to_reg;
+                ID_EX_reg_write <= reg_write;
+                ID_EX_alu_src <= alu_src;
+                ID_EX_branch <= branch;
+                ID_EX_b_type <= b_type;
+                ID_EX_auipc <= auipc;
+                ID_EX_alu_op <= alu_op;
+                ID_EX_mem_write <= mem_write_;
+                ID_EX_mem_read <= mem_read;
+            end
+            
             ID_EX_pc <= IF_ID_pc;
             ID_EX_data1 <= read_data1;
             ID_EX_data2 <= read_data2;
             ID_EX_imm <= imm;
             ID_EX_write_addr <= IF_ID_inst[11:7];
-            ID_EX_pc_src <= pc_src;
-            ID_EX_mem_to_reg <= mem_to_reg;
-            ID_EX_reg_write <= reg_write;
-            ID_EX_alu_src <= alu_src;
-            ID_EX_branch <= branch;
-            ID_EX_b_type <= b_type;
-            ID_EX_auipc <= auipc;
-            ID_EX_alu_op <= alu_op;
-            ID_EX_mem_write <= mem_write_;
+            ID_EX_rs1 <= IF_ID_inst[19:15];
+            ID_EX_rs2 <= IF_ID_inst[24:20];
 
             EX_MEM_pc <= ID_EX_pc;
             EX_MEM_imm <= ID_EX_imm;
-            EX_MEM_data2 <= ID_EX_data2;
+            EX_MEM_data2 <= ex_mem_data2;
             EX_MEM_alu_result <= alu_result;
             EX_MEM_write_addr <= ID_EX_write_addr;
             EX_MEM_pc_src <= ID_EX_pc_src;
@@ -131,6 +173,34 @@ module CPU(
 
 //--------------------ID--------------------//
 
+    StallUnit stallunit (
+        .ID_EX_mem_read(ID_EX_mem_read),
+        .ID_EX_rd(ID_EX_write_addr),
+        .IF_ID_rs1(IF_ID_inst[19:15]),
+        .IF_ID_rs2(IF_ID_inst[24:20]),
+        .jump(jump),
+        .ID_EX_reg_write(ID_EX_reg_write),
+        .bubble_stop(bubble_stop)
+    );
+
+    assign jal_addr = IF_ID_pc + imm;
+    wire    [31:0]  reg1, reg2;
+    assign reg1 = (jump && EX_MEM_reg_write && (EX_MEM_write_addr != 0) && (EX_MEM_write_addr == IF_ID_inst[19:15])) ? EX_MEM_alu_result : read_data1;
+    assign reg2 = (jump && EX_MEM_reg_write && (EX_MEM_write_addr != 0) && (EX_MEM_write_addr == IF_ID_inst[24:20])) ? EX_MEM_alu_result : read_data2;
+    assign jalr_addr = reg1 + reg2;
+
+    MuxPC mux_pc (
+        .I0(jump ? pc : pc + 4),
+        .I1(jalr_addr),
+        .I2(jal_addr),
+        .I3(jal_addr),
+        .s(pc_src),
+        .branch(branch),
+        .b_type(b_type),
+        .alu_res(reg1 ^ reg2),
+        .o(pc_next)
+    );
+
     Regs regs (
         .clk(clk),
         .rst(rst),
@@ -157,7 +227,9 @@ module CPU(
         .branch(branch),
         .b_type(b_type),
         .mem_write(mem_write_),
-        .auipc(auipc)
+        .auipc(auipc),
+        .mem_read(mem_read),
+        .jump(jump)
     );
 
     ImmGen immgen (
@@ -167,17 +239,45 @@ module CPU(
 
 //--------------------EX--------------------//
 
-    Mux2x32 mux2x32_1 (
+    ForwardingUnit forwarding (
+        .EX_MEM_rd(EX_MEM_write_addr),
+        .MEM_WB_rd(MEM_WB_write_addr),
+        .ID_EX_rs1(ID_EX_rs1),
+        .ID_EX_rs2(ID_EX_rs2),
+        .EX_MEM_reg_write(EX_MEM_reg_write),
+        .MEM_WB_reg_write(MEM_WB_reg_write),
+        .EX_MEM_mem_to_reg(EX_MEM_mem_to_reg),
+        .MEM_WB_mem_to_reg(MEM_WB_mem_to_reg),
+        .auipc(ID_EX_auipc),
+        .alu_src_b(ID_EX_alu_src),
+        .ForwardA(forwardA),
+        .ForwardB(forwardB),
+        .ForwardC(forwardC)
+    );
+
+    Mux8x32 mux_alu_a (
         .I0(ID_EX_data1),
-        .I1(ID_EX_pc),
-        .s(ID_EX_auipc),
+        .I1(EX_MEM_alu_result),
+        .I2(write_data),
+        .I3(ID_EX_pc),
+        .I4(EX_MEM_pc + 4),
+        .I5(MEM_WB_pc + 4),
+        .I6(EX_MEM_imm),
+        .I7(MEM_WB_imm),
+        .s(forwardA),
         .o(alu_data1)
     );
 
-    Mux2x32 mux2x32_2 (
+    Mux8x32 mux_alu_b (
         .I0(ID_EX_data2),
-        .I1(ID_EX_imm),
-        .s(ID_EX_alu_src),
+        .I1(EX_MEM_alu_result),
+        .I2(write_data),
+        .I3(ID_EX_imm),
+        .I4(EX_MEM_pc + 4),
+        .I5(MEM_WB_pc + 4),
+        .I6(EX_MEM_imm),
+        .I7(MEM_WB_imm),
+        .s(forwardB),
         .o(alu_data2)
     );
 
@@ -189,28 +289,20 @@ module CPU(
         .zero(alu_zero)
     );
 
+    Mux4x32 mux_data2 (
+        .I0(ID_EX_data2),
+        .I1(EX_MEM_alu_result),
+        .I2(write_data),
+        .I3(32'h00000000),
+        .s(forwardC),
+        .o(ex_mem_data2)
+    );
+
 //--------------------MEM--------------------//
     assign addr_out = EX_MEM_alu_result;
     assign data_out = EX_MEM_data2;
     assign mem_write = EX_MEM_mem_write;
 
-    assign jal_addr = EX_MEM_pc + EX_MEM_imm;
-    assign jalr_addr = EX_MEM_alu_result;
-
-    MuxPC mux_pc (
-        .I0(pc + 4),
-        .I1(jalr_addr),
-        .I2(jal_addr),
-        .I3(jal_addr),
-        .s(EX_MEM_pc_src),
-        .branch(EX_MEM_branch),
-        .b_type(EX_MEM_b_type),
-        .alu_res(EX_MEM_alu_result),
-        .o(pc_next)
-    );
-
-    // assign pc_next = pc + 4;
-
 //--------------------WB--------------------//
 
     Mux4x32 mux4x32 (
diff --git a/src/CoreSim.v b/src/CoreSim.v
index ef5a967..fafba4f 100644
--- a/src/CoreSim.v
+++ b/src/CoreSim.v
@@ -12,7 +12,7 @@ module CoreSim;
 
     initial begin
         $dumpvars(0, CoreSim);
-        #320 $finish;
+        #1000 $finish;
     end
 
     initial begin
diff --git a/src/components/Control.v b/src/components/Control.v
index 7b60164..9b0939c 100644
--- a/src/components/Control.v
+++ b/src/components/Control.v
@@ -12,7 +12,9 @@ module Control (
     output reg          mem_write,  // write RAM or not
     output reg          branch,     // is branch or not
     output reg          b_type,     // 1 -> beq, 0 -> bne
-    output reg          auipc       // is auipc or not
+    output reg          auipc,      // is auipc or not
+    output reg          mem_read,
+    output reg          jump
 );
     `include "AluOp.vh"
     always @(*) begin
@@ -25,11 +27,13 @@ module Control (
         branch      = 0;
         b_type      = 0;
         auipc       = 0;
+        mem_read    = 0;
+        jump        = 0;
 
         case (op_code)
             7'b0000011: begin   // lw
                 reg_write = 1;  alu_src_b = 1;  alu_op = ADD;
-                mem_to_reg = 2'b11;
+                mem_to_reg = 2'b11;             mem_read = 1;
             end
             7'b0100011: begin   // sw
                 alu_src_b = 1;  alu_op = ADD;   mem_write = 1;
@@ -51,9 +55,11 @@ module Control (
             end
             7'b1100011: begin   // bne beq
                 alu_op = XOR;   branch = 1; b_type = ~funct3[0];
+                jump = 1;
             end
             7'b1101111: begin   // jal
-                pc_src = 2'b10; reg_write = 1;  mem_to_reg = 2'b10;
+                pc_src = 2'b10; reg_write = 1;  mem_to_reg = 2'b10; 
+                jump = 1;
             end
             7'b0110111: begin   // lui
                 reg_write = 1;  mem_to_reg = 2'b01;
@@ -67,7 +73,7 @@ module Control (
             end
             7'b1100111: begin   // jalr
                 pc_src = 2'b01; reg_write = 1; mem_to_reg = 2'b10;
-                alu_src_b = 1;
+                alu_src_b = 1;  jump = 1;
             end
         endcase
     end
diff --git a/src/components/ForwardingUnit.v b/src/components/ForwardingUnit.v
new file mode 100644
index 0000000..e19f6a6
--- /dev/null
+++ b/src/components/ForwardingUnit.v
@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+
+
+module ForwardingUnit(
+    input       [4:0]   EX_MEM_rd,
+    input       [4:0]   MEM_WB_rd,
+    input       [4:0]   ID_EX_rs1,
+    input       [4:0]   ID_EX_rs2,
+    input               EX_MEM_reg_write,
+    input               MEM_WB_reg_write,
+    input       [1:0]   EX_MEM_mem_to_reg,
+    input       [1:0]   MEM_WB_mem_to_reg,
+    input               auipc,
+    input               alu_src_b,
+    output reg  [2:0]   ForwardA,   // 00 来自寄存器，01 来自 EX/MEM，10 来自 MEM/WB，11 来自 PC
+                                    // 100 来自 EX/MEM 的 PC + 4，101 来自 MEM/WB 的 PC + 4
+                                    // 110 来自 EX/MEM 的 imm，111 来自 MEM/WB 的 imm
+    output reg  [2:0]   ForwardB,   // 00 来自寄存器，01 来自 EX/MEM，10 来自 MEM/WB，11 来自 imm
+    output reg  [1:0]   ForwardC
+);
+    always @(*) begin
+        if (auipc) begin
+            assign ForwardA = 3'b011;
+        end else begin
+            if          (EX_MEM_reg_write == 1 && EX_MEM_rd != 0 && EX_MEM_rd == ID_EX_rs1) begin
+                if      (EX_MEM_mem_to_reg == 2'b01) assign ForwardA = 3'b110;
+                else if (EX_MEM_mem_to_reg == 2'b10) assign ForwardA = 3'b100;
+                else                                 assign ForwardA = 3'b001;
+            end else if (MEM_WB_reg_write == 1 && MEM_WB_rd != 0 && MEM_WB_rd == ID_EX_rs1) begin
+                if      (MEM_WB_mem_to_reg == 2'b01) assign ForwardA = 3'b111;
+                else if (MEM_WB_mem_to_reg == 2'b10) assign ForwardA = 3'b101;
+                else                                 assign ForwardA = 3'b010;
+            end else begin
+                assign ForwardA = 3'b000;
+            end
+        end
+        if (alu_src_b) begin
+            assign ForwardB = 3'b011;
+        end else begin
+            if          (EX_MEM_reg_write == 1 && EX_MEM_rd != 0 && EX_MEM_rd == ID_EX_rs2) begin
+                if      (EX_MEM_mem_to_reg == 2'b01) assign ForwardB = 3'b110;
+                else if (EX_MEM_mem_to_reg == 2'b10) assign ForwardB = 3'b100;
+                else                                 assign ForwardB = 3'b001;
+            end else if (MEM_WB_reg_write == 1 && MEM_WB_rd != 0 && MEM_WB_rd == ID_EX_rs2) begin
+                if      (MEM_WB_mem_to_reg == 2'b01) assign ForwardB = 3'b111;
+                else if (MEM_WB_mem_to_reg == 2'b10) assign ForwardB = 3'b101;
+                else                                 assign ForwardB = 3'b010;
+            end else begin
+                assign ForwardB = 3'b000;
+            end
+        end
+        if      (EX_MEM_reg_write && EX_MEM_rd != 0 && EX_MEM_rd == ID_EX_rs2) assign ForwardC = 2'b01;
+        else if (MEM_WB_reg_write && MEM_WB_rd != 0 && MEM_WB_rd == ID_EX_rs2) assign ForwardC = 2'b01;
+        else assign ForwardC = 2'b00;
+    end
+endmodule
diff --git a/src/components/Regs.v b/src/components/Regs.v
index 0c0aa73..c39cf01 100644
--- a/src/components/Regs.v
+++ b/src/components/Regs.v
@@ -25,7 +25,7 @@ module Regs (
     assign read_data_2 = (read_addr_2 == 0) ? 0 : register[read_addr_2]; // read
     assign debug_reg = (debug_reg_addr == 0) ? 0 : register[debug_reg_addr];
 
-    always @(posedge clk or posedge rst) begin
+    always @(negedge clk or posedge rst) begin
         if (rst == 1) for (i = 1; i < 32; i = i + 1) register[i] <= 0; // reset
         else if (we == 1 && write_addr != 0) register[write_addr] <= write_data;
     end
diff --git a/src/components/StallUnit.v b/src/components/StallUnit.v
new file mode 100644
index 0000000..ad21331
--- /dev/null
+++ b/src/components/StallUnit.v
@@ -0,0 +1,13 @@
+`timescale 1ns / 1ps
+
+module StallUnit(
+    input           ID_EX_mem_read,
+    input   [4:0]   ID_EX_rd,
+    input   [4:0]   IF_ID_rs1,
+    input   [4:0]   IF_ID_rs2,
+    input           jump,
+    input           ID_EX_reg_write,
+    output          bubble_stop
+);
+    assign bubble_stop = (ID_EX_mem_read && (ID_EX_rd == IF_ID_rs1 || ID_EX_rd == IF_ID_rs2)) || (jump && ID_EX_reg_write && ID_EX_rd != 0 && (ID_EX_rd == IF_ID_rs1 || ID_EX_rd == IF_ID_rs2));
+endmodule
diff --git a/src/memory/RAM.v b/src/memory/RAM.v
index 555b9d6..ba6dacf 100644
--- a/src/memory/RAM.v
+++ b/src/memory/RAM.v
@@ -15,7 +15,8 @@ module RAM (
     end
 
     initial begin
-        for (integer i = 0; i < 2048; i = i + 1) ram[i] <= 0;
+        for (integer i = 10; i < 2048; i = i + 1) ram[i] <= 0;
+        $readmemh("tests/PipelineForwarding/test.ram.hex", ram);
     end
 
     always @(posedge clk) begin
diff --git a/src/memory/ROM.v b/src/memory/ROM.v
index 3acf2e3..be5c44e 100644
--- a/src/memory/ROM.v
+++ b/src/memory/ROM.v
@@ -7,7 +7,7 @@ module ROM (
     reg [31:0] rom [0:2047];
 
     initial begin
-        $readmemh("tests/PipelineStall/test.hex", rom);
+        $readmemh("tests/PipelineForwarding/test.hex", rom);
     end
 
     assign out = rom[address];
diff --git a/src/tests/PipelineForwarding/test.asm b/src/tests/PipelineForwarding/test.asm
new file mode 100644
index 0000000..66e7241
--- /dev/null
+++ b/src/tests/PipelineForwarding/test.asm
@@ -0,0 +1,66 @@
+test1:
+    addi x1, x0, 1
+    addi x2, x0, 1
+    addi x4, x0, 5
+fibonacci:
+    add x3, x1, x2
+    add x1, x2, x3
+    add x2, x1, x3
+    addi x4, x4, -1
+    bne x0, x4, fibonacci
+    addi x5, x0, 0x63D
+    bne x2, x5, fail
+
+test2:
+    addi x1, x0, 5
+    addi x2, x0, 0
+    addi x3, x0, 0x100
+    addi x5, x0, 4
+memcpy:
+    beq x1, x0, exit1 
+    lw x4, 0(x2)
+    sub x4, x4, x3
+    sw x4, 0(x3)
+    add x2, x2, x5
+    add x3, x3, x5
+    addi x1, x1, -1
+    bne x1, x0, memcpy
+exit1:
+    addi x1, x0, 5
+    addi x2, x0, 0
+    addi x3, x0, 0x100
+    addi x5, x0, 4
+memcmp:
+    beq x1, x0, test3
+    lw x4, 0(x2)
+    sub x4, x4, x3
+    lw x6, 0(x3)
+    add x2, x2, x5
+    add x3, x3, x5
+    addi x1, x1, -1
+    bne x4, x6, fail
+    j memcmp
+    
+
+test3:
+    lui x1, 0xDEADB     # 0xDEADB000
+    ori x2, x0, 0xEF    # 0x000000EF
+    add x3, x1, x2      # 0xDEADB0EF
+    sub x1, x2, x1      # 0x215250EF
+    addi x2, x0, 1      # 0x00000001
+    srl x4, x3, x2      # 0x6F56D877
+    and x2, x1, x4      # 0x21525067
+    lui x1, 0x21525     # 0x21525000
+    addi x1, x1, 0x67   # 0x21525067
+    bne x2, x1, fail
+    addi x1, x0, 0xbc
+    jalr x1, x1, 0
+    addi x2, x0, 0xbc
+    bne x1, x2, fail
+
+pass:
+    j pass
+
+
+fail:
+    j fail
diff --git a/src/tests/PipelineForwarding/test.hex b/src/tests/PipelineForwarding/test.hex
new file mode 100644
index 0000000..a171faa
--- /dev/null
+++ b/src/tests/PipelineForwarding/test.hex
@@ -0,0 +1,51 @@
+00100093
+00100113
+00500213
+002081B3
+003100B3
+00308133
+FFF20213
+FE4018E3
+63D00293
+0A511263
+00500093
+00000113
+10000193
+00400293
+02008063
+00012203
+40320233
+0041A023
+00510133
+005181B3
+FFF08093
+FE0092E3
+00500093
+00000113
+10000193
+00400293
+02008263
+00012203
+40320233
+0001A303
+00510133
+005181B3
+FFF08093
+04621263
+FE1FF06F
+DEADB0B7
+0EF06113
+002081B3
+401100B3
+00100113
+0021D233
+0040F133
+215250B7
+06708093
+00111C63
+0BC00093
+000080E7
+0BC00113
+00209463
+0000006F
+0000006F
\ No newline at end of file
diff --git a/src/tests/PipelineForwarding/test.ram.hex b/src/tests/PipelineForwarding/test.ram.hex
new file mode 100644
index 0000000..1774669
--- /dev/null
+++ b/src/tests/PipelineForwarding/test.ram.hex
@@ -0,0 +1,10 @@
+12345678
+87654321
+23333333
+66666666
+AFAFAFAF
+DEADBEAF
+20211021
+19491001
+19210701
+0928ACD4
\ No newline at end of file
diff --git a/src/utils/Mux8x32.v b/src/utils/Mux8x32.v
new file mode 100644
index 0000000..bc03fba
--- /dev/null
+++ b/src/utils/Mux8x32.v
@@ -0,0 +1,29 @@
+`timescale 1ns / 1ps
+
+module Mux8x32(
+    input   [31:0]  I0,
+    input   [31:0]  I1,
+    input   [31:0]  I2,
+    input   [31:0]  I3,
+    input   [31:0]  I4,
+    input   [31:0]  I5,
+    input   [31:0]  I6,
+    input   [31:0]  I7,
+    input   [2:0]   s,
+    output  [31:0]  o
+);
+    reg [31:0] out;
+    always @(*) begin
+        case (s)
+            3'b000: out <= I0;
+            3'b001: out <= I1;
+            3'b010: out <= I2;
+            3'b011: out <= I3;
+            3'b100: out <= I4;
+            3'b101: out <= I5;
+            3'b110: out <= I6;
+            3'b111: out <= I7;
+        endcase
+    end
+    assign o = out;
+endmodule
\ No newline at end of file
diff --git a/src/wave.gtkw b/src/wave.gtkw
index 1f54932..bbd0d01 100644
--- a/src/wave.gtkw
+++ b/src/wave.gtkw
@@ -1,11 +1,10 @@
 [*]
 [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
-[*] Wed Apr 26 13:20:38 2023
 [*]
 [timestart] 0
 [size] 1792 998
-[pos] -1 -1
-*-15.660110 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[pos] 0 320
+*-17.303963 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] CoreSim.
 [treeopen] CoreSim.core.
 [treeopen] CoreSim.core.cpu.
@@ -21,6 +20,15 @@ CoreSim.core.cpu.rst
 CoreSim.core.cpu.pc_out[31:0]
 CoreSim.core.cpu.inst[31:0]
 @800200
+-DataHazard
+@28
+CoreSim.core.cpu.stallunit.bubble_stop
+CoreSim.core.cpu.forwarding.ForwardA[2:0]
+CoreSim.core.cpu.forwarding.ForwardB[2:0]
+CoreSim.core.cpu.forwarding.ForwardC[1:0]
+@1000200
+-DataHazard
+@c00200
 -registers
 @c00024
 CoreSim.core.cpu.regs.\register[1][31:0]
@@ -59,9 +67,8 @@ CoreSim.core.cpu.regs.\register[1][31:0]
 (31)CoreSim.core.cpu.regs.\register[1][31:0]
 @1401200
 -group_end
-@25
-CoreSim.core.cpu.regs.\register[2][31:0]
 @24
+CoreSim.core.cpu.regs.\register[2][31:0]
 CoreSim.core.cpu.regs.\register[3][31:0]
 CoreSim.core.cpu.regs.\register[4][31:0]
 CoreSim.core.cpu.regs.\register[5][31:0]
@@ -91,22 +98,23 @@ CoreSim.core.cpu.regs.\register[28][31:0]
 CoreSim.core.cpu.regs.\register[29][31:0]
 CoreSim.core.cpu.regs.\register[30][31:0]
 CoreSim.core.cpu.regs.\register[31][31:0]
-@1000200
+@1401200
 -registers
-@c00200
+@800200
 -RAM
 @22
 CoreSim.core.ram_unit.\ram[0][31:0]
 CoreSim.core.ram_unit.\ram[1][31:0]
 CoreSim.core.ram_unit.\ram[2][31:0]
-CoreSim.core.ram_unit.\ram[36][31:0]
-CoreSim.core.ram_unit.\ram[37][31:0]
-CoreSim.core.ram_unit.\ram[38][31:0]
-CoreSim.core.ram_unit.\ram[39][31:0]
-CoreSim.core.ram_unit.\ram[256][31:0]
-CoreSim.core.ram_unit.\ram[257][31:0]
-CoreSim.core.ram_unit.\ram[258][31:0]
-@1401200
+CoreSim.core.ram_unit.\ram[3][31:0]
+CoreSim.core.ram_unit.\ram[4][31:0]
+CoreSim.core.ram_unit.\ram[5][31:0]
+CoreSim.core.ram_unit.\ram[6][31:0]
+CoreSim.core.ram_unit.\ram[7][31:0]
+CoreSim.core.ram_unit.\ram[8][31:0]
+CoreSim.core.ram_unit.\ram[9][31:0]
+CoreSim.core.ram_unit.\ram[10][31:0]
+@1000200
 -RAM
 [pattern_trace] 1
 [pattern_trace] 0