memory routing fails

[c-Monster]

I'm generating a bitstream with the iCEcube2 (commercial) flow. When I use icebox_vlog to extract a Verilog netlist, the memories are present but the read and write addresses are tied to 0. Here's HDL and the corresponging Verilog netlist.

module mem_a (
	read_clk,
	read_address,
	data_in,
	write_clk,
	rd_en,
	wr_en,
	write_address,
	data_out);
parameter address_width = 8;
parameter data_width = 32;
parameter depth = 256;
input read_clk, write_clk;
input rd_en;
input wr_en;
input [address_width-1:0] read_address, write_address;
input [data_width-1:0] data_in;
output [data_width-1:0] data_out;
reg [data_width-1:0] mem [depth -1 : 0]/* synthesis syn_ramstyle="no_rw_check" */;
reg [data_width-1:0] data_out;
always @(posedge write_clk)
	if(wr_en)
		mem[write_address] <= data_in;
always @(posedge read_clk)
	if(rd_en)
		data_out <= mem[read_address];
endmodule

Notice how WADDR and RADDR are tied to 0 in ram40_8_23.

module chip (input write_clk_ibuf, input read_clk_ibuf, output \data_out_obuf[1] , output \data_out_obuf[0] , output \data_out_obuf[11] , output \data_out_obuf[10] , output \data_out_obuf[12] , output \data_out_obuf[13] , output \data_out_obuf[15] , output \data_out_obuf[14] , output \data_out_obuf[17] , output \data_out_obuf[16] , output \data_out_obuf[18] , output \data_out_obuf[19] , output \data_out_obuf[23] , output \data_out_obuf[2] , output \data_out_obuf[20] , output \data_out_obuf[25] , output \data_out_obuf[21] , output \data_out_obuf[22] , output \data_out_obuf[24] , output \data_out_obuf[26] , output \data_out_obuf[27] , output \data_out_obuf[28] , output \data_out_obuf[29] , output \data_out_obuf[3] , output \data_out_obuf[30] , output \data_out_obuf[5] , output \data_out_obuf[31] , output \data_out_obuf[6] , output \data_out_obuf[7] , output \data_out_obuf[4] , output \data_out_obuf[8] , output \data_out_obuf[9] , input rd_en, input \read_address_ibuf[0] , input \read_address_ibuf[1] , input \read_address_ibuf[2] , input \read_address_ibuf[3] , input \read_address_ibuf[4] , input \read_address_ibuf[5] , input \read_address_ibuf[6] , input \read_address_ibuf[7] , input wr_en, input \write_address_ibuf[0] , input \write_address_ibuf[1] , input \write_address_ibuf[2] , input \write_address_ibuf[3] , input \write_address_ibuf[4] , input \write_address_ibuf[5] , input \write_address_ibuf[6] , input \data_in_ibuf[0] , input \write_address_ibuf[7] , input \data_in_ibuf[9] , input \data_in_ibuf[8] , input \data_in_ibuf[7] , input \data_in_ibuf[6] , input \data_in_ibuf[4] , input \data_in_ibuf[5] , input \data_in_ibuf[2] , input \data_in_ibuf[3] , input \data_in_ibuf[24] , input \data_in_ibuf[25] , input \data_in_ibuf[26] , input \data_in_ibuf[15] , input \data_in_ibuf[14] , input \data_in_ibuf[16] , input \data_in_ibuf[13] , input \data_in_ibuf[11] , input \data_in_ibuf[28] , input \data_in_ibuf[27] , input \data_in_ibuf[31] , input \data_in_ibuf[18] , input \data_in_ibuf[17] , input \data_in_ibuf[12] , input \data_in_ibuf[10] , input \data_in_ibuf[1] , input \data_in_ibuf[30] , input \data_in_ibuf[29] , input \data_in_ibuf[23] , input \data_in_ibuf[22] , input \data_in_ibuf[19] , input \data_in_ibuf[21] , input \data_in_ibuf[20] );

wire write_clk_ibuf, read_clk_ibuf, \data_out_obuf[1] , \data_out_obuf[0] , \data_out_obuf[11] , \data_out_obuf[10] , \data_out_obuf[12] , \data_out_obuf[13] , \data_out_obuf[15] , \data_out_obuf[14] ;
wire \data_out_obuf[17] , \data_out_obuf[16] , \data_out_obuf[18] , \data_out_obuf[19] , \data_out_obuf[23] , \data_out_obuf[2] , \data_out_obuf[20] , \data_out_obuf[25] , \data_out_obuf[21] , \data_out_obuf[22] ;
wire \data_out_obuf[24] , \data_out_obuf[26] , \data_out_obuf[27] , \data_out_obuf[28] , \data_out_obuf[29] , \data_out_obuf[3] , \data_out_obuf[30] , \data_out_obuf[5] , \data_out_obuf[31] , \data_out_obuf[6] ;
wire \data_out_obuf[7] , \data_out_obuf[4] , \data_out_obuf[8] , \data_out_obuf[9] , rd_en, \read_address_ibuf[0] , \read_address_ibuf[1] , \read_address_ibuf[2] , \read_address_ibuf[3] , \read_address_ibuf[4] ;
wire \read_address_ibuf[5] , \read_address_ibuf[6] , \read_address_ibuf[7] , wr_en, \write_address_ibuf[0] , \write_address_ibuf[1] , \write_address_ibuf[2] , \write_address_ibuf[3] , \write_address_ibuf[4] , \write_address_ibuf[5] ;
wire \write_address_ibuf[6] , \data_in_ibuf[0] , \write_address_ibuf[7] , \data_in_ibuf[9] , \data_in_ibuf[8] , \data_in_ibuf[7] , \data_in_ibuf[6] , \data_in_ibuf[4] , \data_in_ibuf[5] , \data_in_ibuf[2] ;
wire \data_in_ibuf[3] , \data_in_ibuf[24] , \data_in_ibuf[25] , \data_in_ibuf[26] , \data_in_ibuf[15] , n66, \data_in_ibuf[14] , \data_in_ibuf[16] , \data_in_ibuf[13] , \data_in_ibuf[11] ;
wire \data_in_ibuf[28] , \data_in_ibuf[27] , \data_in_ibuf[31] , \data_in_ibuf[18] , \data_in_ibuf[17] , \data_in_ibuf[12] , \data_in_ibuf[10] , \data_in_ibuf[1] , \data_in_ibuf[30] , \data_in_ibuf[29] ;
wire \data_in_ibuf[23] , \data_in_ibuf[22] , \data_in_ibuf[19] , \data_in_ibuf[21] , \data_in_ibuf[20] , open_0, open_1, open_2, open_3, open_4;
wire open_5, open_6, open_7, open_8, open_9, open_10, open_11, open_12, open_13, open_14;
wire open_15, n86;

SB_RAM40_4K #(
  .READ_MODE(0),
  .WRITE_MODE(0),
  .INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ram40_8_25 (
  .WADDR({1'b0, 1'b0, 1'b0, \write_address_ibuf[7] , \write_address_ibuf[6] , \write_address_ibuf[5] , \write_address_ibuf[4] , \write_address_ibuf[3] , \write_address_ibuf[2] , \write_address_ibuf[1] , \write_address_ibuf[0] }),
  .RADDR({1'b0, 1'b0, 1'b0, \read_address_ibuf[7] , \read_address_ibuf[6] , \read_address_ibuf[5] , \read_address_ibuf[4] , \read_address_ibuf[3] , \read_address_ibuf[2] , \read_address_ibuf[1] , \read_address_ibuf[0] }),
  .MASK({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
  .WDATA({\data_in_ibuf[31] , \data_in_ibuf[30] , \data_in_ibuf[29] , \data_in_ibuf[28] , \data_in_ibuf[27] , \data_in_ibuf[26] , \data_in_ibuf[25] , \data_in_ibuf[24] , \data_in_ibuf[23] , \data_in_ibuf[22] , \data_in_ibuf[21] , \data_in_ibuf[20] , \data_in_ibuf[19] , \data_in_ibuf[18] , \data_in_ibuf[17] , \data_in_ibuf[16] }),
  .RDATA({\data_out_obuf[31] , \data_out_obuf[30] , \data_out_obuf[29] , \data_out_obuf[28] , \data_out_obuf[27] , \data_out_obuf[26] , \data_out_obuf[25] , \data_out_obuf[24] , \data_out_obuf[23] , \data_out_obuf[22] , \data_out_obuf[21] , \data_out_obuf[20] , \data_out_obuf[19] , \data_out_obuf[18] , \data_out_obuf[17] , \data_out_obuf[16] }),
  .WE(n66),
  .WCLKE(wr_en),
  .WCLK(write_clk_ibuf),
  .RE(n66),
  .RCLKE(rd_en),
  .RCLK(read_clk_ibuf)
);

SB_RAM40_4K #(
  .READ_MODE(0),
  .WRITE_MODE(0),
  .INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
  .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ram40_8_23 (
  .WADDR({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
  .RADDR({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
  .MASK({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
  .WDATA({\data_in_ibuf[15] , \data_in_ibuf[14] , \data_in_ibuf[13] , \data_in_ibuf[12] , \data_in_ibuf[11] , \data_in_ibuf[10] , \data_in_ibuf[9] , \data_in_ibuf[8] , \data_in_ibuf[7] , \data_in_ibuf[6] , \data_in_ibuf[5] , \data_in_ibuf[4] , \data_in_ibuf[3] , \data_in_ibuf[2] , \data_in_ibuf[1] , \data_in_ibuf[0] }),
  .RDATA({\data_out_obuf[15] , \data_out_obuf[14] , \data_out_obuf[13] , \data_out_obuf[12] , \data_out_obuf[11] , \data_out_obuf[10] , \data_out_obuf[9] , \data_out_obuf[8] , \data_out_obuf[7] , \data_out_obuf[6] , \data_out_obuf[5] , \data_out_obuf[4] , \data_out_obuf[3] , \data_out_obuf[2] , \data_out_obuf[1] , \data_out_obuf[0] }),
  .WE(n66),
  .WCLKE(wr_en),
  .WCLK(write_clk_ibuf),
  .RE(n66),
  .RCLKE(rd_en),
  .RCLK(read_clk_ibuf)
);

assign n86 = /* LUT    7 25  0 */ 1'b1;
/* FF  7 25  0 */ assign n66 = n86;

endmodule