From 48f4e8710d1f51cdfe7db6b52853b8a052c46dcb Mon Sep 17 00:00:00 2001 From: boyang2022 Date: Tue, 12 Nov 2024 14:00:21 +0100 Subject: [PATCH 1/2] FEAT: Circuit current probe (#5352) Co-authored-by: Samuelopez-ansys --- .../modeler/circuits/primitives_nexxim.py | 73 +++++++++++++++++-- tests/system/general/test_21_Circuit.py | 9 ++- 2 files changed, 76 insertions(+), 6 deletions(-) diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py index d57fbf6e470..4179ed83b9b 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py @@ -813,7 +813,7 @@ def create_voltage_probe(self, name=None, location=None, angle=0, use_instance_i Parameters ---------- - name : + name : str, optional Name of the voltage probe. The default is ``None``. location : list of float, optional Position on the X axis and Y axis. The default is ``None``. @@ -830,24 +830,87 @@ def create_voltage_probe(self, name=None, location=None, angle=0, use_instance_i References ---------- + >>> oEditor.CreateComponent + + Examples + -------- + >>> from ansys.aedt.core import Circuit + >>> cir = Circuit() + >>> cir.modeler.components.create_voltage_probe(name="probe") + >>> cir.release_desktop(False, False) + """ + return self.__create_probe( + name=name, + probe_type="voltage", + location=location, + angle=angle, + use_instance_id_netlist=use_instance_id_netlist, + ) + + @pyaedt_function_handler() + def create_current_probe(self, name=None, location=None, angle=0, use_instance_id_netlist=False): + """Create a current probe. + + Parameters + ---------- + name : str, optional + Name of the current probe. The default is ``None``. + location : list of float, optional + Position on the X axis and Y axis. The default is ``None``. + angle : float, optional + Angle rotation in degrees. The default is ``0``. + use_instance_id_netlist : bool, optional + Whether to use the instance ID in the net list. + The default is ``False``. + + Returns + ------- + :class:`ansys.aedt.core.modeler.cad.object_3dcircuit.CircuitComponent` + Circuit Component Object. + References + ---------- >>> oEditor.CreateComponent + + Examples + -------- + >>> from ansys.aedt.core import Circuit + >>> cir = Circuit() + >>> cir.modeler.components.create_current_probe(name="probe") + >>> cir.release_desktop(False, False) """ + return self.__create_probe( + name=name, + probe_type="current", + location=location, + angle=angle, + use_instance_id_netlist=use_instance_id_netlist, + ) + + def __create_probe(self, name=None, probe_type="voltage", location=None, angle=0.0, use_instance_id_netlist=False): + if probe_type == "voltage": + component_name = "VPROBE" + elif probe_type == "current": + component_name = "IPROBE" + else: # pragma: no cover + self.logger.error("Wrong probe type assigned.") + return False + if location is None: location = [] else: location = [location[0] + 0.2 * 24.4 / 1000, location[1] + 0.2 * 24.4 / 1000] cmpid = self.create_component( - None, + name, component_library="Probes", - component_name="VPROBE", + component_name=component_name, location=location, angle=angle, use_instance_id_netlist=use_instance_id_netlist, ) - - cmpid.set_property("Name", name) + if name: + cmpid.set_property("InstanceName", name) return cmpid @pyaedt_function_handler(compname="name") diff --git a/tests/system/general/test_21_Circuit.py b/tests/system/general/test_21_Circuit.py index 5144c237bb4..6d99dd229ae 100644 --- a/tests/system/general/test_21_Circuit.py +++ b/tests/system/general/test_21_Circuit.py @@ -517,7 +517,7 @@ def test_35_netlist_data_block(self): assert self.aedtapp.analyze() def test_36_create_voltage_probe(self): - myprobe = self.aedtapp.modeler.components.create_voltage_probe(name="test_probe", location=[0.4, 0.2]) + myprobe = self.aedtapp.modeler.components.create_voltage_probe(name="voltage_probe") assert type(myprobe.id) is int def test_37_draw_graphical_primitives(self): @@ -988,3 +988,10 @@ def test_51_import_asc(self): self.aedtapp.insert_design("ASC") asc_file = os.path.join(TESTS_GENERAL_PATH, "example_models", test_subfolder, "butter.asc") assert self.aedtapp.create_schematic_from_asc_file(asc_file) + + def test_52_create_current_probe(self): + iprobe = self.aedtapp.modeler.schematic.create_current_probe(name="test_probe", location=[0.4, 0.2]) + assert type(iprobe.id) is int + assert iprobe.InstanceName == "test_probe" + iprobe2 = self.aedtapp.modeler.schematic.create_current_probe(location=[0.8, 0.2]) + assert type(iprobe2.id) is int From 0faf92870162b91571e0e4b3260271187f224e75 Mon Sep 17 00:00:00 2001 From: Hui Zhou Date: Tue, 12 Nov 2024 16:23:12 +0100 Subject: [PATCH 2/2] DOCS: configure layout doc (#5409) Co-authored-by: ring630 <@gmail.com> --- .../project/configure_edb.rst | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst b/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst index d8317179049..077094fa6e2 100644 --- a/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst +++ b/doc/source/User_guide/pyaedt_extensions_doc/project/configure_edb.rst @@ -18,10 +18,6 @@ integrity as well as power integrity analysis. :width: 800 :alt: Principle of working of Layout UI -Please refer to EDB Configuration `User Guide`_ for details - -.. _User Guide: https://edb.docs.pyansys.com/version/stable/examples/use_configuration/index.html - -------------------------------------------------------------------------- A brief description of which options are defined in the configuration file -------------------------------------------------------------------------- @@ -83,4 +79,20 @@ Configure design in siwave project 3, Click ``Select and Apply Configuration`` and browse to your configuration files. -4, In the second pop-up window. Specify where to save the new project. \ No newline at end of file +4, In the second pop-up window. Specify where to save the new project. + +~~~~~~~~~ +Resources +~~~~~~~~~ + +1, EDB Configuration `User Guide`_ for details + +.. _User Guide: https://edb.docs.pyansys.com/version/stable/examples/use_configuration/index.html + +2, `Demo video`_ + +.. _Demo video: https://www.linkedin.com/posts/electronics-simulation_accelerate-hfss-configuration-via-ansys-pyedb-activity-7252325488168177666-ypbN/?utm_source=share&utm_medium=member_desktop + +3, `Webinar Automating Signal and Power Integrity workflow with PyAEDT`_ + +.. _Webinar Automating Signal and Power Integrity workflow with PyAEDT: https://www.ansys.com/webinars/automating-signal-power-integrity-workflow-pyaedt?campaignID=7013g000000Y8uOAAS&utm_campaign=product&utm_content=digital_electronics_oktopost-Ansys+Electronics_oktopost-%25campaign_n&utm_medium=social-organic&utm_source=LinkedIn \ No newline at end of file