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Pci fixbug #13657

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merged 8 commits into from
Sep 27, 2024
Merged

Pci fixbug #13657

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6a1f013
drivers/pci/pci.c: fix warning when CONFIG_PCI_ASSIGN_ALL_BUSES=n
CV-Bowen Mar 7, 2024
d765caf
include/pci_regs: add PCI_STD_NUM_BARS macro
CV-Bowen Mar 25, 2024
b42e8ce
pci.c: fix pci 32bit warning
wyr-7 Apr 23, 2024
8fdab1e
toolchain/ghs: Fix ?? "trigraphs not allowed" warnings
Apr 23, 2024
8331dce
drivers/pci_qemu_test.c: fix compiler warning
szafonimateusz-mi Apr 27, 2024
99a168d
pci.c: fix compile warning
wyr-7 Aug 1, 2024
74e814d
drivers/pci: change all devfn type to unsigned int
CV-Bowen Mar 2, 2024
637cf27
drivers/pci: one pci device should only associate with one driver
CV-Bowen Mar 1, 2024
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16 changes: 9 additions & 7 deletions drivers/pci/pci.c
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Original file line number Diff line number Diff line change
Expand Up @@ -689,6 +689,8 @@ static void pci_setup_device(FAR struct pci_device_s *dev, int max_bar,
pci_read_config_byte(dev, PCI_COMMAND, &cmd);
pci_write_config_byte(dev, PCI_COMMAND,
cmd & ~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY);
#else
uint32_t tmp;
#endif

for (bar = 0; bar < max_bar; bar++)
Expand Down Expand Up @@ -762,8 +764,6 @@ static void pci_setup_device(FAR struct pci_device_s *dev, int max_bar,
res->start += size;
#else
UNUSED(res);
uint32_t tmp;

pci_read_config_dword(dev, base_address_0, &tmp);
if (mask & PCI_BASE_ADDRESS_SPACE_IO)
{
Expand Down Expand Up @@ -959,7 +959,7 @@ static void pci_scan_bus(FAR struct pci_bus_s *bus)
{
FAR struct pci_device_s *dev;
FAR struct pci_bus_s *child_bus;
uint32_t devfn;
unsigned int devfn;
uint32_t l;
uint32_t class;
uint8_t hdr_type;
Expand Down Expand Up @@ -1040,7 +1040,7 @@ static void pci_scan_bus(FAR struct pci_bus_s *bus)
child_bus->parent_bus = bus;

#ifdef CONFIG_PCI_ASSIGN_ALL_BUSES
child_bus->number = ctrl->busno++;
child_bus->number = bus->ctrl->busno++;
#endif

list_add_tail(&bus->children, &child_bus->node);
Expand Down Expand Up @@ -1135,7 +1135,7 @@ static int pci_enable_msi(FAR struct pci_device_s *dev, FAR int *irq,
{
mme = mmc;
num = 1 << mme;
pciinfo("Limit MME to %x, num to %d\n", mmc, num);
pciinfo("Limit MME to %"PRIx32", num to %d\n", mmc, num);
}

/* Configure MSI (arch-specific) */
Expand All @@ -1154,7 +1154,8 @@ static int pci_enable_msi(FAR struct pci_device_s *dev, FAR int *irq,

if ((flags & PCI_MSI_FLAGS_64BIT) != 0)
{
pci_write_config_dword(dev, msi + PCI_MSI_ADDRESS_HI, (mar >> 32));
pci_write_config_dword(dev, msi + PCI_MSI_ADDRESS_HI,
((uint64_t)mar >> 32));
pci_write_config_dword(dev, msi + PCI_MSI_DATA_64, mdr);
}
else
Expand Down Expand Up @@ -2010,12 +2011,13 @@ int pci_register_device(FAR struct pci_device_s *dev)
if (drv->probe(dev) >= 0)
{
dev->drv = drv;
break;
goto out;
}
}
}
}

out:
nxmutex_unlock(&g_pci_lock);
return ret;
}
Expand Down
20 changes: 12 additions & 8 deletions drivers/pci/pci_ecam.c
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Original file line number Diff line number Diff line change
Expand Up @@ -47,11 +47,13 @@
* Private Function Prototypes
****************************************************************************/

static int pci_ecam_read_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, FAR uint32_t *val);
static int pci_ecam_read_config(FAR struct pci_bus_s *bus,
unsigned int devfn, int where, int size,
FAR uint32_t *val);

static int pci_ecam_write_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, uint32_t val);
static int pci_ecam_write_config(FAR struct pci_bus_s *bus,
unsigned int devfn, int where, int size,
uint32_t val);

/****************************************************************************
* Private Types
Expand Down Expand Up @@ -168,8 +170,9 @@ static bool pci_ecam_addr_valid(FAR const struct pci_bus_s *bus,
*
****************************************************************************/

static int pci_ecam_read_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, FAR uint32_t *val)
static int pci_ecam_read_config(FAR struct pci_bus_s *bus,
unsigned int devfn, int where, int size,
FAR uint32_t *val)
{
FAR void *addr;

Expand Down Expand Up @@ -225,8 +228,9 @@ static int pci_ecam_read_config(FAR struct pci_bus_s *bus, uint32_t devfn,
*
****************************************************************************/

static int pci_ecam_write_config(FAR struct pci_bus_s *bus, uint32_t devfn,
int where, int size, uint32_t val)
static int pci_ecam_write_config(FAR struct pci_bus_s *bus,
unsigned int devfn, int where, int size,
uint32_t val)
{
FAR void *addr;

Expand Down
4 changes: 4 additions & 0 deletions drivers/pci/pci_qemu_test.c
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Original file line number Diff line number Diff line change
Expand Up @@ -319,6 +319,10 @@ static int pci_qemu_test_probe(FAR struct pci_device_s *dev)
{
ops = &g_pci_qemu_test_io_ops;
}
else
{
PANIC();
}

for (test_cnt = 0; test_cnt < 0xff; test_cnt++)
{
Expand Down
13 changes: 7 additions & 6 deletions include/nuttx/pci/pci_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
*/

#define PCI_STD_HEADER_SIZEOF 64
#define PCI_STD_NUM_BARS 6 /* Number of standard BARs */
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
Expand Down Expand Up @@ -266,13 +267,13 @@
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (/?/?) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (/?/?) */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER 7 /* (??) */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (/?/?) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (/?/?) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (/?/?) */
#define PCI_PM_DATA_REGISTER 7 /* (/?/?) */
#define PCI_PM_SIZEOF 8

/* AGP registers */
Expand Down
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