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Import XilinxUnisimLibrary as a test suite? #903

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mithro opened this issue Jun 30, 2020 · 5 comments
Open

Import XilinxUnisimLibrary as a test suite? #903

mithro opened this issue Jun 30, 2020 · 5 comments
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import-testsuite Request to import some suite of (System)Verilog code to third_party/ and run.

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@mithro
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mithro commented Jun 30, 2020

Does it make sense to import the https://github.com/SymbiFlow/XilinxUnisimLibrary library as a third_party test suite?

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mithro commented Jun 30, 2020

@hzeller @tgorochowik -- Thoughts? Is the UnisimLibrary pure verilog?

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hzeller commented Jul 10, 2020

@alainmarcel has it in the Surelog testuite in the meantime ( https://github.com/alainmarcel/Surelog/issues/568 ).

Would be worthwhile to include in sv-tests

@hzeller hzeller added the import-testsuite Request to import some suite of (System)Verilog code to third_party/ and run. label Jul 10, 2020
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hzeller commented Jul 13, 2020

Assigning to Karol for now, please delegate to whoever might be free. Having it in sv-tests will help us see how the tools deal with it (.. and/or how changes in the Unisims files change that)

Here is how they are run in Surelog (they are there in a batchfile, but it is easy to see each individual line is one invocation)
https://github.com/alainmarcel/Surelog/blob/master/third_party/tests/XilinxUnisimLibrary/batch.txt

Since we need unique names per test, maybe we just compose it from the filename with some prefix in the generate script. So file RX_BITSLICE.v would become test unisims-RX_BITSLICE maybe.

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System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API. - alainmarcel/Surelog

@mithro
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mithro commented Jul 22, 2020

@alaindargelas - The upstream sim models has been updated with the missing verilog/src/glbl.v file which should make it possible to get further along in the parsing.

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alaindargelas commented Jul 22, 2020 via email

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Labels
import-testsuite Request to import some suite of (System)Verilog code to third_party/ and run.
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