diff --git a/clash-cores/src/Clash/Cores/I2C.hs b/clash-cores/src/Clash/Cores/I2C.hs
index cb838f1cb0..2d7af77914 100644
--- a/clash-cores/src/Clash/Cores/I2C.hs
+++ b/clash-cores/src/Clash/Cores/I2C.hs
@@ -1,6 +1,10 @@
 {-# LANGUAGE CPP #-}
 
-module Clash.Cores.I2C where
+module Clash.Cores.I2C
+  ( i2c
+  , i2cTop
+  , Clash.Cores.I2C.ByteMaster.I2COperation(..)
+  ) where
 
 import Clash.Prelude hiding (read)
 
diff --git a/clash-cores/test/Test/Cores/I2C.hs b/clash-cores/test/Test/Cores/I2C.hs
index 1c949a5d0f..66fa013c78 100644
--- a/clash-cores/test/Test/Cores/I2C.hs
+++ b/clash-cores/test/Test/Cores/I2C.hs
@@ -8,9 +8,11 @@ import Clash.Explicit.Prelude
 import Clash.Cores.I2C
 
 import Data.Maybe
-import Test.Cores.I2C.Slave
 import Test.Cores.I2C.Config
-import Clash.Cores.I2C.ByteMaster (I2COperation(..))
+import Test.Cores.I2C.Slave
+import Test.Tasty
+import Test.Tasty.HUnit
+
 
 system0 :: Clock System -> Reset System -> Signal System (Vec 16 (Unsigned 8), Bool, Bool)
 system0 clk arst = bundle (registerFile,done,fault)
@@ -42,3 +44,9 @@ system = system0 systemClockGen resetGen
 
 systemResult :: (Vec 16 (Unsigned 8), Bool, Bool)
 systemResult = L.last (sampleN 200050 system)
+
+i2cTest :: TestTree
+i2cTest = testCase "i2c core testcase passed."
+  $ assertBool "i2c core test procedure failed" (not f)
+ where
+  (_, _, f) = L.last $ takeWhile (\ (_, done, _) -> not done) $ sample system
diff --git a/clash-cores/test/Test/Cores/I2C/Config.hs b/clash-cores/test/Test/Cores/I2C/Config.hs
index f020668f53..8726909107 100644
--- a/clash-cores/test/Test/Cores/I2C/Config.hs
+++ b/clash-cores/test/Test/Cores/I2C/Config.hs
@@ -54,7 +54,7 @@ configT s0 (rst,ena,cmdAck,rxAck,al) = do
       -> pure s { i2cConfStateM = CONFaddr }
       | done
       -> do display "done"
-            finish 0
+            pure s
 
     CONFaddr
       -> pure s { i2cConfStateM = CONFaddrAck
diff --git a/clash-cores/test/unittests.hs b/clash-cores/test/unittests.hs
index f4e58874a0..21849c6bbb 100644
--- a/clash-cores/test/unittests.hs
+++ b/clash-cores/test/unittests.hs
@@ -10,6 +10,7 @@ module Main where
 import Prelude
 import Test.Tasty
 
+import qualified Test.Cores.I2C
 import qualified Test.Cores.SPI
 import qualified Test.Cores.SPI.MultiSlave
 import qualified Test.Cores.UART
@@ -23,6 +24,7 @@ tests = testGroup "Unittests"
   , Test.Cores.UART.tests
   , Test.Cores.Xilinx.DcFifo.tests
   , Test.Cores.Xilinx.BlockRam.tests
+  , Test.Cores.I2C.i2cTest
   ]
 
 main :: IO ()