AMD/Zen Performance Counters

[cyring]

EXPERIMENTAL

Commit 44d678a is about the L3 Cache PMC

• PMC is programmed for the L3 Cache Miss Latency
• The UI Package cycles view is reused
  (nominally designed for Intel Package C-States)
• Monitoring is per Complex CCX.
  The associated counter starts at PC02 as the first placeholder.
• Refer to the Topology window for the Zen CCX IDs.
  So far only the first socket of a dual EPYC will be rendered.
• The CPU load bellow was supplied by 7-zip benchmark.
  7z b

• The implemented event.

Refer to the PPR specifications for other Events

[cyring]

Commit 09a50ae : AMD Zen Processors count the "Micro-ops Retired" events

• Those are grouped per Complex

• Build instructions

make AMD_ZEN_PMU=PERF

• ISO test image

[cyring]

Styling UI for AMD PMC

[cyring]

Commit 90e711e is a bit draft but I'm able to monitor the frequency of my Ryzen memory controller

Quiet system

Stressed system

(Conic > Hyperboloid of two sheets)

I'm getting some relative frequency of my G.Skill DIMMs

Build

In the Makefile, UMC is now the default of AMD_ZEN_PMC
( L3 and PERF are still available )

• Make sure to rebuild and reload all after pulling the latest commit from the develop branch.

make clean all

make[1]: Entering directory '/usr/lib/modules/5.16.13-arch1-1/build'
  CC [M]  CoreFreq/corefreqk.o
CoreFreq/corefreqk.c:11355:13: warning: ‘AMD_Zen_PMC_PERF_Counters’ defined but not used [-Wunused-function]
11355 | static void AMD_Zen_PMC_PERF_Counters(CORE_RO *Core, unsigned int T)
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~
CoreFreq/corefreqk.c:11332:13: warning: ‘AMD_Zen_PMC_L3_Counters’ defined but not used [-Wunused-function]
11332 | static void AMD_Zen_PMC_L3_Counters(CORE_RO *Core, unsigned int T)
      |             ^~~~~~~~~~~~~~~~~~~~~~~
  MODPOST CoreFreq/Module.symvers
  CC [M]  CoreFreq/corefreqk.mod.o
  LD [M]  CoreFreq/corefreqk.ko
  BTF [M] CoreFreq/corefreqk.ko
make[1]: Leaving directory '/usr/lib/modules/5.16.13-arch1-1/build'

Those warnings are OK

Run

• Start the Driver and the Daemon

insmod corefreqk.ko
corefreqd

• Start the Client directly in the Package cycles view

corefreq-cli -top package

• Press shortcut M to display the Memory Controller window
• And compare Channel frequencies beside CTR0 ... CTR7 to the Bus Rate or Bus Speed
  ( Don't bother with MC6 and TSC: I'm still wondering what to with them. Perhaps DCLOCK if available from specs: UMC, SMU, etc)

Contribute

Feel free to show your Zen, EPYC, TR results.
I need that to understand some relations between the CPU topology and the UMCs; and scale CoreFreq with enough counters.

Remarks

• Those enhancements are not for Intel processors. It should have no regression.
• Zen system with lots of DIMMs, more than 2 controllers, and so on will be greatly appreciated

[cyring]

Commit c900b76

Scaling counters to UMC x CHANNEL x DIMM

[cyring]

In commit 6b8eff3, MEMCLK is computed within the loop and now serves as a clock base ratio.

[cyring]

Since commit cd6ee61 FCLK is computed iff HSMP is available on Processor.

[cyring]

Commit f061daa : the Makefile will conditionally build the UI

make AMD_ZEN_PMC=L3 clean all
## or
make AMD_ZEN_PMC=PERF clean all
## or
make AMD_ZEN_PMC=UMC clean all