- Circuit: 16-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add16se_26Q | 0.00076 | 0.0015 | 50.00 | 0.017 | 0.5 | [Verilog] [C] |
| add16se_20J | 0.0015 | 0.0031 | 75.00 | 0.033 | 1.5 | [Verilog] [C] |
| add16se_2JY | 0.0031 | 0.0061 | 87.50 | 0.065 | 5.5 | [Verilog] [C] |
| add16se_1Y7 | 0.0069 | 0.021 | 93.75 | 0.15 | 30 | [Verilog] [C] |
| add16se_29A | 0.012 | 0.027 | 96.88 | 0.26 | 87 | [Verilog] [C] |
| add16se_2JB | 0.023 | 0.058 | 97.95 | 0.48 | 312 | [Verilog] [C] |
| add16se_2E1 | 0.049 | 0.099 | 99.80 | 1.03 | 1248 | [Verilog] [C] |
| add16se_2AS | 0.046 | 0.13 | 99.02 | 0.96 | 1281 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020