- Circuit: 16-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add16u_1E2 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add16u_0EM | 0.0018 | 0.0053 | 87.50 | 0.005 | 8.5 | [Verilog] [C] |
| add16u_1JH | 0.0066 | 0.019 | 96.88 | 0.018 | 109 | [Verilog] [C] |
| add16u_073 | 0.021 | 0.079 | 98.74 | 0.056 | 1136 | [Verilog] [C] |
| add16u_0M0 | 0.057 | 0.19 | 99.61 | 0.16 | 8209 | [Verilog] [C] |
| add16u_00G | 0.29 | 0.92 | 99.92 | 0.82 | 222640 | [Verilog] [C] |
| add16u_0GK | 0.91 | 2.90 | 99.98 | 2.49 | 20515.545e2 | [Verilog] [C] |
| add16u_02E | 3.52 | 9.74 | 99.99 | 9.54 | 30582.328e3 | [Verilog] [C] |
| add16u_0MH | 9.90 | 34.18 | 100.00 | 22.35 | 25358.103e4 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020