- Circuit: 8-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8se_7A2 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8se_8YC | 0.078 | 0.39 | 25.00 | 0.87 | 0.2 | [Verilog] [C] |
| add8se_72D | 0.27 | 0.78 | 62.40 | 2.88 | 1.0 | [Verilog] [C] |
| add8se_7LN | 0.47 | 1.17 | 62.50 | 4.89 | 2.8 | [Verilog] [C] |
| add8se_7J7 | 0.82 | 2.73 | 84.38 | 8.19 | 7.2 | [Verilog] [C] |
| add8se_91D | 1.56 | 3.52 | 96.78 | 15.45 | 20 | [Verilog] [C] |
| add8se_92J | 3.12 | 6.25 | 99.22 | 32.28 | 77 | [Verilog] [C] |
| add8se_90Z | 6.25 | 12.50 | 99.80 | 64.84 | 313 | [Verilog] [C] |
| add8se_8UN | 8.28 | 26.17 | 98.49 | 56.09 | 672 | [Verilog] [C] |
| add8se_8XS | 25.00 | 50.00 | 99.95 | 249.36 | 4798 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020