- Circuit: 8-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8se_7A2 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8se_8V4 | 0.20 | 0.39 | 50.00 | 2.28 | 0.5 | [Verilog] [C] |
| add8se_91Y | 0.39 | 0.78 | 75.00 | 4.02 | 1.5 | [Verilog] [C] |
| add8se_90R | 0.78 | 1.56 | 87.50 | 8.05 | 5.5 | [Verilog] [C] |
| add8se_8ZU | 1.56 | 3.12 | 93.75 | 16.11 | 22 | [Verilog] [C] |
| add8se_92J | 3.12 | 6.25 | 99.22 | 32.28 | 77 | [Verilog] [C] |
| add8se_90Z | 6.25 | 12.50 | 99.80 | 64.84 | 313 | [Verilog] [C] |
| add8se_8UN | 8.28 | 26.17 | 98.49 | 56.09 | 672 | [Verilog] [C] |
| add8se_8XS | 25.00 | 50.00 | 99.95 | 249.36 | 4798 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020