- Circuit: 9-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add9se_07Y | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add9se_0E4 | 0.18 | 0.39 | 68.75 | 2.06 | 1.2 | [Verilog] [C] |
| add9se_077 | 0.29 | 0.59 | 87.50 | 3.42 | 3.0 | [Verilog] [C] |
| add9se_0DX | 0.47 | 1.37 | 84.38 | 5.20 | 9.0 | [Verilog] [C] |
| add9se_07F | 0.94 | 2.73 | 94.14 | 9.31 | 33 | [Verilog] [C] |
| add9se_036 | 1.72 | 5.08 | 96.88 | 18.00 | 112 | [Verilog] [C] |
| add9se_056 | 3.05 | 7.03 | 99.12 | 34.40 | 300 | [Verilog] [C] |
| add9se_048 | 4.98 | 12.50 | 98.97 | 55.73 | 896 | [Verilog] [C] |
| add9se_0AL | 7.83 | 24.80 | 99.24 | 74.66 | 2406 | [Verilog] [C] |
| add9se_0DV | 14.37 | 49.61 | 99.53 | 69.54 | 8574 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020