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Selected circuits

  • Circuit: 16-bit unsigned multiplier
  • Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters

Parameters of selected circuits

Circuit name MAE% WCE% EP% MRE% MSE Download
mul16u_BMC 0.00 0.00 0.00 0.00 0 [Verilog] [VerilogPDK45] [C]
mul16u_52B 0.000000068 0.00000021 71.09 0.0000097 16 [Verilog] [VerilogPDK45] [C]
mul16u_C37 0.00000096 0.0000032 98.37 0.00013 2581 [Verilog] [VerilogPDK45] [C]
mul16u_679 0.000011 0.000051 99.15 0.0011 329216 [Verilog] [VerilogPDK45] [C]
mul16u_F6B 0.000075 0.00042 99.84 0.0067 16238.254e3 [Verilog] [VerilogPDK45] [C]
mul16u_94L 0.0013 0.0062 99.98 0.083 44379.574e5 [Verilog] [VerilogPDK45] [C]
mul16u_8VH 0.011 0.058 100.00 0.46 32818.049e7 [Verilog] [C]
mul16u_GPE 0.16 0.63 100.00 3.06 55158.891e9 [Verilog] [VerilogPDK45] [C]
mul16u_H6G 1.76 7.03 100.00 19.30 73909.015e11 [Verilog] [VerilogPDK45] [C]
mul16u_G9P 15.62 62.50 100.00 79.49 71651.74e13 [Verilog] [C]

Parameters

Parameters figure

References

  • V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362