- Circuit: 7-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul7u_01L | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul7u_0CZ | 0.025 | 0.092 | 77.61 | 0.72 | 30 | [Verilog] [C] |
| mul7u_08B | 0.027 | 0.092 | 79.54 | 0.76 | 34 | [Verilog] [C] |
| mul7u_03M | 0.03 | 0.092 | 82.61 | 0.98 | 40 | [Verilog] [C] |
| mul7u_0B2 | 0.058 | 0.19 | 85.08 | 1.68 | 155 | [Verilog] [C] |
| mul7u_0DE | 0.051 | 0.19 | 87.35 | 1.44 | 115 | [Verilog] [C] |
| mul7u_0ED | 0.13 | 0.49 | 92.88 | 3.06 | 709 | [Verilog] [C] |
| mul7u_093 | 0.24 | 0.99 | 95.40 | 5.32 | 2487 | [Verilog] [C] |
| mul7u_0CA | 5.09 | 19.05 | 98.41 | 46.83 | 11107.118e2 | [Verilog] [C] |
- V. Mrazek, S. S. Sarwar, L. Sekanina, Z. Vasicek and K. Roy, "Design of power-efficient approximate multipliers for approximate artificial neural networks," 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2016, pp. 1-7. doi: 10.1145/2966986.2967021