- Circuit: 8x2-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x2u_106 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x2u_0LK | 0.073 | 1.56 | 4.69 | 0.64 | 12 | [Verilog] [C] |
| mul8x2u_166 | 0.049 | 0.39 | 12.50 | 0.81 | 2.0 | [Verilog] [C] |
| mul8x2u_0PJ | 0.049 | 0.20 | 25.00 | 0.76 | 1.0 | [Verilog] [C] |
| mul8x2u_0S7 | 0.067 | 0.29 | 37.50 | 1.45 | 1.5 | [Verilog] [C] |
| mul8x2u_015 | 0.17 | 0.68 | 56.25 | 3.54 | 7.0 | [Verilog] [C] |
| mul8x2u_0SV | 0.32 | 1.46 | 65.62 | 6.33 | 23 | [Verilog] [C] |
| mul8x2u_0NG | 18.68 | 74.71 | 74.71 | 100.00 | 76011 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020