- Circuit: 8x4-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x4u_2UU | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x4u_3AA | 0.018 | 0.049 | 37.50 | 0.50 | 1.5 | [Verilog] [C] |
| mul8x4u_485 | 0.039 | 0.15 | 60.79 | 0.90 | 5.3 | [Verilog] [C] |
| mul8x4u_3BJ | 0.082 | 0.29 | 73.34 | 1.86 | 20 | [Verilog] [C] |
| mul8x4u_29J | 0.26 | 0.81 | 88.33 | 5.76 | 189 | [Verilog] [C] |
| mul8x4u_3Y3 | 0.66 | 2.17 | 91.16 | 10.34 | 1164 | [Verilog] [C] |
| mul8x4u_2AE | 1.45 | 5.35 | 92.72 | 20.48 | 5621 | [Verilog] [C] |
| mul8x4u_1TT | 3.76 | 13.75 | 92.99 | 38.63 | 37866 | [Verilog] [C] |
| mul8x4u_134 | 9.08 | 34.11 | 93.33 | 67.10 | 230371 | [Verilog] [C] |
| mul8x4u_555 | 23.35 | 93.38 | 93.38 | 100.00 | 16831.062e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020