- Circuit: 8x5-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x5u_4E8 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x5u_379 | 0.0031 | 0.098 | 3.12 | 0.063 | 2.0 | [Verilog] [C] |
| mul8x5u_1HM | 0.12 | 1.56 | 13.57 | 1.17 | 1020 | [Verilog] [C] |
| mul8x5u_41G | 0.0093 | 0.037 | 40.62 | 0.26 | 1.7 | [Verilog] [C] |
| mul8x5u_4B0 | 0.012 | 0.061 | 50.00 | 0.39 | 2.2 | [Verilog] [C] |
| mul8x5u_52X | 0.028 | 0.11 | 62.50 | 0.77 | 11 | [Verilog] [C] |
| mul8x5u_3BF | 0.036 | 0.11 | 70.31 | 1.03 | 16 | [Verilog] [C] |
| mul8x5u_3UR | 0.13 | 0.44 | 84.86 | 2.99 | 200 | [Verilog] [C] |
| mul8x5u_541 | 24.12 | 96.50 | 96.50 | 100.00 | 70690.462e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020