- Circuit: 8x6-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x6u_049 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x6u_2F5 | 0.011 | 0.20 | 5.47 | 0.18 | 56 | [Verilog] [C] |
| mul8x6u_1FJ | 2.57 | 12.89 | 25.20 | 7.96 | 856704 | [Verilog] [C] |
| mul8x6u_5TS | 0.0045 | 0.012 | 37.11 | 0.16 | 1.5 | [Verilog] [C] |
| mul8x6u_4TY | 0.014 | 0.037 | 62.50 | 0.47 | 10 | [Verilog] [C] |
| mul8x6u_446 | 0.019 | 0.061 | 73.83 | 0.60 | 17 | [Verilog] [C] |
| mul8x6u_3DQ | 0.07 | 0.29 | 86.56 | 1.70 | 219 | [Verilog] [C] |
| mul8x6u_51C | 24.51 | 98.05 | 98.05 | 100.00 | 28960.286e3 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020