- Circuit: 8x7-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x7u_0V5 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x7u_5FH | 0.0015 | 0.0061 | 37.50 | 0.059 | 0.75 | [Verilog] [C] |
| mul8x7u_3Y3 | 0.006 | 0.021 | 76.95 | 0.22 | 7.0 | [Verilog] [C] |
| mul8x7u_3C6 | 0.021 | 0.064 | 83.59 | 0.69 | 79 | [Verilog] [C] |
| mul8x7u_36L | 0.081 | 0.30 | 92.92 | 2.16 | 1105 | [Verilog] [C] |
| mul8x7u_4DP | 0.22 | 0.92 | 97.83 | 5.13 | 8076 | [Verilog] [C] |
| mul8x7u_44V | 0.56 | 2.39 | 98.57 | 10.75 | 51673 | [Verilog] [C] |
| mul8x7u_15S | 2.66 | 9.76 | 98.77 | 30.68 | 11319.049e2 | [Verilog] [C] |
| mul8x7u_056 | 9.73 | 30.62 | 98.83 | 62.41 | 16898.093e3 | [Verilog] [C] |
| mul8x7u_4MC | 24.71 | 98.83 | 98.83 | 100.00 | 11722.021e4 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020