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Selected circuits

  • Circuit: 8-bit signed multiplier
  • Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters

Parameters of selected circuits

Circuit name MAE% WCE% EP% MRE% MSE Download
mul8s_1KV8 0.00 0.00 0.00 0.00 0 [Verilog] [VerilogPDK45] [C]
mul8s_1KVA 0.0018 0.0076 50.00 0.28 3.8 [Verilog] [VerilogPDK45] [C]
mul8s_1KVB 0.0064 0.026 68.75 0.90 34 [Verilog] [VerilogPDK45] [C]
mul8s_1KX2 0.019 0.075 81.25 2.53 248 [Verilog] [VerilogPDK45] [C]
mul8s_1KR6 0.051 0.21 74.80 2.73 2746 [Verilog] [VerilogPDK45] [C]
mul8s_1L2H 0.081 0.39 74.61 4.41 5462 [Verilog] [VerilogPDK45] [C]
mul8s_1L2D 0.23 1.16 93.16 12.26 38236 [Verilog] [VerilogPDK45] [C]
mul8s_1L1G 0.52 2.66 97.75 27.44 191238 [Verilog] [VerilogPDK45] [C]
mul8s_1KR3 3.08 12.30 98.05 135.77 72829.102e2 [Verilog] [VerilogPDK45] [C]

Parameters

Parameters figure

References

  • V. Mrazek, Z. Vasicek, L. Sekanina, H. Jiang and J. Han, "Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 11, pp. 2572-2576, Nov. 2018. doi: 10.1109/TVLSI.2018.2856362