- Circuit: 8-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8u_1JFF | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| mul8u_Y48 | 0.00019 | 0.0031 | 6.25 | 0.0053 | 0.25 | [Verilog] [C] |
| mul8u_LM7 | 0.0014 | 0.015 | 19.53 | 0.033 | 5.0 | [Verilog] [C] |
| mul8u_150Q | 0.0076 | 0.064 | 37.30 | 0.15 | 93 | [Verilog] [C] |
| mul8u_2AC | 0.037 | 0.12 | 98.12 | 1.25 | 892 | [Verilog] [C] |
| mul8u_185Q | 0.18 | 0.79 | 98.05 | 4.16 | 22286 | [Verilog] [C] |
| mul8u_FTA | 0.89 | 4.29 | 98.74 | 13.96 | 543210 | [Verilog] [C] |
| mul8u_13QR | 4.83 | 19.46 | 99.20 | 44.00 | 15608.397e3 | [Verilog] [C] |
| mul8u_E9R | 24.81 | 99.22 | 99.22 | 100.00 | 47164.981e4 | [Verilog] [C] |
- V. Mrazek, R. Hrbacek, Z. Vasicek and L. Sekanina, "EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 258-261. doi: 10.23919/DATE.2017.7926993