CLK Gen mixed up T4/T5?

[ogamespec]

@msinger, Hi.

Please check the ports T4 and T5. It looks like they are mixed up. If you do them like you do, the simulation does not start (IDU will overwrite its results).

https://github.com/emu-russia/dmgcpu/blob/main/clk.md

[msinger]

Thank you for the information. I will check immediately.

[msinger]

Yes, thank you very much. This seems to be a remnant of issue msinger/dmg-schematics#148 that we haven't spotted.

I will change the names of the CPU ports in our schematics once you settled for good ones that make sense from the CPUs perspective. They were just guesses based on which signals change on the cartridge connector during the edges of these clocks. So you don't really need to have them in your table.

I haven't noticed before that @Gekkio is also looking into the CPU. That's great. He also has good pictures.

[msinger]

Fixed in commit msinger/dmg-schematics@2b100a6, no new PDF yet though.