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vmx.c
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vmx.c
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/*-
* Copyright (c) 2011 NetApp, Inc.
* Copyright (c) 2015 xhyve developers
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <stdio.h>
#include <errno.h>
#include <assert.h>
#include <Hypervisor/hv.h>
#include <Hypervisor/hv_vmx.h>
#include <xhyve/support/misc.h>
#include <xhyve/support/atomic.h>
#include <xhyve/support/psl.h>
#include <xhyve/support/specialreg.h>
#include <xhyve/vmm/vmm.h>
#include <xhyve/vmm/vmm_instruction_emul.h>
#include <xhyve/vmm/vmm_lapic.h>
#include <xhyve/vmm/vmm_host.h>
#include <xhyve/vmm/vmm_ktr.h>
#include <xhyve/vmm/vmm_stat.h>
#include <xhyve/vmm/io/vatpic.h>
#include <xhyve/vmm/io/vlapic.h>
#include <xhyve/vmm/io/vlapic_priv.h>
#include <xhyve/vmm/intel/vmx.h>
#include <xhyve/vmm/intel/vmx_msr.h>
#include <xhyve/vmm/x86.h>
#include <xhyve/vmm/intel/vmx_controls.h>
#define PROCBASED_CTLS_WINDOW_SETTING \
(PROCBASED_INT_WINDOW_EXITING | \
PROCBASED_NMI_WINDOW_EXITING)
#define PROCBASED_CTLS_ONE_SETTING \
(PROCBASED_SECONDARY_CONTROLS | \
PROCBASED_MWAIT_EXITING | \
PROCBASED_MONITOR_EXITING | \
PROCBASED_IO_EXITING | \
PROCBASED_MSR_BITMAPS | \
PROCBASED_CTLS_WINDOW_SETTING | \
PROCBASED_CR8_LOAD_EXITING | \
PROCBASED_CR8_STORE_EXITING | \
PROCBASED_HLT_EXITING | \
PROCBASED_TSC_OFFSET)
#define PROCBASED_CTLS_ZERO_SETTING \
(PROCBASED_CR3_LOAD_EXITING | \
PROCBASED_CR3_STORE_EXITING | \
PROCBASED_IO_BITMAPS | \
PROCBASED_RDTSC_EXITING | \
PROCBASED_USE_TPR_SHADOW | \
PROCBASED_MOV_DR_EXITING | \
PROCBASED_MTF | \
PROCBASED_INVLPG_EXITING | \
PROCBASED_PAUSE_EXITING)
#define PROCBASED_CTLS2_ONE_SETTING \
(PROCBASED2_ENABLE_EPT | \
PROCBASED2_UNRESTRICTED_GUEST | \
PROCBASED2_ENABLE_VPID | \
PROCBASED2_ENABLE_RDTSCP)
#define PROCBASED_CTLS2_ZERO_SETTING \
(PROCBASED2_VIRTUALIZE_APIC_ACCESSES | \
PROCBASED2_DESC_TABLE_EXITING | \
PROCBASED2_WBINVD_EXITING | \
PROCBASED2_PAUSE_LOOP_EXITING /* FIXME */ | \
PROCBASED2_RDRAND_EXITING | \
PROCBASED2_ENABLE_INVPCID /* FIXME */ | \
PROCBASED2_RDSEED_EXITING)
#define PINBASED_CTLS_ONE_SETTING \
(PINBASED_EXTINT_EXITING | \
PINBASED_NMI_EXITING | \
PINBASED_VIRTUAL_NMI)
#define PINBASED_CTLS_ZERO_SETTING \
(PINBASED_PREMPTION_TIMER)
#define VM_ENTRY_CTLS_ONE_SETTING \
(VM_ENTRY_LOAD_EFER)
#define VM_ENTRY_CTLS_ZERO_SETTING \
(VM_ENTRY_INTO_SMM | \
VM_ENTRY_DEACTIVATE_DUAL_MONITOR | \
VM_ENTRY_GUEST_LMA)
#define VM_EXIT_CTLS_ONE_SETTING \
(VM_EXIT_HOST_LMA | \
VM_EXIT_LOAD_EFER)
#define VM_EXIT_CTLS_ZERO_SETTING \
(VM_EXIT_SAVE_PREEMPTION_TIMER)
#define NMI_BLOCKING \
(VMCS_INTERRUPTIBILITY_NMI_BLOCKING | \
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)
#define HWINTR_BLOCKING \
(VMCS_INTERRUPTIBILITY_STI_BLOCKING | \
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)
#define HANDLED 1
#define UNHANDLED 0
static uint32_t pinbased_ctls, procbased_ctls, procbased_ctls2;
static uint32_t exit_ctls, entry_ctls;
static uint64_t cr0_ones_mask, cr0_zeros_mask;
static uint64_t cr4_ones_mask, cr4_zeros_mask;
/*
* Optional capabilities
*/
static int cap_halt_exit;
static int cap_pause_exit;
// static int cap_unrestricted_guest;
static int cap_monitor_trap;
// static int cap_invpcid;
// static int pirvec = -1;
// static struct unrhdr *vpid_unr;
// static u_int vpid_alloc_failed;
/*
* Use the last page below 4GB as the APIC access address. This address is
* occupied by the boot firmware so it is guaranteed that it will not conflict
* with a page in system memory.
*/
// #define APIC_ACCESS_ADDRESS 0xFFFFF000
static int vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc);
static int vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval);
static __inline uint64_t
reg_read(int vcpuid, hv_x86_reg_t reg) {
uint64_t val;
hv_vcpu_read_register(((hv_vcpuid_t) vcpuid), reg, &val);
return val;
}
static __inline void
reg_write(int vcpuid, hv_x86_reg_t reg, uint64_t val) {
hv_vcpu_write_register(((hv_vcpuid_t) vcpuid), reg, val);
}
static void hvdump(int vcpu) {
printf("VMCS_PIN_BASED_CTLS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_PIN_BASED_CTLS));
printf("VMCS_PRI_PROC_BASED_CTLS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_PRI_PROC_BASED_CTLS));
printf("VMCS_SEC_PROC_BASED_CTLS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_SEC_PROC_BASED_CTLS));
printf("VMCS_ENTRY_CTLS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_ENTRY_CTLS));
printf("VMCS_EXCEPTION_BITMAP: 0x%016llx\n",
vmcs_read(vcpu, VMCS_EXCEPTION_BITMAP));
printf("VMCS_CR0_MASK: 0x%016llx\n",
vmcs_read(vcpu, VMCS_CR0_MASK));
printf("VMCS_CR0_SHADOW: 0x%016llx\n",
vmcs_read(vcpu, VMCS_CR0_SHADOW));
printf("VMCS_CR4_MASK: 0x%016llx\n",
vmcs_read(vcpu, VMCS_CR4_MASK));
printf("VMCS_CR4_SHADOW: 0x%016llx\n",
vmcs_read(vcpu, VMCS_CR4_SHADOW));
printf("VMCS_GUEST_CS_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_CS_SELECTOR));
printf("VMCS_GUEST_CS_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_CS_LIMIT));
printf("VMCS_GUEST_CS_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_CS_ACCESS_RIGHTS));
printf("VMCS_GUEST_CS_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_CS_BASE));
printf("VMCS_GUEST_DS_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_DS_SELECTOR));
printf("VMCS_GUEST_DS_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_DS_LIMIT));
printf("VMCS_GUEST_DS_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_DS_ACCESS_RIGHTS));
printf("VMCS_GUEST_DS_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_DS_BASE));
printf("VMCS_GUEST_ES_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_ES_SELECTOR));
printf("VMCS_GUEST_ES_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_ES_LIMIT));
printf("VMCS_GUEST_ES_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_ES_ACCESS_RIGHTS));
printf("VMCS_GUEST_ES_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_ES_BASE));
printf("VMCS_GUEST_FS_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_FS_SELECTOR));
printf("VMCS_GUEST_FS_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_FS_LIMIT));
printf("VMCS_GUEST_FS_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_FS_ACCESS_RIGHTS));
printf("VMCS_GUEST_FS_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_FS_BASE));
printf("VMCS_GUEST_GS_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_GS_SELECTOR));
printf("VMCS_GUEST_GS_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_GS_LIMIT));
printf("VMCS_GUEST_GS_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_GS_ACCESS_RIGHTS));
printf("VMCS_GUEST_GS_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_GS_BASE));
printf("VMCS_GUEST_SS_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_SS_SELECTOR));
printf("VMCS_GUEST_SS_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_SS_LIMIT));
printf("VMCS_GUEST_SS_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_SS_ACCESS_RIGHTS));
printf("VMCS_GUEST_SS_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_SS_BASE));
printf("VMCS_GUEST_LDTR_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_LDTR_SELECTOR));
printf("VMCS_GUEST_LDTR_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_LDTR_LIMIT));
printf("VMCS_GUEST_LDTR_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_LDTR_ACCESS_RIGHTS));
printf("VMCS_GUEST_LDTR_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_LDTR_BASE));
printf("VMCS_GUEST_TR_SELECTOR: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_TR_SELECTOR));
printf("VMCS_GUEST_TR_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_TR_LIMIT));
printf("VMCS_GUEST_TR_ACCESS_RIGHTS: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS));
printf("VMCS_GUEST_TR_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_TR_BASE));
printf("VMCS_GUEST_GDTR_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_GDTR_LIMIT));
printf("VMCS_GUEST_GDTR_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_GDTR_BASE));
printf("VMCS_GUEST_IDTR_LIMIT: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_LDTR_LIMIT));
printf("VMCS_GUEST_IDTR_BASE: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_LDTR_BASE));
printf("VMCS_GUEST_CR0: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_CR0));
printf("VMCS_GUEST_CR3: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_CR3));
printf("VMCS_GUEST_CR4: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_CR4));
printf("VMCS_GUEST_IA32_EFER: 0x%016llx\n",
vmcs_read(vcpu, VMCS_GUEST_IA32_EFER));
printf("\n");
printf("rip: 0x%016llx rfl: 0x%016llx cr2: 0x%016llx\n",
reg_read(vcpu, HV_X86_RIP), reg_read(vcpu, HV_X86_RFLAGS),
reg_read(vcpu, HV_X86_CR2));
printf("rax: 0x%016llx rbx: 0x%016llx rcx: 0x%016llx rdx: 0x%016llx\n",
reg_read(vcpu, HV_X86_RAX), reg_read(vcpu, HV_X86_RBX),
reg_read(vcpu, HV_X86_RCX), reg_read(vcpu, HV_X86_RDX));
printf("rsi: 0x%016llx rdi: 0x%016llx rbp: 0x%016llx rsp: 0x%016llx\n",
reg_read(vcpu, HV_X86_RSI), reg_read(vcpu, HV_X86_RDI),
reg_read(vcpu, HV_X86_RBP), reg_read(vcpu, HV_X86_RSP));
printf("r8: 0x%016llx r9: 0x%016llx r10: 0x%016llx r11: 0x%016llx\n",
reg_read(vcpu, HV_X86_R8), reg_read(vcpu, HV_X86_R9),
reg_read(vcpu, HV_X86_R10), reg_read(vcpu, HV_X86_R11));
printf("r12: 0x%016llx r13: 0x%016llx r14: 0x%016llx r15: 0x%016llx\n",
reg_read(vcpu, HV_X86_R12), reg_read(vcpu, HV_X86_R12),
reg_read(vcpu, HV_X86_R14), reg_read(vcpu, HV_X86_R15));
}
#ifdef XHYVE_CONFIG_TRACE
static const char *
exit_reason_to_str(int reason)
{
static char reasonbuf[32];
switch (reason) {
case EXIT_REASON_EXCEPTION:
return "exception";
case EXIT_REASON_EXT_INTR:
return "extint";
case EXIT_REASON_TRIPLE_FAULT:
return "triplefault";
case EXIT_REASON_INIT:
return "init";
case EXIT_REASON_SIPI:
return "sipi";
case EXIT_REASON_IO_SMI:
return "iosmi";
case EXIT_REASON_SMI:
return "smi";
case EXIT_REASON_INTR_WINDOW:
return "intrwindow";
case EXIT_REASON_NMI_WINDOW:
return "nmiwindow";
case EXIT_REASON_TASK_SWITCH:
return "taskswitch";
case EXIT_REASON_CPUID:
return "cpuid";
case EXIT_REASON_GETSEC:
return "getsec";
case EXIT_REASON_HLT:
return "hlt";
case EXIT_REASON_INVD:
return "invd";
case EXIT_REASON_INVLPG:
return "invlpg";
case EXIT_REASON_RDPMC:
return "rdpmc";
case EXIT_REASON_RDTSC:
return "rdtsc";
case EXIT_REASON_RSM:
return "rsm";
case EXIT_REASON_VMCALL:
return "vmcall";
case EXIT_REASON_VMCLEAR:
return "vmclear";
case EXIT_REASON_VMLAUNCH:
return "vmlaunch";
case EXIT_REASON_VMPTRLD:
return "vmptrld";
case EXIT_REASON_VMPTRST:
return "vmptrst";
case EXIT_REASON_VMREAD:
return "vmread";
case EXIT_REASON_VMRESUME:
return "vmresume";
case EXIT_REASON_VMWRITE:
return "vmwrite";
case EXIT_REASON_VMXOFF:
return "vmxoff";
case EXIT_REASON_VMXON:
return "vmxon";
case EXIT_REASON_CR_ACCESS:
return "craccess";
case EXIT_REASON_DR_ACCESS:
return "draccess";
case EXIT_REASON_INOUT:
return "inout";
case EXIT_REASON_RDMSR:
return "rdmsr";
case EXIT_REASON_WRMSR:
return "wrmsr";
case EXIT_REASON_INVAL_VMCS:
return "invalvmcs";
case EXIT_REASON_INVAL_MSR:
return "invalmsr";
case EXIT_REASON_MWAIT:
return "mwait";
case EXIT_REASON_MTF:
return "mtf";
case EXIT_REASON_MONITOR:
return "monitor";
case EXIT_REASON_PAUSE:
return "pause";
case EXIT_REASON_MCE_DURING_ENTRY:
return "mce-during-entry";
case EXIT_REASON_TPR:
return "tpr";
case EXIT_REASON_APIC_ACCESS:
return "apic-access";
case EXIT_REASON_GDTR_IDTR:
return "gdtridtr";
case EXIT_REASON_LDTR_TR:
return "ldtrtr";
case EXIT_REASON_EPT_FAULT:
return "eptfault";
case EXIT_REASON_EPT_MISCONFIG:
return "eptmisconfig";
case EXIT_REASON_INVEPT:
return "invept";
case EXIT_REASON_RDTSCP:
return "rdtscp";
case EXIT_REASON_VMX_PREEMPT:
return "vmxpreempt";
case EXIT_REASON_INVVPID:
return "invvpid";
case EXIT_REASON_WBINVD:
return "wbinvd";
case EXIT_REASON_XSETBV:
return "xsetbv";
case EXIT_REASON_APIC_WRITE:
return "apic-write";
default:
snprintf(reasonbuf, sizeof(reasonbuf), "%d", reason);
return (reasonbuf);
}
}
#endif /* XHYVE_CONFIG_TRACE */
// static int
// vmx_allow_x2apic_msrs(struct vmx *vmx)
// {
// int i, error;
// error = 0;
// /*
// * Allow readonly access to the following x2APIC MSRs from the guest.
// */
// error += guest_msr_ro(vmx, MSR_APIC_ID);
// error += guest_msr_ro(vmx, MSR_APIC_VERSION);
// error += guest_msr_ro(vmx, MSR_APIC_LDR);
// error += guest_msr_ro(vmx, MSR_APIC_SVR);
// for (i = 0; i < 8; i++)
// error += guest_msr_ro(vmx, MSR_APIC_ISR0 + i);
// for (i = 0; i < 8; i++)
// error += guest_msr_ro(vmx, MSR_APIC_TMR0 + i);
// for (i = 0; i < 8; i++)
// error += guest_msr_ro(vmx, MSR_APIC_IRR0 + i);
// error += guest_msr_ro(vmx, MSR_APIC_ESR);
// error += guest_msr_ro(vmx, MSR_APIC_LVT_TIMER);
// error += guest_msr_ro(vmx, MSR_APIC_LVT_THERMAL);
// error += guest_msr_ro(vmx, MSR_APIC_LVT_PCINT);
// error += guest_msr_ro(vmx, MSR_APIC_LVT_LINT0);
// error += guest_msr_ro(vmx, MSR_APIC_LVT_LINT1);
// error += guest_msr_ro(vmx, MSR_APIC_LVT_ERROR);
// error += guest_msr_ro(vmx, MSR_APIC_ICR_TIMER);
// error += guest_msr_ro(vmx, MSR_APIC_DCR_TIMER);
// error += guest_msr_ro(vmx, MSR_APIC_ICR);
// /*
// * Allow TPR, EOI and SELF_IPI MSRs to be read and written by the guest.
// *
// * These registers get special treatment described in the section
// * "Virtualizing MSR-Based APIC Accesses".
// */
// error += guest_msr_rw(vmx, MSR_APIC_TPR);
// error += guest_msr_rw(vmx, MSR_APIC_EOI);
// error += guest_msr_rw(vmx, MSR_APIC_SELF_IPI);
// return (error);
// }
u_long
vmx_fix_cr0(u_long cr0)
{
return ((cr0 | cr0_ones_mask) & ~cr0_zeros_mask);
}
u_long
vmx_fix_cr4(u_long cr4)
{
return ((cr4 | cr4_ones_mask) & ~cr4_zeros_mask);
}
static int
vmx_cleanup(void)
{
return (0);
}
static int
vmx_init(void)
{
int error = hv_vm_create(HV_VM_DEFAULT);
if (error) {
if (error == HV_NO_DEVICE) {
printf("vmx_init: processor not supported by "
"Hypervisor.framework\n");
return (error);
}
else
xhyve_abort("hv_vm_create failed\n");
}
/* Check support for primary processor-based VM-execution controls */
error = vmx_set_ctlreg(HV_VMX_CAP_PROCBASED,
PROCBASED_CTLS_ONE_SETTING,
PROCBASED_CTLS_ZERO_SETTING, &procbased_ctls);
if (error) {
printf("vmx_init: processor does not support desired primary "
"processor-based controls\n");
return (error);
}
/* Clear the processor-based ctl bits that are set on demand */
procbased_ctls &= ~PROCBASED_CTLS_WINDOW_SETTING;
/* Check support for secondary processor-based VM-execution controls */
error = vmx_set_ctlreg(HV_VMX_CAP_PROCBASED2,
PROCBASED_CTLS2_ONE_SETTING,
PROCBASED_CTLS2_ZERO_SETTING, &procbased_ctls2);
if (error) {
printf("vmx_init: processor does not support desired secondary "
"processor-based controls\n");
return (error);
}
/* Check support for pin-based VM-execution controls */
error = vmx_set_ctlreg(HV_VMX_CAP_PINBASED,
PINBASED_CTLS_ONE_SETTING,
PINBASED_CTLS_ZERO_SETTING, &pinbased_ctls);
if (error) {
printf("vmx_init: processor does not support desired "
"pin-based controls\n");
return (error);
}
/* Check support for VM-exit controls */
error = vmx_set_ctlreg(HV_VMX_CAP_EXIT,
VM_EXIT_CTLS_ONE_SETTING,
VM_EXIT_CTLS_ZERO_SETTING,
&exit_ctls);
if (error) {
printf("vmx_init: processor does not support desired "
"exit controls\n");
return (error);
}
/* Check support for VM-entry controls */
error = vmx_set_ctlreg(HV_VMX_CAP_ENTRY,
VM_ENTRY_CTLS_ONE_SETTING, VM_ENTRY_CTLS_ZERO_SETTING,
&entry_ctls);
if (error) {
printf("vmx_init: processor does not support desired "
"entry controls\n");
return (error);
}
/*
* Check support for optional features by testing them
* as individual bits
*/
cap_halt_exit = 1;
cap_monitor_trap = 1;
cap_pause_exit = 1;
// cap_unrestricted_guest = 1;
// cap_invpcid = 1;
/* FIXME */
cr0_ones_mask = cr4_ones_mask = 0;
cr0_zeros_mask = cr4_zeros_mask = 0;
cr0_ones_mask |= (CR0_NE | CR0_ET);
cr0_zeros_mask |= (CR0_NW | CR0_CD);
cr4_ones_mask = 0x2000;
vmx_msr_init();
return (0);
}
static int
vmx_setup_cr_shadow(int vcpuid, int which, uint32_t initial)
{
int error, mask_ident, shadow_ident;
uint64_t mask_value;
if (which != 0 && which != 4)
xhyve_abort("vmx_setup_cr_shadow: unknown cr%d", which);
if (which == 0) {
mask_ident = VMCS_CR0_MASK;
mask_value = (cr0_ones_mask | cr0_zeros_mask) | (CR0_PG | CR0_PE);
shadow_ident = VMCS_CR0_SHADOW;
} else {
mask_ident = VMCS_CR4_MASK;
mask_value = cr4_ones_mask | cr4_zeros_mask;
shadow_ident = VMCS_CR4_SHADOW;
}
error = vmcs_setreg(vcpuid, VMCS_IDENT(mask_ident), mask_value);
if (error)
return (error);
error = vmcs_setreg(vcpuid, VMCS_IDENT(shadow_ident), initial);
if (error)
return (error);
return (0);
}
#define vmx_setup_cr0_shadow(vcpuid,init) vmx_setup_cr_shadow(vcpuid, 0, (init))
#define vmx_setup_cr4_shadow(vcpuid,init) vmx_setup_cr_shadow(vcpuid, 4, (init))
static void *
vmx_vm_init(struct vm *vm)
{
struct vmx *vmx;
vmx = malloc(sizeof(struct vmx));
assert(vmx);
bzero(vmx, sizeof(struct vmx));
vmx->vm = vm;
return (vmx);
}
static int
vmx_vcpu_init(void *arg, int vcpuid) {
uint32_t exc_bitmap;
struct vmx *vmx;
hv_vcpuid_t hvid;
int error;
vmx = (struct vmx *) arg;
if (hv_vcpu_create(&hvid, HV_VCPU_DEFAULT)) {
xhyve_abort("hv_vcpu_create failed\n");
}
if (hvid != ((hv_vcpuid_t) vcpuid)) {
/* FIXME */
xhyve_abort("vcpu id mismatch\n");
}
if (hv_vcpu_enable_native_msr(hvid, MSR_GSBASE, 1) ||
hv_vcpu_enable_native_msr(hvid, MSR_FSBASE, 1) ||
hv_vcpu_enable_native_msr(hvid, MSR_SYSENTER_CS_MSR, 1) ||
hv_vcpu_enable_native_msr(hvid, MSR_SYSENTER_ESP_MSR, 1) ||
hv_vcpu_enable_native_msr(hvid, MSR_SYSENTER_EIP_MSR, 1) ||
hv_vcpu_enable_native_msr(hvid, MSR_TSC, 1) ||
hv_vcpu_enable_native_msr(hvid, MSR_IA32_TSC_AUX, 1))
{
xhyve_abort("vmx_vcpu_init: error setting guest msr access\n");
}
vmx_msr_guest_init(vmx, vcpuid);
vmcs_write(vcpuid, VMCS_PIN_BASED_CTLS, pinbased_ctls);
vmcs_write(vcpuid, VMCS_PRI_PROC_BASED_CTLS, procbased_ctls);
vmcs_write(vcpuid, VMCS_SEC_PROC_BASED_CTLS, procbased_ctls2);
vmcs_write(vcpuid, VMCS_EXIT_CTLS, exit_ctls);
vmcs_write(vcpuid, VMCS_ENTRY_CTLS, entry_ctls);
/* exception bitmap */
if (vcpu_trace_exceptions())
exc_bitmap = 0xffffffff;
else
exc_bitmap = 1 << IDT_MC;
vmcs_write(vcpuid, VMCS_EXCEPTION_BITMAP, exc_bitmap);
vmx->cap[vcpuid].set = 0;
vmx->cap[vcpuid].proc_ctls = procbased_ctls;
vmx->cap[vcpuid].proc_ctls2 = procbased_ctls2;
vmx->state[vcpuid].nextrip = ~(uint64_t) 0;
/*
* Set up the CR0/4 shadows, and init the read shadow
* to the power-on register value from the Intel Sys Arch.
* CR0 - 0x60000010
* CR4 - 0
*/
error = vmx_setup_cr0_shadow(vcpuid, 0x60000010);
if (error != 0)
xhyve_abort("vmx_setup_cr0_shadow %d\n", error);
error = vmx_setup_cr4_shadow(vcpuid, 0);
if (error != 0)
xhyve_abort("vmx_setup_cr4_shadow %d\n", error);
return (0);
}
static int
vmx_handle_cpuid(struct vm *vm, int vcpuid)
{
uint32_t eax, ebx, ecx, edx;
int error;
eax = (uint32_t) reg_read(vcpuid, HV_X86_RAX);
ebx = (uint32_t) reg_read(vcpuid, HV_X86_RBX);
ecx = (uint32_t) reg_read(vcpuid, HV_X86_RCX);
edx = (uint32_t) reg_read(vcpuid, HV_X86_RDX);
error = x86_emulate_cpuid(vm, vcpuid, &eax, &ebx, &ecx, &edx);
reg_write(vcpuid, HV_X86_RAX, eax);
reg_write(vcpuid, HV_X86_RBX, ebx);
reg_write(vcpuid, HV_X86_RCX, ecx);
reg_write(vcpuid, HV_X86_RDX, edx);
return (error);
}
static __inline void
vmx_run_trace(struct vmx *vmx, int vcpu)
{
#ifdef XHYVE_CONFIG_TRACE
VCPU_CTR1(vmx->vm, vcpu, "Resume execution at %#llx", vmcs_guest_rip(vcpu));
#else
(void) vmx;
(void) vcpu;
#endif
}
static __inline void
vmx_exit_trace(struct vmx *vmx, int vcpu, uint64_t rip, uint32_t exit_reason,
int handled)
{
#ifdef XHYVE_CONFIG_TRACE
VCPU_CTR3(vmx->vm, vcpu, "%s %s vmexit at 0x%0llx",
handled ? "handled" : "unhandled",
exit_reason_to_str((int) exit_reason), rip);
#else
(void) vmx;
(void) vcpu;
(void) rip;
(void) exit_reason;
(void) handled;
#endif
}
/*
* We depend on 'procbased_ctls' to have the Interrupt Window Exiting bit set.
*/
CTASSERT((PROCBASED_CTLS_ONE_SETTING & PROCBASED_INT_WINDOW_EXITING) != 0);
static void __inline
vmx_set_int_window_exiting(struct vmx *vmx, int vcpu)
{
if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) == 0) {
vmx->cap[vcpu].proc_ctls |= PROCBASED_INT_WINDOW_EXITING;
vmcs_write(vcpu, VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
VCPU_CTR0(vmx->vm, vcpu, "Enabling interrupt window exiting");
}
}
static void __inline
vmx_clear_int_window_exiting(struct vmx *vmx, int vcpu)
{
KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0,
("intr_window_exiting not set: %#x", vmx->cap[vcpu].proc_ctls));
vmx->cap[vcpu].proc_ctls &= ~PROCBASED_INT_WINDOW_EXITING;
vmcs_write(vcpu, VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
VCPU_CTR0(vmx->vm, vcpu, "Disabling interrupt window exiting");
}
static void __inline
vmx_set_nmi_window_exiting(struct vmx *vmx, int vcpu)
{
if ((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) == 0) {
vmx->cap[vcpu].proc_ctls |= PROCBASED_NMI_WINDOW_EXITING;
vmcs_write(vcpu, VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
VCPU_CTR0(vmx->vm, vcpu, "Enabling NMI window exiting");
}
}
static void __inline
vmx_clear_nmi_window_exiting(struct vmx *vmx, int vcpu)
{
KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) != 0,
("nmi_window_exiting not set %#x", vmx->cap[vcpu].proc_ctls));
vmx->cap[vcpu].proc_ctls &= ~PROCBASED_NMI_WINDOW_EXITING;
vmcs_write(vcpu, VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
VCPU_CTR0(vmx->vm, vcpu, "Disabling NMI window exiting");
}
static void
vmx_inject_nmi(struct vmx *vmx, int vcpu)
{
uint32_t gi, info;
gi = (uint32_t) vmcs_read(vcpu, VMCS_GUEST_INTERRUPTIBILITY);
KASSERT((gi & NMI_BLOCKING) == 0, ("vmx_inject_nmi: invalid guest "
"interruptibility-state %#x", gi));
info = (uint32_t) vmcs_read(vcpu, VMCS_ENTRY_INTR_INFO);
KASSERT((info & VMCS_INTR_VALID) == 0, ("vmx_inject_nmi: invalid "
"VM-entry interruption information %#x", info));
/*
* Inject the virtual NMI. The vector must be the NMI IDT entry
* or the VMCS entry check will fail.
*/
info = IDT_NMI | VMCS_INTR_T_NMI | VMCS_INTR_VALID;
vmcs_write(vcpu, VMCS_ENTRY_INTR_INFO, info);
VCPU_CTR0(vmx->vm, vcpu, "Injecting vNMI");
/* Clear the request */
vm_nmi_clear(vmx->vm, vcpu);
}
static void
vmx_inject_interrupts(struct vmx *vmx, int vcpu, struct vlapic *vlapic,
uint64_t guestrip)
{
int vector, need_nmi_exiting, extint_pending;
uint64_t rflags, entryinfo;
uint32_t gi, info;
if (vmx->state[vcpu].nextrip != guestrip) {
gi = (uint32_t) vmcs_read(vcpu, VMCS_GUEST_INTERRUPTIBILITY);
if (gi & HWINTR_BLOCKING) {
VCPU_CTR2(vmx->vm, vcpu, "Guest interrupt blocking "
"cleared due to rip change: %#llx/%#llx",
vmx->state[vcpu].nextrip, guestrip);
gi &= ~HWINTR_BLOCKING;
vmcs_write(vcpu, VMCS_GUEST_INTERRUPTIBILITY, gi);
}
}
if (vm_entry_intinfo(vmx->vm, vcpu, &entryinfo)) {
KASSERT((entryinfo & VMCS_INTR_VALID) != 0, ("%s: entry "
"intinfo is not valid: %#llx", __func__, entryinfo));
info = (uint32_t) vmcs_read(vcpu, VMCS_ENTRY_INTR_INFO);
KASSERT((info & VMCS_INTR_VALID) == 0, ("%s: cannot inject "
"pending exception: %#llx/%#x", __func__, entryinfo, info));
info = (uint32_t) entryinfo;
vector = info & 0xff;
if (vector == IDT_BP || vector == IDT_OF) {
/*
* VT-x requires #BP and #OF to be injected as software
* exceptions.
*/
info &= ~VMCS_INTR_T_MASK;
info |= VMCS_INTR_T_SWEXCEPTION;
}
if (info & VMCS_INTR_DEL_ERRCODE)
vmcs_write(vcpu, VMCS_ENTRY_EXCEPTION_ERROR, entryinfo >> 32);
vmcs_write(vcpu, VMCS_ENTRY_INTR_INFO, info);
}
if (vm_nmi_pending(vmx->vm, vcpu)) {
/*
* If there are no conditions blocking NMI injection then
* inject it directly here otherwise enable "NMI window
* exiting" to inject it as soon as we can.
*
* We also check for STI_BLOCKING because some implementations
* don't allow NMI injection in this case. If we are running
* on a processor that doesn't have this restriction it will
* immediately exit and the NMI will be injected in the
* "NMI window exiting" handler.
*/
need_nmi_exiting = 1;
gi = (uint32_t) vmcs_read(vcpu, VMCS_GUEST_INTERRUPTIBILITY);
if ((gi & (HWINTR_BLOCKING | NMI_BLOCKING)) == 0) {
info = (uint32_t) vmcs_read(vcpu, VMCS_ENTRY_INTR_INFO);
if ((info & VMCS_INTR_VALID) == 0) {
vmx_inject_nmi(vmx, vcpu);
need_nmi_exiting = 0;
} else {
VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI "
"due to VM-entry intr info %#x", info);
}
} else {
VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI due to "
"Guest Interruptibility-state %#x", gi);
}
if (need_nmi_exiting)
vmx_set_nmi_window_exiting(vmx, vcpu);
}
extint_pending = vm_extint_pending(vmx->vm, vcpu);
/*
* If interrupt-window exiting is already in effect then don't bother
* checking for pending interrupts. This is just an optimization and
* not needed for correctness.
*/
if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0) {
VCPU_CTR0(vmx->vm, vcpu, "Skip interrupt injection due to "
"pending int_window_exiting");
return;
}
if (!extint_pending) {
/* Ask the local apic for a vector to inject */
if (!vlapic_pending_intr(vlapic, &vector))
return;
/*
* From the Intel SDM, Volume 3, Section "Maskable
* Hardware Interrupts":
* - maskable interrupt vectors [16,255] can be delivered
* through the local APIC.
*/
KASSERT(vector >= 16 && vector <= 255,
("invalid vector %d from local APIC", vector));
} else {
/* Ask the legacy pic for a vector to inject */
vatpic_pending_intr(vmx->vm, &vector);
/*
* From the Intel SDM, Volume 3, Section "Maskable
* Hardware Interrupts":
* - maskable interrupt vectors [0,255] can be delivered
* through the INTR pin.
*/
KASSERT(vector >= 0 && vector <= 255,
("invalid vector %d from INTR", vector));
}
/* Check RFLAGS.IF and the interruptibility state of the guest */
rflags = vmcs_read(vcpu, VMCS_GUEST_RFLAGS);
if ((rflags & PSL_I) == 0) {
VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
"rflags %#llx", vector, rflags);
goto cantinject;
}
gi = (uint32_t) vmcs_read(vcpu, VMCS_GUEST_INTERRUPTIBILITY);
if (gi & HWINTR_BLOCKING) {
VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
"Guest Interruptibility-state %#x", vector, gi);
goto cantinject;
}
info = (uint32_t) vmcs_read(vcpu, VMCS_ENTRY_INTR_INFO);
if (info & VMCS_INTR_VALID) {
/*
* This is expected and could happen for multiple reasons:
* - A vectoring VM-entry was aborted due to astpending
* - A VM-exit happened during event injection.
* - An exception was injected above.
* - An NMI was injected above or after "NMI window exiting"
*/
VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
"VM-entry intr info %#x", vector, info);
goto cantinject;
}
/* Inject the interrupt */
info = VMCS_INTR_T_HWINTR | VMCS_INTR_VALID;
info |= (uint32_t) vector;
vmcs_write(vcpu, VMCS_ENTRY_INTR_INFO, info);
if (!extint_pending) {
/* Update the Local APIC ISR */
vlapic_intr_accepted(vlapic, vector);
} else {
vm_extint_clear(vmx->vm, vcpu);
vatpic_intr_accepted(vmx->vm, vector);
/*
* After we accepted the current ExtINT the PIC may
* have posted another one. If that is the case, set
* the Interrupt Window Exiting execution control so
* we can inject that one too.
*
* Also, interrupt window exiting allows us to inject any
* pending APIC vector that was preempted by the ExtINT
* as soon as possible. This applies both for the software
* emulated vlapic and the hardware assisted virtual APIC.
*/
vmx_set_int_window_exiting(vmx, vcpu);
}
VCPU_CTR1(vmx->vm, vcpu, "Injecting hwintr at vector %d", vector);
return;
cantinject:
/*
* Set the Interrupt Window Exiting execution control so we can inject
* the interrupt as soon as blocking condition goes away.
*/
vmx_set_int_window_exiting(vmx, vcpu);
}
/*
* If the Virtual NMIs execution control is '1' then the logical processor
* tracks virtual-NMI blocking in the Guest Interruptibility-state field of
* the VMCS. An IRET instruction in VMX non-root operation will remove any
* virtual-NMI blocking.
*
* This unblocking occurs even if the IRET causes a fault. In this case the
* hypervisor needs to restore virtual-NMI blocking before resuming the guest.
*/
static void
vmx_restore_nmi_blocking(struct vmx *vmx, int vcpuid)
{
uint32_t gi;
VCPU_CTR0(vmx->vm, vcpuid, "Restore Virtual-NMI blocking");
gi = (uint32_t) vmcs_read(vcpuid, VMCS_GUEST_INTERRUPTIBILITY);
gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
vmcs_write(vcpuid, VMCS_GUEST_INTERRUPTIBILITY, gi);
}
static void
vmx_clear_nmi_blocking(struct vmx *vmx, int vcpuid)
{
uint32_t gi;
VCPU_CTR0(vmx->vm, vcpuid, "Clear Virtual-NMI blocking");
gi = (uint32_t) vmcs_read(vcpuid, VMCS_GUEST_INTERRUPTIBILITY);
gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;