arch/arm: add CONFIG_ARCH_TRUSTZONE_SECURE to some code

Signed-off-by: hujun5 <hujun5@xiaomi.com>
hujun260 · Aug 18, 2023 · 6524163 · 6524163
1 parent d75e767
commit 6524163
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diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c
@@ -196,13 +196,17 @@ void arm_gic_initialize(void)
 
   /* Registers with 1-bit per interrupt */
 
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
   /* per-CPU inerrupts config:
    * ID0-ID7(SGI)  for Non-secure interrupts
    * ID8-ID15(SGI)  for Secure interrupts.
    * All PPI config as secure interrupts.
    */
 
   putreg32(0x000000ff, GIC_ICDISR(0));
+#else
+  putreg32(0x00000000, GIC_ICDISR(0));      /* SGIs and PPIs secure */
+#endif
   putreg32(0xfe000000, GIC_ICDICER(0));     /* PPIs disabled */
 
   /* Registers with 8-bits per interrupt */

diff --git a/arch/arm/src/armv7-r/arm_gicv2.c b/arch/arm/src/armv7-r/arm_gicv2.c
@@ -196,13 +196,17 @@ void arm_gic_initialize(void)
 
   /* Registers with 1-bit per interrupt */
 
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
   /* per-CPU inerrupts config:
    * ID0-ID7(SGI)  for Non-secure interrupts
    * ID8-ID15(SGI)  for Secure interrupts.
    * All PPI config as secure interrupts.
    */
 
   putreg32(0x000000ff, GIC_ICDISR(0));
+#else
+  putreg32(0x00000000, GIC_ICDISR(0));      /* SGIs and PPIs secure */
+#endif
   putreg32(0xfe000000, GIC_ICDICER(0));     /* PPIs disabled */
 
   /* Registers with 8-bits per interrupt */

diff --git a/arch/arm64/src/common/arm64_gicv2.c b/arch/arm64/src/common/arm64_gicv2.c
@@ -922,13 +922,17 @@ static void arm_gic_initialize(void)
 
   /* Registers with 1-bit per interrupt */
 
+#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
   /* per-CPU inerrupts config:
    * ID0-ID7(SGI)  for Non-secure interrupts
    * ID8-ID15(SGI)  for Secure interrupts.
    * All PPI config as secure interrupts.
    */
 
   putreg32(0x000000ff, GIC_ICDISR(0));
+#else
+  putreg32(0x00000000, GIC_ICDISR(0));      /* SGIs and PPIs secure */
+#endif
   putreg32(0xfe000000, GIC_ICDICER(0));     /* PPIs disabled */
 
   /* Registers with 8-bits per interrupt */