ROHD swizzle output variable must be equal to the swizzle result width

[quekyj]

In ROHD, the width of the swizzle must be equal to the width of the output. The code below fail with error message Uncaught Error: Failed to put value on signal (f): Updated value width mismatch. The width of 10'bzzzz00111z should be 11.

Will there be support that allows 0 to be added Infront if the width of the output is larger than the swizzle?

import 'package:rohd/rohd.dart';

void slicing(Logic a, Logic b, Logic c, Logic d, Logic e, Logic f) {
  d <= b[7];
  e <= [d, c, a].swizzle();
  f <= [d, c, a].rswizzle();
}

void main() async {
  // Declare Logic
  final a = Logic(name: 'a', width: 4);
  final b = Logic(name: 'b', width: 8);
  final c = Const(7, width: 5);
  final d = Logic(name: 'd');
  final e = Logic(name: 'e', width: d.width + c.width + a.width);
  
  // PURPOSELY ADD +1 here.
  final f = Logic(name: 'f', width: d.width + c.width + a.width + 1);
  
  final rangeSwizzling = RangeSwizzling(a, b, c, d, e, f, slicing);
  await rangeSwizzling.build();
  print(rangeSwizzling.generateSynth());
  
  print('\n');
  a.put(bin('1110'));

  b.put(bin('11000100'));
  print('e: ${rangeSwizzling.e.value.toString(includeWidth: false)}');
  print('f: ${rangeSwizzling.f.value.toString(includeWidth: false)}');
}


class RangeSwizzling extends Module {
  Logic get d => output('d');
  Logic get e => output('e');
  Logic get f => output('f');
  RangeSwizzling(Logic a, Logic b, Logic c, Logic d, Logic e, Logic f,
      void Function(Logic a, Logic b, Logic c, Logic d, Logic e, Logic f) slice)
      : super(name: 'range_swizzling') {
    a = addInput(a.name, a, width: a.width);
    b = addInput(b.name, b, width: b.width);
    c = addInput(c.name, c, width: c.width);
    d = addOutput(d.name, width: d.width);
    e = addOutput(e.name, width: e.width);
    f = addOutput(f.name, width: f.width);
    slice(a, b, c, d, e, f);
  }
}

[chykon]

There is a method zeroExtend. Or have I misunderstood something?

f <= [d, c, a].rswizzle().zeroExtend(f.width);

[quekyj]

I see. This is exactly what I want. Just a quick question, should swizzle() always zeroExtend based on its own logic width?

[chykon]

My opinion is to use zeroExtend/signExtend only when explicitly required. ROHD will not allow a circuit with conflicting widths to work.

[mkorbel1]

This code actually should fail at connection time rather than put time. I tried running it and got this output:

Exception: Bus widths must match. Cannot connect Logic(11): f to Logic(10): _swizzled which have different widths.

But the root-cause is the same, and the other answer from @chykon still applies.

[chykon]

Hmm, DartPad shows the same error as @quekyj

[mkorbel1]

That's weird! I wonder why

[mkorbel1]

Ah, I was running on a side-branch of ROHD which had some different behavior. The old error should be reinstated since I think it's much more helpful!

[mkorbel1]

I filed a bug here: #311