README.md

IIR Filter Synthesizable Unit Specifications

Document	Metadata
Version	v0.0.1
Prepared by	Jose R Garcia
Date	xx/xx/20XX

Overview

Verilog code for a IIR filter. As new values are fed through the input the filtered result goes out the streaming output synchronous to the input clock.

Table of Contents

• IIR Filter Synthesizable Unit Specifications

  • Overview

  • Table of Contents

  • 1 Syntax and Abbreviations

  • 2 Design

  • 3 Clocks and Resets

  • 4 Interfaces

    • 4.1 Streaming Interface
    • 4.2 Asynchronous Memory Write Interface

  • 5 Generic Parameters

  • 6 Memory Map

    • 6.1 Coefficients Memory Address Space

      • 6.1.1 Coefficient[N] Register

  • 7 Directory Structure

  • 8 Simulation

  • 9 Synthesis

  • 10 Build

1 Syntax and Abbreviations

Characters	Definition
0b0	Binary number syntax
0x0	Hexadecimal number syntax
IIR	Infinite Impulse Response
FPGA	Field Programmable Gate Array

2 Design

The IIR_Filter has N number of coefficients of n length configured at compile time. This coefficients are use to create the filter's tabs. Each tab consist of a MACC. As data moves through the pipeline it fed to each MACC. Coefficients are populated through the Asynchronous Memory Write Interface. The data input is fed through the Streaming Input Interface. The N^th^ MACC output is connected directly to the Streaming Output Interface.

Figure 2-1 : Transposed Direct-Form II

3 Clocks and Resets

Signals	Initial State	Direction	Definition
i_clk	N/A	In	Input clock. Streaming interface fall within the domain of this clock
i_reset_sync	0b1	In	Top level synchronous reset. Use to reset the whole unit.

4 Interfaces

The IIR_Filter has a Streaming input/output interface and a Asynchronous Memory Write Interface. The Streaming interface is use for create the data path. The memory interface makes the coefficients accessible to be reconfigure on real time.

4.1 Streaming Interface

Signals	Initial State	Dimension	Direction	Definition
o_ready_in	0b0	1-bit	Out	Ready signal for input data.
i_valid_in	N/A	1-bit	In	Valid signal for input data.
i_data_in	N/A	[P_DATA_MSB:0]	In	Input for streaming data.
i_ready_out	N/A	1-bit	In	Ready signal for output data.
o_valid_out	0b0	1-bit	Out	Valid signal for output data.
o_data_out	0x0	[P_DATA_MSB:0]	Out	Output for streaming data.

4.2 Asynchronous Memory Write Interface

Signals	Initial State	Dimension	Direction	Definition
i_slave_wselect	N/A	1-bit	In	Input Select.
i_slave_write	N/A	1-bit	In	Write enable. Indicates the current write data is valid and it is to be written into memory. Also indicates write acknowledge(o_slave_wack) has not been detected.
o_slave_wack	0b0	1-bit	Out	Write acknowledge. Indicate a write was performed. Stays high until write enable(i_slave_write) is detected to be low.
i_slave_write_data	N/A	[P_COEFFICIENTS_MSB:0]	In	Write Data. Data input to this addressable memory space.
i_slave_write_addr	N/A	[P_WRITE_ADDRESS_MSB:0]	In	Write Address. Address input to this addressable memory space.

5 Generic Parameters

Parameters	Default	Description
P_COEFFICIENTS_MSB	0	Most significant bit of the FIR filter coefficients.
P_NUM_COEFFICIENTS	1	Number of coefficients used to build the filter.
P_DATA_MSB	0	Most significant bit of the streaming data.
P_WRITE_ADDRESS_MSB	0	Most significant bit of the memory address.

6 Memory Map

6.1 Coefficients Memory Address Space

Address Range	Description
0x0 to P_NUM_COEFFICIENTS-1	Coefficients address space.

6.1.1 Coefficient[N] Register

Bits	Access	Reset	Description
P_COEFFICIENTS_MSB:0	W	0b0	Signed coefficient value used in one tap of the filter.

7 Directory Structure

• build contains synthesis scripts and outputs, build scripts, build constraints, build outputs(reports) and flashable image
• octave contains math scripts used to generate artifacts that complement the synthesizable unit and/or its test bench
• sim contains simulation scripts and results
• source contains source code file (*.v)
• testbench contains test bench source files

8 Simulation

Simulation scripts assumes Icarus Verilog (iverilog) as the simulation tool. From the /sim directory run make. Options available are

Command	Description
make all	cleans, compiles and runs the test bench, then it loads the waveform.
make test	compiles the test bench and UUT
make run	runs the simulation
make wave	loads the waveform in gtkwave
make clean	cleans all the compile and simulation products

9 Build

Synthesis scripts assume Yosys as the tool for synthesizing code and Lattice ICE HX-8K as the target FPGA device.

Build scripts are written for the Icestorm tool-chain. The target device is the hx8kboard sold by Lattice.

Command	Description
make all	cleans, synthesizes and runs place and route and generates timing report.
make syn	Runs Yosys synthesis script
make pnr	Runs place and route. (NextPnR)
make bin	create bin file
make rpt	Output timing report
make clean	cleans all the compile and simulation products

10 Generating Coefficients

To generate the coefficients use the Octave script. The first coefficient of the "A" side must always be "1".