README.md

PipeUtils

Basic component for pipeline design

Pipeline control

Pipeline

Source code of pipeline control logic is at pipeline.vh

Include the pipeline task.

`include "pipeline.vh"

Assign the state machine for ready/valid control.

always @(posedge clk or negedge resetb)
begin
    if (!resetb)
        state		<= 1'b0;
    else
        state		<= state_nxt;
end

Use the pipeline task to perform ready/valid control.

always @*
begin
    pipeline (
        .state 		(state),
        .state_nxt 	(state_nxt),
        
        .ready_in	(ready_in),
        .valid_in	(valid_in),
        
        .ready_out	(ready_out),
        .valid_out	(valid_out),
        .stall		(stall)
    );
end

Data path.

always @(posedge clk)
begin
    if (!stall)
        dout		<= din
end

Verilog

assign valid_in     = valid_out || !ready_out;
assign stall        = !(ready_in && valid_in);

always @(posedge clk or negedge resetn)
begin
    if (!resetn)
        ready_out   <= 1'b0;
    else
        ready_out   <= ready_in && !valid_in;
end

Timing issue on valid signal

bypass

Include the pipeline task.

`include "pipeline.vh"

Assigned the ready/valid state machine.

always @(posedge clk or negedge resetb)
begin
    if (!resetb)
        state		<= 1'b0;
    else
        state		<= state_nxt;
end

Use the bypass to perform ready/valid handshaking.

always @*
begin
    bypass (
        .state		(state),
        .state_nxt	(state_nxt),
        
        .ready_in	(ready_in),
        .valid_in	(valid_in),
        
        .ready_out	(ready_out),
        .valid_out	(valid_out),
        .stall		(stall),
        .selection	(selection)
    );
end

Data path

always @(posedge clk)
begin
    if (!stall)
        dout_r		<= din;
end

assign dout = selection ? din : dout_r;

Verilog expression

assign valid_in     = !select;
assign stall        = !(ready_in && valid_in);
assign ready_out    = select || ready_in;

always @(posedge clk or negedge resetn)
begin
    if (!resetn)
        select      <= 1'b0;
    else
        select      <= !(valid_out || !(select || ready_in));
end

Add bypass between two pipelined controls

Extra timing path on ready_out and data path

Pipeline multiplexer and demultiplex

pipeMux41:

ready_out = ready_in1 & ready_in2 & ready_in3 & ready_in4;
valid_in1 = valid_out & ready_in2 & ready_in3 & ready_in4;
valid_in2 = valid_out & ready_in1 & ready_in3 & ready_in4;
valid_in3 = valid_out & ready_in1 & ready_in2 & ready_in4;
valid_in4 = valid_out & ready_in1 & ready_in2 & ready_in3;

pipeDeMux14:

valid_in   = valid_out1 & valid_out2 & valid_out3 & valid_out4;
ready_out1 = ready_in & valid_out2 & valid_out3 & valid_out4;
ready_out2 = ready_in & valid_out1 & valid_out3 & valid_out4;
ready_out3 = ready_in & valid_out1 & valid_out2 & valid_out4;
ready_out4 = ready_in & valid_out1 & valid_out2 & valid_out3;

Examples

Multiplier-Adder

Using pipeline

Using bypass

Data read

This is an example to show the data request.

Address path

1. address generator
2. address arbitor
3. pipeline demutiplexor
4. address request

Data path

1. data respond
2. pipeline multiplexor
3. data dispatcher

Asynchronous FIFO

This is an example to make the registered input and output of asynchronous FIFO using pipeline control logic.

License

LGPL license