You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Thank you for your comment.
I'm using ImAxis<24> which have only 5 signals (data, valid, ready, user, and last) instead of ap_axiu<24,1,1,1> because of due to specification of AXI VDMA.
I checked working my code using Vivado HLS 2018.2 now, however, I think it is no problem as far as I saw the synthesis log.
I want to modify your code so that it could take hls::stream<ap_axiu<24,1,1,1>>& instead of hls::stream<ImAxis<24>>&
i.e from
void canny_edge_detection(stream<ImAxis<24>>& axis_in, stream<ImAxis<24> >& axis_out,
uint8_t& hist_hthr, uint8_t& hist_lthr)
to
void canny_edge_detection(stream<ap_axiu<24,1,1,1>>& axis_in, stream<ap_axiu<24,1,1,1>>& axis_out,
uint8_t& hist_hthr, uint8_t& hist_lthr)
But, vivado_hls keeps complaining there is left over data, can you advise me how to do it?
Many thanks
The text was updated successfully, but these errors were encountered: