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YoDawg_preroute.twx
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YoDawg_preroute.twx
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml YoDawg_preroute.twx YoDawg_map.ncd -o YoDawg_preroute.twr
YoDawg.pcf -ucf YoDawg.ucf
</twCmdLine><twDesign>YoDawg_map.ncd</twDesign><twDesignPath>YoDawg_map.ncd</twDesignPath><twPCF>YoDawg.pcf</twPCF><twPcfPath>YoDawg.pcf</twPcfPath><twDevInfo arch="artix7" pkg="csg324"><twDevName>xc7a100t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.10 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="6" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="NET "Clk_100M" PERIOD = 10 ns HIGH 5 ns;" ScopeName="">NET "Clk_100M_BUFGP/IBUFG" PERIOD = 10 ns HIGH 5 ns;</twConstName><twItemCnt>265608266446177861632</twItemCnt><twErrCntSetup>5025</twErrCntSetup><twErrCntEndPt>5027</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">2</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>18262</twEndPtCnt><twPathErrCnt>265608266263586635776</twPathErrCnt><twMinPer>31.106</twMinPer></twConstHead><twPathRptBanner iPaths="10555589314555054080" iCriticalPaths="10555589314554720256" sType="EndPoint">Paths for end point MandelbrotGen0/Z_im_254 (SLICE_X48Y92.CIN), 10555589314555054080 paths
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twEdge="twRising">0.341</twDelInfo><twComp>MandelbrotGen0/Z_re<1></twComp><twBEL>MandelbrotGen0/Z_re_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y47.B2</twSite><twDelType>net</twDelType><twFanCnt>263</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.653</twDelInfo><twComp>MandelbrotGen0/Z_re<1></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y47.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.509</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd87_cy<6></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd87_lut<4></twBEL><twBEL>MandelbrotGen0/Mmult_n0085_Madd87_cy<6></twBEL></twPathDel><twPathDel><twSite>SLICE_X7Y48.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd87_cy<6></twComp></twPathDel><twPathDel><twSite>SLICE_X7Y48.BMUX</twSite><twDelType>Tcinb</twDelType><twDelInfo twEdge="twRising">0.358</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd87_cy<10></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd87_cy<10></twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y51.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">1.766</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd_8787</twComp></twPathDel><twPathDel><twSite>SLICE_X82Y51.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.492</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd170_cy<11></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd170_lut<8></twBEL><twBEL>MandelbrotGen0/Mmult_n0085_Madd170_cy<11></twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y52.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd170_cy<11></twComp></twPathDel><twPathDel><twSite>SLICE_X82Y52.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.371</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd170_cy<15></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd170_cy<15></twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.607</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd_94170</twComp></twPathDel><twPathDel><twSite>SLICE_X1Y5.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.509</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd213_cy<21></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd213_lut<19></twBEL><twBEL>MandelbrotGen0/Mmult_n0085_Madd213_cy<21></twBEL></twPathDel><twPathDel><twSite>SLICE_X1Y6.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd213_cy<21></twComp></twPathDel><twPathDel><twSite>SLICE_X1Y6.BMUX</twSite><twDelType>Tcinb</twDelType><twDelInfo twEdge="twRising">0.358</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd213_cy<25></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd213_cy<25></twBEL></twPathDel><twPathDel><twSite>SLICE_X84Y53.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.588</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd_98213</twComp></twPathDel><twPathDel><twSite>SLICE_X84Y53.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.499</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd234_cy<25></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd234_lut<23></twBEL><twBEL>MandelbrotGen0/Mmult_n0085_Madd234_cy<25></twBEL></twPathDel><twPathDel><twSite>SLICE_X84Y54.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd234_cy<25></twComp></twPathDel><twPathDel><twSite>SLICE_X84Y54.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd234_cy<29></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd234_cy<29></twBEL></twPathDel><twPathDel><twSite>SLICE_X84Y55.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd234_cy<29></twComp></twPathDel><twPathDel><twSite>SLICE_X84Y55.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd234_cy<33></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd234_cy<33></twBEL></twPathDel><twPathDel><twSite>SLICE_X84Y56.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd234_cy<33></twComp></twPathDel><twPathDel><twSite>SLICE_X84Y56.BMUX</twSite><twDelType>Tcinb</twDelType><twDelInfo twEdge="twRising">0.342</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd234_cy<37></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd234_cy<37></twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y19.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.547</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd_110270</twComp></twPathDel><twPathDel><twSite>SLICE_X5Y19.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.509</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd245_cy<53></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd245_lut<51></twBEL><twBEL>MandelbrotGen0/Mmult_n0085_Madd245_cy<53></twBEL></twPathDel><twPathDel><twSite>SLICE_X5Y20.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd245_cy<53></twComp></twPathDel><twPathDel><twSite>SLICE_X5Y20.BMUX</twSite><twDelType>Tcinb</twDelType><twDelInfo twEdge="twRising">0.358</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd245_cy<57></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd245_cy<57></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y88.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">2.713</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd_114250</twComp></twPathDel><twPathDel><twSite>SLICE_X74Y88.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.499</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<57></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_lut<55></twBEL><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<57></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y89.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<57></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y89.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<61></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<61></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y90.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<61></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y90.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<65></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<65></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y91.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<65></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y91.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<69></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<69></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y92.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<69></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y92.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<73></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<73></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y93.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<73></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y93.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<77></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<77></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y94.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<77></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y94.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<81></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<81></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y95.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<81></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y95.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<85></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<85></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y96.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<85></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y96.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<89></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<89></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y97.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<89></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y97.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo 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twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<101></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<101></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y100.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<101></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y100.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<105></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<105></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y101.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<105></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y101.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<109></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<109></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y102.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<109></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y102.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.092</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<113></twComp><twBEL>MandelbrotGen0/Mmult_n0085_Madd250_cy<113></twBEL></twPathDel><twPathDel><twSite>SLICE_X74Y103.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Mmult_n0085_Madd250_cy<113></twComp></twPathDel><twPathDel><twSite>SLICE_X74Y103.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo 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twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<232></twComp></twPathDel><twPathDel><twSite>SLICE_X48Y87.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.089</twDelInfo><twComp>MandelbrotGen0/Z_im<236></twComp><twBEL>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<236></twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y88.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<236></twComp></twPathDel><twPathDel><twSite>SLICE_X48Y88.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.089</twDelInfo><twComp>MandelbrotGen0/Z_im<240></twComp><twBEL>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<240></twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y89.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<240></twComp></twPathDel><twPathDel><twSite>SLICE_X48Y89.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.089</twDelInfo><twComp>MandelbrotGen0/Z_im<244></twComp><twBEL>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<244></twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y90.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<244></twComp></twPathDel><twPathDel><twSite>SLICE_X48Y90.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.089</twDelInfo><twComp>MandelbrotGen0/Z_im<248></twComp><twBEL>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<248></twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y91.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<248></twComp></twPathDel><twPathDel><twSite>SLICE_X48Y91.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.089</twDelInfo><twComp>MandelbrotGen0/Z_im<252></twComp><twBEL>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<252></twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y92.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising" twAcc="twEst">0.000</twDelInfo><twComp>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_cy<252></twComp></twPathDel><twPathDel><twSite>SLICE_X48Y92.CLK</twSite><twDelType>Tcinck</twDelType><twDelInfo twEdge="twRising">0.103</twDelInfo><twComp>MandelbrotGen0/Z_im<255></twComp><twBEL>MandelbrotGen0/Madd_Z_re[254]_C_im[11]_add_13_OUT_xor<255></twBEL><twBEL>MandelbrotGen0/Z_im_253</twBEL></twPathDel><twLogDel>10.821</twLogDel><twRouteDel>20.179</twRouteDel><twTotDel>31.000</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">Clk_100M_BUFGP</twDestClk><twPctLog>34.9</twPctLog><twPctRoute>65.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: NET "Clk_100M_BUFGP/IBUFG" PERIOD = 10 ns HIGH 5 ns;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram (RAMB36_X3Y18.DIADI3), 1 path
</twPathRptBanner><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-0.145</twSlack><twSrc BELType="FF">MandelbrotGen0/dinA_6</twSrc><twDest BELType="RAM">best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twDest><twTotPathDel>-0.145</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="23" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>MandelbrotGen0/dinA_6</twSrc><twDest BELType='RAM'>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X81Y93.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">Clk_100M_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X81Y93.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.274</twDelInfo><twComp>dinA<4></twComp><twBEL>MandelbrotGen0/dinA_6</twBEL></twPathDel><twPathDel><twSite>RAMB36_X3Y18.DIADI3</twSite><twDelType>net</twDelType><twFanCnt>75</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.174</twDelInfo><twComp>dinA<6></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB36_X3Y18.CLKARDCLKU</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.593</twDelInfo><twComp>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twComp><twBEL>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twLogDel>-0.319</twLogDel><twRouteDel>0.174</twRouteDel><twTotDel>-0.145</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">Clk_100M_BUFGP</twDestClk><twPctLog>220.0</twPctLog><twPctRoute>-120.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram (RAMB36_X3Y18.DIADI5), 1 path
</twPathRptBanner><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>-0.010</twSlack><twSrc BELType="FF">MandelbrotGen0/dinA_8</twSrc><twDest BELType="RAM">best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twDest><twTotPathDel>-0.010</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="23" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>MandelbrotGen0/dinA_8</twSrc><twDest BELType='RAM'>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X79Y93.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">Clk_100M_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X79Y93.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.274</twDelInfo><twComp>dinA<8></twComp><twBEL>MandelbrotGen0/dinA_8</twBEL></twPathDel><twPathDel><twSite>RAMB36_X3Y18.DIADI5</twSite><twDelType>net</twDelType><twFanCnt>75</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.309</twDelInfo><twComp>dinA<8></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB36_X3Y18.CLKARDCLKU</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.593</twDelInfo><twComp>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twComp><twBEL>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twLogDel>-0.319</twLogDel><twRouteDel>0.309</twRouteDel><twTotDel>-0.010</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">Clk_100M_BUFGP</twDestClk><twPctLog>3190.0</twPctLog><twPctRoute>-3090.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram (RAMB36_X3Y18.DIADI7), 1 path
</twPathRptBanner><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.014</twSlack><twSrc BELType="FF">MandelbrotGen0/dinA_10</twSrc><twDest BELType="RAM">best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twDest><twTotPathDel>0.014</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="23" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>MandelbrotGen0/dinA_10</twSrc><twDest BELType='RAM'>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X79Y93.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">Clk_100M_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X79Y93.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.274</twDelInfo><twComp>dinA<8></twComp><twBEL>MandelbrotGen0/dinA_10</twBEL></twPathDel><twPathDel><twSite>RAMB36_X3Y18.DIADI7</twSite><twDelType>net</twDelType><twFanCnt>75</twFanCnt><twDelInfo twEdge="twFalling" twAcc="twEst">0.333</twDelInfo><twComp>dinA<10></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>RAMB36_X3Y18.CLKARDCLKU</twSite><twDelType>Trckd_DIA</twDelType><twDelInfo twEdge="twFalling">-0.593</twDelInfo><twComp>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twComp><twBEL>best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram</twBEL></twPathDel><twLogDel>-0.319</twLogDel><twRouteDel>0.333</twRouteDel><twTotDel>0.014</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">Clk_100M_BUFGP</twDestClk><twPctLog>-2278.6</twPctLog><twPctRoute>2378.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="31"><twPinLimitBanner>Component Switching Limit Checks: NET "Clk_100M_BUFGP/IBUFG" PERIOD = 10 ns HIGH 5 ns;</twPinLimitBanner><twPinLimit anchorID="32" type="MINPERIOD" name="Trper_CLKA" slack="7.859" period="10.000" constraintValue="10.000" deviceLimit="2.141" freqLimit="467.071" physResource="best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKARDCLKL" logResource="best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKARDCLKL" locationPin="RAMB36_X1Y27.CLKARDCLKL" clockNet="Clk_100M_BUFGP"/><twPinLimit anchorID="33" type="MINPERIOD" name="Trper_CLK_WF_NC(FMAX_CAS_WF_NC)" slack="7.859" period="10.000" constraintValue="10.000" deviceLimit="2.141" freqLimit="467.071" physResource="best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKARDCLKU" logResource="best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKARDCLKU" locationPin="RAMB36_X1Y27.CLKARDCLKU" clockNet="Clk_100M_BUFGP"/><twPinLimit anchorID="34" type="MINPERIOD" name="Trper_CLKB" slack="7.859" period="10.000" constraintValue="10.000" deviceLimit="2.141" freqLimit="467.071" physResource="best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKBWRCLKL" logResource="best_ram_eva0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKBWRCLKL" locationPin="RAMB36_X1Y27.CLKBWRCLKL" clockNet="Clk_100M_BUFGP"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="35">1</twUnmetConstCnt><twDataSheet anchorID="36" twNameLen="15"><twClk2SUList anchorID="37" twDestWidth="8"><twDest>Clk_100M</twDest><twClk2SU><twSrc>Clk_100M</twSrc><twRiseRise>31.106</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="38"><twErrCnt>5027</twErrCnt><twScore>45090508</twScore><twSetupScore>45090353</twSetupScore><twHoldScore>155</twHoldScore><twConstCov><twPathCnt>265608266446177894400</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>227424</twConnCnt></twConstCov><twStats anchorID="39"><twMinPer>31.106</twMinPer><twFootnote number="1" /><twMaxFreq>32.148</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Wed May 11 15:46:37 2016 </twTimestamp></twFoot><twClientInfo anchorID="40"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 1959 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>