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The RISC-V Instruction Set Manual
Volume II: Privileged Architecture
Document Version 20190608-Priv-MSU-Ratified
mbadaddr : -> mtval?
The mbadaddr register has been subsumed by a more general mtval register that can now
capture bad instruction bits on an illegal instruction fault to speed instruction emulation.
(Preface to Version 1.10 - Page 5)
sptbr : -> satp
The supervisor virtual memory configuration has been moved from the mstatus register to
the sptbr register. Accordingly, the sptbr register has been renamed to satp (Supervisor
Address Translation and Protection) to reflect its broadened role.
(Preface to Version 1.10 - Page 5)
sbadaddr : stval?
thanks for reading and for the great work done with the simulator!
The text was updated successfully, but these errors were encountered:
racarla
changed the title
mbadaddr : -> mtval?
mbadaddr : -> mtval? and some registes unknown
Jul 3, 2019
racarla
changed the title
mbadaddr : -> mtval? and some registes unknown
Registers names
Jul 3, 2019
racarla
changed the title
Registers names
Changes on registers names
Jul 3, 2019
The RISC-V Instruction Set Manual
Volume II: Privileged Architecture
Document Version 20190608-Priv-MSU-Ratified
mbadaddr : -> mtval?
The mbadaddr register has been subsumed by a more general mtval register that can now
capture bad instruction bits on an illegal instruction fault to speed instruction emulation.
(Preface to Version 1.10 - Page 5)
mbase : ?
mibase : ?
mdbase : ?
mbound : ?
mibound : ?
mdbound : ?
sptbr : -> satp
The supervisor virtual memory configuration has been moved from the mstatus register to
the sptbr register. Accordingly, the sptbr register has been renamed to satp (Supervisor
Address Translation and Protection) to reflect its broadened role.
(Preface to Version 1.10 - Page 5)
sbadaddr : stval?
thanks for reading and for the great work done with the simulator!
The text was updated successfully, but these errors were encountered: