diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp
index 09467bc80e8a..fbbe92bd5202 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp
@@ -222,30 +222,19 @@ LogicalResult verifyDoubleTilingExpertPassPipelineConfig(
       }
     }
 
-    SmallVector<int64_t> thirdLevelTileSizes;
-    std::tie(thirdLevelTileSizes, std::ignore) =
-        tilingConfig.getVectorReductionSizes();
-    for (auto [index, tileSize] : llvm::enumerate(thirdLevelTileSizes)) {
-      if (tileSize != 0 && pLoopsSet.contains(index)) {
-        return op->emitOpError(
-                   "expected only reduction dims to be set in the third tiling "
-                   "level, got ")
-               << index << "-th tile size set";
+    if (!clEnableQuantizedMatmulReassociation) {
+      SmallVector<int64_t> thirdLevelTileSizes;
+      std::tie(thirdLevelTileSizes, std::ignore) =
+          tilingConfig.getVectorReductionSizes();
+      for (auto [index, tileSize] : llvm::enumerate(thirdLevelTileSizes)) {
+        if (tileSize != 0 && pLoopsSet.contains(index)) {
+          return op->emitOpError("expected only reduction dims to be set in "
+                                 "the third tiling "
+                                 "level, got ")
+                 << index << "-th tile size set";
+        }
       }
     }
-    // if (!clEnableQuantizedMatmulReassociation) {
-    //   SmallVector<int64_t> thirdLevelTileSizes;
-    //   std::tie(thirdLevelTileSizes, std::ignore) =
-    //       tilingConfig.getVectorReductionSizes();
-    //   for (auto [index, tileSize] : llvm::enumerate(thirdLevelTileSizes)) {
-    //     if (tileSize != 0 && pLoopsSet.contains(index)) {
-    //       return op->emitOpError("expected only reduction dims to be set in "
-    //                              "the third tiling "
-    //                              "level, got ")
-    //              << index << "-th tile size set";
-    //     }
-    //   }
-    // }
   }
 
   // Verify interchange