Error using f4pga flow for Xilinx

[carlosedp]

I'm trying to use the f4pga flow for a Xilinx board but I'm getting the following error:

Traceback (most recent call last):
  File "/Users/cdepaula/python_bins/bin/fusesoc", line 8, in <module>
    sys.exit(main())
             ^^^^^^
  File "/Users/cdepaula/python_bins/lib/python3.12/site-packages/fusesoc/main.py", line 672, in main
    fusesoc(args)
  File "/Users/cdepaula/python_bins/lib/python3.12/site-packages/fusesoc/main.py", line 662, in fusesoc
    args.func(fs, args)
  File "/Users/cdepaula/python_bins/lib/python3.12/site-packages/fusesoc/main.py", line 316, in run
    edam_file, backend = fs.get_backend(core, flags, args.backendargs)
                         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/cdepaula/python_bins/lib/python3.12/site-packages/fusesoc/fusesoc.py", line 155, in get_backend
    edalizer.parse_args(backend_class, backendargs, edam)
  File "/Users/cdepaula/python_bins/lib/python3.12/site-packages/fusesoc/edalizer.py", line 492, in parse_args
    parser = self._build_parser(backend_class, edam)
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/cdepaula/python_bins/lib/python3.12/site-packages/fusesoc/edalizer.py", line 324, in _build_parser
    paramtypes = backend_class.argtypes
                 ^^^^^^^^^^^^^^^^^^^^^^
AttributeError: type object 'F4pga' has no attribute 'argtypes'

The config is like:

  artya7-35t-f4pga:
    default_tool: f4pga
    description: Digilent ArtyA7-35T Board using F4PGA Toolchain
    filesets: [base, artya7-35t, proginfo, progload]
    generate: [artya7-35t]
    hooks:
      post_run: [artya7-35t]
    tools:
      f4pga:
        device: artix7
        part: xc7a35tcpg236-1
        chip: xc7a50t_test
    toplevel: Toplevel
    parameters:
      - ENABLE_INITIAL_MEM_
...
parameters:
  ENABLE_INITIAL_MEM_:
    description: Used by firtool so the memories are initialized with readmemh. https://github.com/llvm/circt/pull/5237
    paramtype: vlogdefine
    datatype: bool
    default: true