From 485662f0c9a315e084c5e18db49b4ea4a7503dfe Mon Sep 17 00:00:00 2001 From: Emeric Poulin <46192993+E-Poulin@users.noreply.github.com> Date: Wed, 26 May 2021 16:59:42 +0200 Subject: [PATCH] Index width adaptation to cache size and assoc (#643) Signed-off-by: Emeric Poulin --- include/ariane_pkg.sv | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv index f98a6d3144..a324e6113b 100644 --- a/include/ariane_pkg.sv +++ b/include/ariane_pkg.sv @@ -417,17 +417,18 @@ package ariane_pkg; localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(`CONFIG_L1D_SIZE / DCACHE_SET_ASSOC); localparam int unsigned DCACHE_TAG_WIDTH = riscv::PLEN - DCACHE_INDEX_WIDTH; `else - // align to openpiton for the time being (this should be more configurable in the future) - // I$ - localparam int unsigned ICACHE_INDEX_WIDTH = 12; // in bit + // I$ + localparam int unsigned CONFIG_L1I_SIZE = 16*1024; + localparam int unsigned ICACHE_SET_ASSOC = 4; + localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); // in bit, contains also offset width localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN-ICACHE_INDEX_WIDTH; // in bit localparam int unsigned ICACHE_LINE_WIDTH = 128; // in bit - localparam int unsigned ICACHE_SET_ASSOC = 4; // D$ - localparam int unsigned DCACHE_INDEX_WIDTH = 12; // in bit + localparam int unsigned CONFIG_L1D_SIZE = 32*1024; + localparam int unsigned DCACHE_SET_ASSOC = 8; + localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(CONFIG_L1D_SIZE / DCACHE_SET_ASSOC); // in bit, contains also offset width localparam int unsigned DCACHE_TAG_WIDTH = riscv::PLEN-DCACHE_INDEX_WIDTH; // in bit localparam int unsigned DCACHE_LINE_WIDTH = 128; // in bit - localparam int unsigned DCACHE_SET_ASSOC = 8; `endif // ---------------