From 802066bfd374ab0faacec20b9c4d46e9b57390f5 Mon Sep 17 00:00:00 2001
From: slgth <166491525+slgth@users.noreply.github.com>
Date: Sun, 16 Jun 2024 23:20:41 +0200
Subject: [PATCH] docs: move riscv-isa-manual outside of cv32a65x documentation
 (#2264)

---
 .gitmodules                                   |   2 +-
 docs/04_cv32a65x/riscv/Makefile               |  29 ++-----------
 docs/riscv-isa/build.mk                       |  41 ++++++++++++++++++
 .../riscv => riscv-isa}/riscv-isa-manual      |   0
 .../riscv => riscv-isa}/src/a-st-ext.adoc     |   0
 .../riscv => riscv-isa}/src/bfloat16.adoc     |   0
 .../src/calling-convention.adoc               |   0
 .../riscv => riscv-isa}/src/cmo.adoc          |   0
 .../riscv => riscv-isa}/src/colophon.adoc     |   0
 .../riscv => riscv-isa}/src/counters.adoc     |   0
 .../riscv => riscv-isa}/src/d-st-ext.adoc     |   0
 .../riscv => riscv-isa}/src/f-st-ext.adoc     |   0
 .../riscv => riscv-isa}/src/hypervisor.adoc   |   0
 .../src/images/bytefield/pmp-rv32.adoc        |   0
 .../src/images/ohg_logo.png                   | Bin
 .../riscv => riscv-isa}/src/indirect-csr.adoc |   0
 .../riscv => riscv-isa}/src/machine.adoc      |   0
 .../riscv => riscv-isa}/src/priv-cfi.adoc     |   0
 .../riscv => riscv-isa}/src/priv-preface.adoc |   0
 .../riscv => riscv-isa}/src/q-st-ext.adoc     |   0
 .../src/resources/themes/riscv-spec.yml       |   0
 .../src/riscv-privileged.adoc                 |   6 +--
 .../src/riscv-unprivileged.adoc               |   6 +--
 .../riscv => riscv-isa}/src/rnmi.adoc         |   0
 .../riscv => riscv-isa}/src/rv-32-64g.adoc    |   0
 .../riscv => riscv-isa}/src/rv128.adoc        |   0
 .../riscv => riscv-isa}/src/rv32e.adoc        |   0
 .../riscv => riscv-isa}/src/rv64.adoc         |   0
 .../src/scalar-crypto.adoc                    |   0
 .../riscv => riscv-isa}/src/smcdeleg.adoc     |   0
 .../riscv => riscv-isa}/src/smcntrpmf.adoc    |   0
 .../riscv => riscv-isa}/src/smdbltrp.adoc     |   0
 .../riscv => riscv-isa}/src/smepmp.adoc       |   0
 .../riscv => riscv-isa}/src/smstateen.adoc    |   0
 .../riscv => riscv-isa}/src/sscofpmf.adoc     |   0
 .../riscv => riscv-isa}/src/ssdbltrp.adoc     |   0
 .../riscv => riscv-isa}/src/sstc.adoc         |   0
 .../riscv => riscv-isa}/src/supervisor.adoc   |   0
 .../riscv => riscv-isa}/src/unpriv-cfi.adoc   |   0
 .../riscv => riscv-isa}/src/v-st-ext.adoc     |   0
 .../src/vector-crypto.adoc                    |   0
 .../src/vector-examples.adoc                  |   0
 .../riscv => riscv-isa}/src/zabha.adoc        |   0
 .../riscv => riscv-isa}/src/zacas.adoc        |   0
 .../riscv => riscv-isa}/src/zawrs.adoc        |   0
 .../riscv => riscv-isa}/src/zfa.adoc          |   0
 .../riscv => riscv-isa}/src/zfh.adoc          |   0
 .../riscv => riscv-isa}/src/zfinx.adoc        |   0
 .../riscv => riscv-isa}/src/zicond.adoc       |   0
 .../riscv => riscv-isa}/src/zifencei.adoc     |   0
 .../riscv => riscv-isa}/src/zihintntl.adoc    |   0
 .../riscv => riscv-isa}/src/zihintpause.adoc  |   0
 .../riscv => riscv-isa}/src/zimop.adoc        |   0
 .../riscv => riscv-isa}/src/ztso-st-ext.adoc  |   0
 54 files changed, 51 insertions(+), 33 deletions(-)
 create mode 100644 docs/riscv-isa/build.mk
 rename docs/{04_cv32a65x/riscv => riscv-isa}/riscv-isa-manual (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/a-st-ext.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/bfloat16.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/calling-convention.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/cmo.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/colophon.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/counters.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/d-st-ext.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/f-st-ext.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/hypervisor.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/images/bytefield/pmp-rv32.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/images/ohg_logo.png (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/indirect-csr.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/machine.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/priv-cfi.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/priv-preface.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/q-st-ext.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/resources/themes/riscv-spec.yml (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/riscv-privileged.adoc (97%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/riscv-unprivileged.adoc (98%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/rnmi.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/rv-32-64g.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/rv128.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/rv32e.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/rv64.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/scalar-crypto.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/smcdeleg.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/smcntrpmf.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/smdbltrp.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/smepmp.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/smstateen.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/sscofpmf.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/ssdbltrp.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/sstc.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/supervisor.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/unpriv-cfi.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/v-st-ext.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/vector-crypto.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/vector-examples.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zabha.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zacas.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zawrs.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zfa.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zfh.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zfinx.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zicond.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zifencei.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zihintntl.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zihintpause.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/zimop.adoc (100%)
 rename docs/{04_cv32a65x/riscv => riscv-isa}/src/ztso-st-ext.adoc (100%)

diff --git a/.gitmodules b/.gitmodules
index 81f655384f..ac5783d35e 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -47,5 +47,5 @@
 	path = verif/sim/dv
 	url = https://github.com/google/riscv-dv.git
 [submodule "docs/06_cv32a65x_riscv/riscv-isa-manual"]
-	path = docs/04_cv32a65x/riscv/riscv-isa-manual
+	path = docs/riscv-isa/riscv-isa-manual
 	url = https://github.com/riscv/riscv-isa-manual.git
diff --git a/docs/04_cv32a65x/riscv/Makefile b/docs/04_cv32a65x/riscv/Makefile
index 0b756f386c..221fa66467 100644
--- a/docs/04_cv32a65x/riscv/Makefile
+++ b/docs/04_cv32a65x/riscv/Makefile
@@ -4,30 +4,7 @@
 #   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #   You may obtain a copy of the License at https://solderpad.org/licenses/
 #
-#   Original Author: Jean-Roch COULON - Thales
+#   Original Author: Thales DIS
 
-all: priv-pdf priv-html unpriv-pdf unpriv-html
-
-setup:
-	mkdir -p build/riscv-isa-manual
-	cp -r riscv-isa-manual/* build/riscv-isa-manual
-	cp -r src build/riscv-isa-manual
-
-priv-pdf: setup
-	cd build/riscv-isa-manual/build; make priv-pdf
-	cp ./build/riscv-isa-manual/build/riscv-privileged.pdf priv-isa-cv32a65x.pdf
-
-priv-html: setup
-	cd build/riscv-isa-manual/build; make priv-html
-	cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-cv32a65x.html
-
-unpriv-pdf: setup
-	cd build/riscv-isa-manual/build; make unpriv-pdf
-	cp ./build/riscv-isa-manual/build/riscv-unprivileged.pdf unpriv-isa-cv32a65x.pdf
-
-unpriv-html: setup
-	cd build/riscv-isa-manual/build; make unpriv-html
-	cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-cv32a65x.html
-
-clean:
-	rm -rf build
+CONFIG := cv32a65x
+include ../../riscv-isa/build.mk
diff --git a/docs/riscv-isa/build.mk b/docs/riscv-isa/build.mk
new file mode 100644
index 0000000000..b046b49dbf
--- /dev/null
+++ b/docs/riscv-isa/build.mk
@@ -0,0 +1,41 @@
+#   Copyright 2024 Thales DIS France SAS
+#   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+#   you may not use this file except in compliance with the License.
+#   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#   You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+#   Original Author: Jean-Roch COULON - Thales
+
+ifeq ($(CONFIG),)
+$(error CONFIG must be defined)
+endif
+
+# Path of current file, intended to be included by a configuration subfolder
+riscv-isa_dir := $(dir $(lastword $(MAKEFILE_LIST)))
+
+all: priv-pdf priv-html unpriv-pdf unpriv-html
+
+setup:
+	mkdir -p build/riscv-isa-manual
+	cp -r $(riscv-isa_dir)/riscv-isa-manual/* build/riscv-isa-manual
+	cp -r $(riscv-isa_dir)/src build/riscv-isa-manual
+	cp -r src build/riscv-isa-manual
+
+priv-pdf: setup
+	cd build/riscv-isa-manual/build; make priv-pdf
+	cp ./build/riscv-isa-manual/build/riscv-privileged.pdf priv-isa-$(CONFIG).pdf
+
+priv-html: setup
+	cd build/riscv-isa-manual/build; make priv-html
+	cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-$(CONFIG).html
+
+unpriv-pdf: setup
+	cd build/riscv-isa-manual/build; make unpriv-pdf
+	cp ./build/riscv-isa-manual/build/riscv-unprivileged.pdf unpriv-isa-$(CONFIG).pdf
+
+unpriv-html: setup
+	cd build/riscv-isa-manual/build; make unpriv-html
+	cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-$(CONFIG).html
+
+clean:
+	rm -rf build
diff --git a/docs/04_cv32a65x/riscv/riscv-isa-manual b/docs/riscv-isa/riscv-isa-manual
similarity index 100%
rename from docs/04_cv32a65x/riscv/riscv-isa-manual
rename to docs/riscv-isa/riscv-isa-manual
diff --git a/docs/04_cv32a65x/riscv/src/a-st-ext.adoc b/docs/riscv-isa/src/a-st-ext.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/a-st-ext.adoc
rename to docs/riscv-isa/src/a-st-ext.adoc
diff --git a/docs/04_cv32a65x/riscv/src/bfloat16.adoc b/docs/riscv-isa/src/bfloat16.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/bfloat16.adoc
rename to docs/riscv-isa/src/bfloat16.adoc
diff --git a/docs/04_cv32a65x/riscv/src/calling-convention.adoc b/docs/riscv-isa/src/calling-convention.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/calling-convention.adoc
rename to docs/riscv-isa/src/calling-convention.adoc
diff --git a/docs/04_cv32a65x/riscv/src/cmo.adoc b/docs/riscv-isa/src/cmo.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/cmo.adoc
rename to docs/riscv-isa/src/cmo.adoc
diff --git a/docs/04_cv32a65x/riscv/src/colophon.adoc b/docs/riscv-isa/src/colophon.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/colophon.adoc
rename to docs/riscv-isa/src/colophon.adoc
diff --git a/docs/04_cv32a65x/riscv/src/counters.adoc b/docs/riscv-isa/src/counters.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/counters.adoc
rename to docs/riscv-isa/src/counters.adoc
diff --git a/docs/04_cv32a65x/riscv/src/d-st-ext.adoc b/docs/riscv-isa/src/d-st-ext.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/d-st-ext.adoc
rename to docs/riscv-isa/src/d-st-ext.adoc
diff --git a/docs/04_cv32a65x/riscv/src/f-st-ext.adoc b/docs/riscv-isa/src/f-st-ext.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/f-st-ext.adoc
rename to docs/riscv-isa/src/f-st-ext.adoc
diff --git a/docs/04_cv32a65x/riscv/src/hypervisor.adoc b/docs/riscv-isa/src/hypervisor.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/hypervisor.adoc
rename to docs/riscv-isa/src/hypervisor.adoc
diff --git a/docs/04_cv32a65x/riscv/src/images/bytefield/pmp-rv32.adoc b/docs/riscv-isa/src/images/bytefield/pmp-rv32.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/images/bytefield/pmp-rv32.adoc
rename to docs/riscv-isa/src/images/bytefield/pmp-rv32.adoc
diff --git a/docs/04_cv32a65x/riscv/src/images/ohg_logo.png b/docs/riscv-isa/src/images/ohg_logo.png
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/images/ohg_logo.png
rename to docs/riscv-isa/src/images/ohg_logo.png
diff --git a/docs/04_cv32a65x/riscv/src/indirect-csr.adoc b/docs/riscv-isa/src/indirect-csr.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/indirect-csr.adoc
rename to docs/riscv-isa/src/indirect-csr.adoc
diff --git a/docs/04_cv32a65x/riscv/src/machine.adoc b/docs/riscv-isa/src/machine.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/machine.adoc
rename to docs/riscv-isa/src/machine.adoc
diff --git a/docs/04_cv32a65x/riscv/src/priv-cfi.adoc b/docs/riscv-isa/src/priv-cfi.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/priv-cfi.adoc
rename to docs/riscv-isa/src/priv-cfi.adoc
diff --git a/docs/04_cv32a65x/riscv/src/priv-preface.adoc b/docs/riscv-isa/src/priv-preface.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/priv-preface.adoc
rename to docs/riscv-isa/src/priv-preface.adoc
diff --git a/docs/04_cv32a65x/riscv/src/q-st-ext.adoc b/docs/riscv-isa/src/q-st-ext.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/q-st-ext.adoc
rename to docs/riscv-isa/src/q-st-ext.adoc
diff --git a/docs/04_cv32a65x/riscv/src/resources/themes/riscv-spec.yml b/docs/riscv-isa/src/resources/themes/riscv-spec.yml
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/resources/themes/riscv-spec.yml
rename to docs/riscv-isa/src/resources/themes/riscv-spec.yml
diff --git a/docs/04_cv32a65x/riscv/src/riscv-privileged.adoc b/docs/riscv-isa/src/riscv-privileged.adoc
similarity index 97%
rename from docs/04_cv32a65x/riscv/src/riscv-privileged.adoc
rename to docs/riscv-isa/src/riscv-privileged.adoc
index 45367e718d..2bd1194953 100644
--- a/docs/04_cv32a65x/riscv/src/riscv-privileged.adoc
+++ b/docs/riscv-isa/src/riscv-privileged.adoc
@@ -1,5 +1,7 @@
+include::config.adoc[]
+
 [[risc-v-isa]]
-= The RISC-V Instruction Set Manual for CV32A65X: Volume II: Privileged Architecture
+= The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture
 :description: Volume II - Privileged Architecture
 :company: RISC-V.org
 :revnumber: 20240612
@@ -60,8 +62,6 @@ endif::[]
 :approx: &#8776;
 :inf: &#8734;
 
-include::config.adoc[]
-
 This document describes the RISC-V privileged architecture tailored for
 OpenHW Group {ohg-config}.
 Not relevant parts (e.g. unsupported extensions) of the original
diff --git a/docs/04_cv32a65x/riscv/src/riscv-unprivileged.adoc b/docs/riscv-isa/src/riscv-unprivileged.adoc
similarity index 98%
rename from docs/04_cv32a65x/riscv/src/riscv-unprivileged.adoc
rename to docs/riscv-isa/src/riscv-unprivileged.adoc
index efa5176dc9..1ba63ad6d0 100644
--- a/docs/04_cv32a65x/riscv/src/riscv-unprivileged.adoc
+++ b/docs/riscv-isa/src/riscv-unprivileged.adoc
@@ -1,5 +1,7 @@
+include::config.adoc[]
+
 [[risc-v-isa]]
-= The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture
+= The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture
 :description: Volume I - Unprivileged Architecture
 :company: RISC-V.org
 :revnumber: 20240612
@@ -57,8 +59,6 @@ endif::[]
 :inf: &#8734;
 :csrname: envcfg
 
-include::config.adoc[]
-
 This document describes the RISC-V unprivileged architecture tailored for
 OpenHW Group {ohg-config}.
 Not relevant parts (e.g. unsupported extensions) of the original
diff --git a/docs/04_cv32a65x/riscv/src/rnmi.adoc b/docs/riscv-isa/src/rnmi.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/rnmi.adoc
rename to docs/riscv-isa/src/rnmi.adoc
diff --git a/docs/04_cv32a65x/riscv/src/rv-32-64g.adoc b/docs/riscv-isa/src/rv-32-64g.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/rv-32-64g.adoc
rename to docs/riscv-isa/src/rv-32-64g.adoc
diff --git a/docs/04_cv32a65x/riscv/src/rv128.adoc b/docs/riscv-isa/src/rv128.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/rv128.adoc
rename to docs/riscv-isa/src/rv128.adoc
diff --git a/docs/04_cv32a65x/riscv/src/rv32e.adoc b/docs/riscv-isa/src/rv32e.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/rv32e.adoc
rename to docs/riscv-isa/src/rv32e.adoc
diff --git a/docs/04_cv32a65x/riscv/src/rv64.adoc b/docs/riscv-isa/src/rv64.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/rv64.adoc
rename to docs/riscv-isa/src/rv64.adoc
diff --git a/docs/04_cv32a65x/riscv/src/scalar-crypto.adoc b/docs/riscv-isa/src/scalar-crypto.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/scalar-crypto.adoc
rename to docs/riscv-isa/src/scalar-crypto.adoc
diff --git a/docs/04_cv32a65x/riscv/src/smcdeleg.adoc b/docs/riscv-isa/src/smcdeleg.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/smcdeleg.adoc
rename to docs/riscv-isa/src/smcdeleg.adoc
diff --git a/docs/04_cv32a65x/riscv/src/smcntrpmf.adoc b/docs/riscv-isa/src/smcntrpmf.adoc
similarity index 100%
rename from docs/04_cv32a65x/riscv/src/smcntrpmf.adoc
rename to docs/riscv-isa/src/smcntrpmf.adoc
diff --git a/docs/04_cv32a65x/riscv/src/smdbltrp.adoc b/docs/riscv-isa/src/smdbltrp.adoc
similarity index 100%
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