diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/.cproject b/examples/mss-rtc/mpfs-rtc-interrupt/.cproject index c1732ca..df1f381 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/.cproject +++ b/examples/mss-rtc/mpfs-rtc-interrupt/.cproject @@ -99,13 +99,15 @@ @@ -121,13 +123,15 @@ @@ -247,7 +251,7 @@ - + @@ -317,13 +321,15 @@ @@ -343,13 +349,15 @@ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/mpfs-rtc-interrupt hw all-harts debug.launch b/examples/mss-rtc/mpfs-rtc-interrupt/mpfs-rtc-interrupt hw all-harts debug.launch index 76329aa..c0b9e40 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/mpfs-rtc-interrupt hw all-harts debug.launch +++ b/examples/mss-rtc/mpfs-rtc-interrupt/mpfs-rtc-interrupt hw all-harts debug.launch @@ -10,7 +10,7 @@ - + @@ -33,7 +33,7 @@ - + diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/application/hart0/e51.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/application/hart0/e51.c index 53141a7..aafaae8 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/application/hart0/e51.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/application/hart0/e51.c @@ -55,8 +55,7 @@ void e51(void) PLIC_SetPriority(RTC_WAKEUP_PLIC, 2); SYSREG->SUBBLK_CLOCK_CR = 0xffffffff; - SYSREG->SOFT_RESET_CR &= ~( (1u << 0u) | (1u << 4u) | (1u << 5u) | - (1u << 19u) | (1u << 23u) | (1u << 28u) | (1u << 18u)) ; /* RTC*/ + SYSREG->SOFT_RESET_CR &= ~((1u << 5u) | (1u << 18u)) ; /* RTC and MMUART0 */ MSS_UART_init(&g_mss_uart0_lo, MSS_UART_115200_BAUD, @@ -66,11 +65,11 @@ void e51(void) temp = BIT_SET; SYSREG->RTC_CLOCK_CR &= ~BIT_SET; - SYSREG->RTC_CLOCK_CR = LIBERO_SETTING_MSS_RTC_TOGGLE_CLK / 100000UL; + SYSREG->RTC_CLOCK_CR = LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK / LIBERO_SETTING_MSS_RTC_TOGGLE_CLK; SYSREG->RTC_CLOCK_CR |= BIT_SET; /* Initialize RTC. */ - MSS_RTC_init(MSS_RTC_LO_BASE, MSS_RTC_BINARY_MODE, RTC_PERIPH_PRESCALER / 10u ); + MSS_RTC_init(MSS_RTC_LO_BASE, MSS_RTC_BINARY_MODE, RTC_PERIPH_PRESCALER); /* Set initial RTC count and match values. */ MSS_RTC_reset_counter(); diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_ddr_pll.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_ddr_pll.h deleted file mode 100644 index 2f5c741..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_ddr_pll.h +++ /dev/null @@ -1,198 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_ddr_pll.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_ddr_pll.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_DDR_PLL_H_ -#define HW_CLK_DDR_PLL_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DDR_SOFT_RESET) -/*This is a compulsory register for all SCB slaves and must be at the same -offset in all slaves to facilitate global soft reset of all SCB registers with -a single broadcast write from the SCB master. */ -#define LIBERO_SETTING_DDR_SOFT_RESET 0x00000000UL - /* NV_MAP [0:1] RST */ - /* V_MAP [1:1] RST */ - /* PERIPH [8:1] RST */ - /* BLOCKID [16:16] ID */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_CTRL) -/*PLL control register */ -#define LIBERO_SETTING_DDR_PLL_CTRL 0x0100003FUL - /* REG_POWERDOWN_B [0:1] RW value= 0x1 */ - /* REG_RFDIV_EN [1:1] RW value= 0x1 */ - /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ - /* REG_DIVQ1_EN [3:1] RW value= 0x1 */ - /* REG_DIVQ2_EN [4:1] RW value= 0x1 */ - /* REG_DIVQ3_EN [5:1] RW value= 0x1 */ - /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ - /* RESETONLOCK [7:1] RW value= 0x0 */ - /* BYPCK_SEL [8:4] RW value= 0x0 */ - /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ - /* RESERVE10 [13:3] RSVD */ - /* REG_BYPASSPRE [16:4] RW value= 0x0 */ - /* REG_BYPASSPOST [20:4] RW value= 0x0 */ - /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ - /* LOCK [25:1] RO */ - /* LOCK_INT_EN [26:1] RW value= 0x0 */ - /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ - /* LOCK_INT [28:1] SW1C */ - /* UNLOCK_INT [29:1] SW1C */ - /* RESERVE11 [30:1] RSVD */ - /* LOCK_B [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_REF_FB) -/*PLL reference and feedback registers */ -#define LIBERO_SETTING_DDR_PLL_REF_FB 0x00000500UL - /* FSE_B [0:1] RW value= 0x0 */ - /* FBCK_SEL [1:2] RW value= 0x0 */ - /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ - /* RESERVE12 [4:4] RSVD */ - /* RFDIV [8:6] RW value= 0x5 */ - /* RESERVE13 [14:2] RSVD */ - /* RESERVE14 [16:12] RSVD */ - /* RESERVE15 [28:4] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_FRACN) -/*PLL fractional register */ -#define LIBERO_SETTING_DDR_PLL_FRACN 0x00000000UL - /* FRACN_EN [0:1] RW value= 0x0 */ - /* FRACN_DAC_EN [1:1] RW value= 0x0 */ - /* RESERVE16 [2:6] RSVD */ - /* RESERVE17 [8:24] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_DIV_0_1) -/*PLL 0/1 division registers */ -#define LIBERO_SETTING_DDR_PLL_DIV_0_1 0x02000100UL - /* VCO0PH_SEL [0:3] RO */ - /* DIV0_START [3:3] RW value= 0x0 */ - /* RESERVE18 [6:2] RSVD */ - /* POST0DIV [8:7] RW value= 0x1 */ - /* RESERVE19 [15:1] RSVD */ - /* VCO1PH_SEL [16:3] RO */ - /* DIV1_START [19:3] RW value= 0x0 */ - /* RESERVE20 [22:2] RSVD */ - /* POST1DIV [24:7] RW value= 0x2 */ - /* RESERVE21 [31:1] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_DIV_2_3) -/*PLL 2/3 division registers */ -#define LIBERO_SETTING_DDR_PLL_DIV_2_3 0x01000100UL - /* VCO2PH_SEL [0:3] RO */ - /* DIV2_START [3:3] RW value= 0x0 */ - /* RESERVE22 [6:2] RSVD */ - /* POST2DIV [8:7] RW value= 0x1 */ - /* RESERVE23 [15:1] RSVD */ - /* VCO3PH_SEL [16:3] RO */ - /* DIV3_START [19:3] RW value= 0x0 */ - /* RESERVE24 [22:2] RSVD */ - /* POST3DIV [24:7] RW value= 0x1 */ - /* CKPOST3_SEL [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_CTRL2) -/*PLL control register */ -#define LIBERO_SETTING_DDR_PLL_CTRL2 0x00001020UL - /* BWI [0:2] RW value= 0x0 */ - /* BWP [2:2] RW value= 0x0 */ - /* IREF_EN [4:1] RW value= 0x0 */ - /* IREF_TOGGLE [5:1] RW value= 0x1 */ - /* RESERVE25 [6:3] RSVD */ - /* LOCKCNT [9:4] RW value= 0x8 */ - /* RESERVE26 [13:4] RSVD */ - /* ATEST_EN [17:1] RW value= 0x0 */ - /* ATEST_SEL [18:3] RW value= 0x0 */ - /* RESERVE27 [21:11] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_CAL) -/*PLL calibration register */ -#define LIBERO_SETTING_DDR_PLL_CAL 0x00000D06UL - /* DSKEWCALCNT [0:3] RW value= 0x6 */ - /* DSKEWCAL_EN [3:1] RW value= 0x0 */ - /* DSKEWCALBYP [4:1] RW value= 0x0 */ - /* RESERVE28 [5:3] RSVD */ - /* DSKEWCALIN [8:7] RW value= 0xd */ - /* RESERVE29 [15:1] RSVD */ - /* DSKEWCALOUT [16:7] RO */ - /* RESERVE30 [23:9] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_PHADJ) -/*PLL phase registers */ -#define LIBERO_SETTING_DDR_PLL_PHADJ 0x00005003UL - /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ - /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ - /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ - /* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */ - /* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */ - /* REG_OUT3_PHSINIT [11:3] RW value= 0x2 */ - /* REG_LOADPHS_B [14:1] RW value= 0x1 */ - /* RESERVE31 [15:17] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_0) -/*SSCG registers 0 */ -#define LIBERO_SETTING_DDR_SSCG_REG_0 0x00000000UL - /* DIVVAL [0:6] RW value= 0x0 */ - /* FRACIN [6:24] RW value= 0x0 */ - /* RESERVE00 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_1) -/*SSCG registers 1 */ -#define LIBERO_SETTING_DDR_SSCG_REG_1 0x00000000UL - /* DOWNSPREAD [0:1] RW value= 0x0 */ - /* SSMD [1:5] RW value= 0x0 */ - /* FRACMOD [6:24] RO */ - /* RESERVE01 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_2) -/*SSCG registers 2 */ -#define LIBERO_SETTING_DDR_SSCG_REG_2 0x00000080UL - /* INTIN [0:12] RW value= 0x80 */ - /* INTMOD [12:12] RO */ - /* RESERVE02 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_3) -/*SSCG registers 3 */ -#define LIBERO_SETTING_DDR_SSCG_REG_3 0x00000001UL - /* SSE_B [0:1] RW value= 0x1 */ - /* SEL_EXTWAVE [1:2] RW value= 0x0 */ - /* EXT_MAXADDR [3:8] RW value= 0x0 */ - /* TBLADDR [11:8] RO */ - /* RANDOM_FILTER [19:1] RW value= 0x0 */ - /* RANDOM_SEL [20:2] RW value= 0x0 */ - /* RESERVE03 [22:1] RSVD */ - /* RESERVE04 [23:9] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_DDR_PLL_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_mss_cfm.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_mss_cfm.h deleted file mode 100644 index 6fde0cf..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_mss_cfm.h +++ /dev/null @@ -1,115 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_mss_cfm.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_mss_cfm.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_MSS_CFM_H_ -#define HW_CLK_MSS_CFM_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_BCLKMUX) -/*Input mux selections */ -#define LIBERO_SETTING_MSS_BCLKMUX 0x00000208UL - /* BCLK0_SEL [0:5] RW value= 0x8 */ - /* BCLK1_SEL [5:5] RW value= 0x10 */ - /* BCLK2_SEL [10:5] RW value= 0x0 */ - /* BCLK3_SEL [15:5] RW value= 0x0 */ - /* BCLK4_SEL [20:5] RW value= 0x0 */ - /* BCLK5_SEL [25:5] RW value= 0x0 */ - /* RESERVED [30:2] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_CKMUX) -/*Input mux selections */ -#define LIBERO_SETTING_MSS_PLL_CKMUX 0x00000155UL - /* CLK_IN_MAC_TSU_SEL [0:2] RW value= 0x1 */ - /* PLL0_RFCLK0_SEL [2:2] RW value= 0x1 */ - /* PLL0_RFCLK1_SEL [4:2] RW value= 0x1 */ - /* PLL1_RFCLK0_SEL [6:2] RW value= 0x1 */ - /* PLL1_RFCLK1_SEL [8:2] RW value= 0x1 */ - /* PLL1_FDR_SEL [10:5] RW value= 0x0 */ - /* RESERVED [15:17] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_MSSCLKMUX) -/*MSS Clock mux selections */ -#define LIBERO_SETTING_MSS_MSSCLKMUX 0x00000003UL - /* MSSCLK_MUX_SEL [0:2] RW value= 0x3 */ - /* MSSCLK_MUX_MD [2:2] RW value= 0x0 */ - /* CLK_STANDBY_SEL [4:1] RW value= 0x0 */ - /* RESERVED [5:27] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_SPARE0) -/*spare logic */ -#define LIBERO_SETTING_MSS_SPARE0 0x00000000UL - /* SPARE0 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_FMETER_ADDR) -/*Frequency_meter_address_selections */ -#define LIBERO_SETTING_MSS_FMETER_ADDR 0x00000000UL - /* ADDR10 [0:2] RSVD */ - /* ADDR [2:4] RW value= 0x0 */ - /* RESERVE18 [6:26] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_FMETER_DATAW) -/*Frequency_meter_data_write */ -#define LIBERO_SETTING_MSS_FMETER_DATAW 0x00000000UL - /* DATA [0:24] RW value= 0x0 */ - /* STROBE [24:1] W1P */ - /* RESERVE19 [25:7] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_FMETER_DATAR) -/*Frequency_meter_data_read */ -#define LIBERO_SETTING_MSS_FMETER_DATAR 0x00000000UL - /* DATA [0:24] RO */ - /* RESERVE20 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_IMIRROR_TRIM) -/*Imirror TRIM Bits */ -#define LIBERO_SETTING_MSS_IMIRROR_TRIM 0x00000000UL - /* BG_CODE [0:3] RW value= 0x0 */ - /* CC_CODE [3:8] RW value= 0x0 */ - /* RESERVE21 [11:21] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_TEST_CTRL) -/*Test MUX Controls */ -#define LIBERO_SETTING_MSS_TEST_CTRL 0x00000000UL - /* OSC_ENABLE [0:4] RW value= 0x0 */ - /* ATEST_EN [4:1] RW value= 0x0 */ - /* ATEST_SEL [5:5] RW value= 0x0 */ - /* DTEST_EN [10:1] RW value= 0x0 */ - /* DTEST_SEL [11:5] RW value= 0x0 */ - /* RESERVE22 [16:16] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_MSS_CFM_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_mss_pll.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_mss_pll.h deleted file mode 100644 index fb6a379..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_mss_pll.h +++ /dev/null @@ -1,188 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_mss_pll.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_mss_pll.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_MSS_PLL_H_ -#define HW_CLK_MSS_PLL_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_PLL_CTRL) -/*PLL control register */ -#define LIBERO_SETTING_MSS_PLL_CTRL 0x01000007UL - /* REG_POWERDOWN_B [0:1] RW value= 0x1 */ - /* REG_RFDIV_EN [1:1] RW value= 0x1 */ - /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ - /* REG_DIVQ1_EN [3:1] RW value= 0x0 */ - /* REG_DIVQ2_EN [4:1] RW value= 0x0 */ - /* REG_DIVQ3_EN [5:1] RW value= 0x0 */ - /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ - /* RESETONLOCK [7:1] RW value= 0x0 */ - /* BYPCK_SEL [8:4] RW value= 0x0 */ - /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ - /* RESERVE10 [13:3] RSVD */ - /* REG_BYPASSPRE [16:4] RW value= 0x0 */ - /* REG_BYPASSPOST [20:4] RW value= 0x0 */ - /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ - /* LOCK [25:1] RO */ - /* LOCK_INT_EN [26:1] RW value= 0x0 */ - /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ - /* LOCK_INT [28:1] SW1C */ - /* UNLOCK_INT [29:1] SW1C */ - /* RESERVE11 [30:1] RSVD */ - /* LOCK_B [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_REF_FB) -/*PLL reference and feedback registers */ -#define LIBERO_SETTING_MSS_PLL_REF_FB 0x00000500UL - /* FSE_B [0:1] RW value= 0x0 */ - /* FBCK_SEL [1:2] RW value= 0x0 */ - /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ - /* RESERVE12 [4:4] RSVD */ - /* RFDIV [8:6] RW value= 0x5 */ - /* RESERVE13 [14:2] RSVD */ - /* RESERVE14 [16:12] RSVD */ - /* RESERVE15 [28:4] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_FRACN) -/*PLL fractional register */ -#define LIBERO_SETTING_MSS_PLL_FRACN 0x00000000UL - /* FRACN_EN [0:1] RW value= 0x0 */ - /* FRACN_DAC_EN [1:1] RW value= 0x0 */ - /* RESERVE16 [2:6] RSVD */ - /* RESERVE17 [8:24] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_DIV_0_1) -/*PLL 0/1 division registers */ -#define LIBERO_SETTING_MSS_PLL_DIV_0_1 0x01000100UL - /* VCO0PH_SEL [0:3] RO */ - /* DIV0_START [3:3] RW value= 0x0 */ - /* RESERVE18 [6:2] RSVD */ - /* POST0DIV [8:7] RW value= 0x1 */ - /* RESERVE19 [15:1] RSVD */ - /* VCO1PH_SEL [16:3] RO */ - /* DIV1_START [19:3] RW value= 0x0 */ - /* RESERVE20 [22:2] RSVD */ - /* POST1DIV [24:7] RW value= 0x1 */ - /* RESERVE21 [31:1] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_DIV_2_3) -/*PLL 2/3 division registers */ -#define LIBERO_SETTING_MSS_PLL_DIV_2_3 0x01000100UL - /* VCO2PH_SEL [0:3] RO */ - /* DIV2_START [3:3] RW value= 0x0 */ - /* RESERVE22 [6:2] RSVD */ - /* POST2DIV [8:7] RW value= 0x1 */ - /* RESERVE23 [15:1] RSVD */ - /* VCO3PH_SEL [16:3] RO */ - /* DIV3_START [19:3] RW value= 0x0 */ - /* RESERVE24 [22:2] RSVD */ - /* POST3DIV [24:7] RW value= 0x1 */ - /* CKPOST3_SEL [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_CTRL2) -/*PLL control register */ -#define LIBERO_SETTING_MSS_PLL_CTRL2 0x00001020UL - /* BWI [0:2] RW value= 0x0 */ - /* BWP [2:2] RW value= 0x0 */ - /* IREF_EN [4:1] RW value= 0x0 */ - /* IREF_TOGGLE [5:1] RW value= 0x1 */ - /* RESERVE25 [6:3] RSVD */ - /* LOCKCNT [9:4] RW value= 0x8 */ - /* RESERVE26 [13:4] RSVD */ - /* ATEST_EN [17:1] RW value= 0x0 */ - /* ATEST_SEL [18:3] RW value= 0x0 */ - /* RESERVE27 [21:11] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_CAL) -/*PLL calibration register */ -#define LIBERO_SETTING_MSS_PLL_CAL 0x00000D06UL - /* DSKEWCALCNT [0:3] RW value= 0x6 */ - /* DSKEWCAL_EN [3:1] RW value= 0x0 */ - /* DSKEWCALBYP [4:1] RW value= 0x0 */ - /* RESERVE28 [5:3] RSVD */ - /* DSKEWCALIN [8:7] RW value= 0xd */ - /* RESERVE29 [15:1] RSVD */ - /* DSKEWCALOUT [16:7] RO */ - /* RESERVE30 [23:9] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_PHADJ) -/*PLL phase registers */ -#define LIBERO_SETTING_MSS_PLL_PHADJ 0x00004003UL - /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ - /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ - /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ - /* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */ - /* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */ - /* REG_OUT3_PHSINIT [11:3] RW value= 0x8 */ - /* REG_LOADPHS_B [14:1] RW value= 0x0 */ - /* RESERVE31 [15:17] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_0) -/*SSCG registers 0 */ -#define LIBERO_SETTING_MSS_SSCG_REG_0 0x00000000UL - /* DIVVAL [0:6] RW value= 0x0 */ - /* FRACIN [6:24] RW value= 0x0 */ - /* RESERVE00 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_1) -/*SSCG registers 1 */ -#define LIBERO_SETTING_MSS_SSCG_REG_1 0x00000000UL - /* DOWNSPREAD [0:1] RW value= 0x0 */ - /* SSMD [1:5] RW value= 0x0 */ - /* FRACMOD [6:24] RO */ - /* RESERVE01 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_2) -/*SSCG registers 2 */ -#define LIBERO_SETTING_MSS_SSCG_REG_2 0x00000060UL - /* INTIN [0:12] RW value= 0x60 */ - /* INTMOD [12:12] RO */ - /* RESERVE02 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_3) -/*SSCG registers 3 */ -#define LIBERO_SETTING_MSS_SSCG_REG_3 0x00000001UL - /* SSE_B [0:1] RW value= 0x1 */ - /* SEL_EXTWAVE [1:2] RW value= 0x0 */ - /* EXT_MAXADDR [3:8] RW value= 0x0 */ - /* TBLADDR [11:8] RO */ - /* RANDOM_FILTER [19:1] RW value= 0x0 */ - /* RANDOM_SEL [20:2] RW value= 0x0 */ - /* RESERVE03 [22:1] RSVD */ - /* RESERVE04 [23:9] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_MSS_PLL_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_cfm.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_cfm.h deleted file mode 100644 index aab31e7..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_cfm.h +++ /dev/null @@ -1,85 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_sgmii_cfm.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_sgmii_cfm.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_SGMII_CFM_H_ -#define HW_CLK_SGMII_CFM_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SGMII_REFCLKMUX) -/*Input mux selections */ -#define LIBERO_SETTING_SGMII_REFCLKMUX 0x00000005UL - /* PLL0_RFCLK0_SEL [0:2] RW value= 0x1 */ - /* PLL0_RFCLK1_SEL [2:2] RW value= 0x1 */ - /* RESERVED [4:28] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SGMII_CLKMUX) -/*sgmii clk mux */ -#define LIBERO_SETTING_SGMII_SGMII_CLKMUX 0x00000005UL - /* SGMII_CLKMUX [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SPARE0) -/*spare logic */ -#define LIBERO_SETTING_SGMII_SPARE0 0x00000000UL - /* RESERVED [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_CLK_XCVR) -/*Clock_Receiver */ -#define LIBERO_SETTING_SGMII_CLK_XCVR 0x00002C30UL - /* EN_UDRIVE_P [0:1] RW value= 0x0 */ - /* EN_INS_HYST_P [1:1] RW value= 0x0 */ - /* EN_TERM_P [2:2] RW value= 0x0 */ - /* EN_RXMODE_P [4:2] RW value= 0x3 */ - /* EN_UDRIVE_N [6:1] RW value= 0x0 */ - /* EN_INS_HYST_N [7:1] RW value= 0x0 */ - /* EN_TERM_N [8:2] RW value= 0x0 */ - /* EN_RXMODE_N [10:2] RW value= 0x3 */ - /* CLKBUF_EN_PULLUP [12:1] RW value= 0x0 */ - /* EN_RDIFF [13:1] RW value= 0x1 */ - /* RESERVED [14:18] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_TEST_CTRL) -/*Test MUX Controls */ -#define LIBERO_SETTING_SGMII_TEST_CTRL 0x00000000UL - /* OSC_ENABLE [0:4] RW value= 0x0 */ - /* ATEST_EN [4:1] RW value= 0x0 */ - /* ATEST_SEL [5:5] RW value= 0x0 */ - /* DTEST_EN [10:1] RW value= 0x0 */ - /* DTEST_SEL [11:5] RW value= 0x0 */ - /* RESERVE22 [16:16] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_SGMII_CFM_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_pll.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_pll.h deleted file mode 100644 index d518916..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_pll.h +++ /dev/null @@ -1,198 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_sgmii_pll.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_sgmii_pll.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_SGMII_PLL_H_ -#define HW_CLK_SGMII_PLL_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SGMII_SOFT_RESET) -/*This is a compulsory register for all SCB slaves and must be at the same -offset in all slaves to facilitate global soft reset of all SCB registers with -a single broadcast write from the SCB master. */ -#define LIBERO_SETTING_SGMII_SOFT_RESET 0x00000000UL - /* NV_MAP [0:1] RST */ - /* V_MAP [1:1] RST */ - /* PERIPH [8:1] RST */ - /* BLOCKID [16:16] ID */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL) -/*PLL control register */ -#define LIBERO_SETTING_SGMII_PLL_CTRL 0x0100003EUL - /* REG_POWERDOWN_B [0:1] RW value= 0x0 */ - /* REG_RFDIV_EN [1:1] RW value= 0x1 */ - /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ - /* REG_DIVQ1_EN [3:1] RW value= 0x1 */ - /* REG_DIVQ2_EN [4:1] RW value= 0x1 */ - /* REG_DIVQ3_EN [5:1] RW value= 0x1 */ - /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ - /* RESETONLOCK [7:1] RW value= 0x0 */ - /* BYPCK_SEL [8:4] RW value= 0x0 */ - /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ - /* RESERVE10 [13:3] RSVD */ - /* REG_BYPASSPRE [16:4] RW value= 0x0 */ - /* REG_BYPASSPOST [20:4] RW value= 0x0 */ - /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ - /* LOCK [25:1] RO */ - /* LOCK_INT_EN [26:1] RW value= 0x0 */ - /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ - /* LOCK_INT [28:1] SW1C */ - /* UNLOCK_INT [29:1] SW1C */ - /* RESERVE11 [30:1] RSVD */ - /* LOCK_B [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_REF_FB) -/*PLL reference and feedback registers */ -#define LIBERO_SETTING_SGMII_PLL_REF_FB 0x00000100UL - /* FSE_B [0:1] RW value= 0x0 */ - /* FBCK_SEL [1:2] RW value= 0x0 */ - /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ - /* RESERVE12 [4:4] RSVD */ - /* RFDIV [8:6] RW value= 0x1 */ - /* RESERVE13 [14:2] RSVD */ - /* RESERVE14 [16:12] RSVD */ - /* RESERVE15 [28:4] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_FRACN) -/*PLL fractional register */ -#define LIBERO_SETTING_SGMII_PLL_FRACN 0x00000000UL - /* FRACN_EN [0:1] RW value= 0x0 */ - /* FRACN_DAC_EN [1:1] RW value= 0x0 */ - /* RESERVE16 [2:6] RSVD */ - /* RESERVE17 [8:24] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_0_1) -/*PLL 0/1 division registers */ -#define LIBERO_SETTING_SGMII_PLL_DIV_0_1 0x01000100UL - /* VCO0PH_SEL [0:3] RO */ - /* DIV0_START [3:3] RW value= 0x0 */ - /* RESERVE18 [6:2] RSVD */ - /* POST0DIV [8:7] RW value= 0x1 */ - /* RESERVE19 [15:1] RSVD */ - /* VCO1PH_SEL [16:3] RO */ - /* DIV1_START [19:3] RW value= 0x0 */ - /* RESERVE20 [22:2] RSVD */ - /* POST1DIV [24:7] RW value= 0x1 */ - /* RESERVE21 [31:1] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_2_3) -/*PLL 2/3 division registers */ -#define LIBERO_SETTING_SGMII_PLL_DIV_2_3 0x01000100UL - /* VCO2PH_SEL [0:3] RO */ - /* DIV2_START [3:3] RW value= 0x0 */ - /* RESERVE22 [6:2] RSVD */ - /* POST2DIV [8:7] RW value= 0x1 */ - /* RESERVE23 [15:1] RSVD */ - /* VCO3PH_SEL [16:3] RO */ - /* DIV3_START [19:3] RW value= 0x0 */ - /* RESERVE24 [22:2] RSVD */ - /* POST3DIV [24:7] RW value= 0x1 */ - /* CKPOST3_SEL [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL2) -/*PLL control register */ -#define LIBERO_SETTING_SGMII_PLL_CTRL2 0x00001020UL - /* BWI [0:2] RW value= 0x0 */ - /* BWP [2:2] RW value= 0x0 */ - /* IREF_EN [4:1] RW value= 0x0 */ - /* IREF_TOGGLE [5:1] RW value= 0x1 */ - /* RESERVE25 [6:3] RSVD */ - /* LOCKCNT [9:4] RW value= 0x8 */ - /* RESERVE26 [13:4] RSVD */ - /* ATEST_EN [17:1] RW value= 0x0 */ - /* ATEST_SEL [18:3] RW value= 0x0 */ - /* RESERVE27 [21:11] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_CAL) -/*PLL calibration register */ -#define LIBERO_SETTING_SGMII_PLL_CAL 0x00000D06UL - /* DSKEWCALCNT [0:3] RW value= 0x6 */ - /* DSKEWCAL_EN [3:1] RW value= 0x0 */ - /* DSKEWCALBYP [4:1] RW value= 0x0 */ - /* RESERVE28 [5:3] RSVD */ - /* DSKEWCALIN [8:7] RW value= 0xd */ - /* RESERVE29 [15:1] RSVD */ - /* DSKEWCALOUT [16:7] RO */ - /* RESERVE30 [23:9] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_PHADJ) -/*PLL phase registers */ -#define LIBERO_SETTING_SGMII_PLL_PHADJ 0x00007443UL - /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ - /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ - /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ - /* REG_OUT1_PHSINIT [5:3] RW value= 0x2 */ - /* REG_OUT2_PHSINIT [8:3] RW value= 0x4 */ - /* REG_OUT3_PHSINIT [11:3] RW value= 0x6 */ - /* REG_LOADPHS_B [14:1] RW value= 0x1 */ - /* RESERVE31 [15:17] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_0) -/*SSCG registers 0 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_0 0x00000000UL - /* DIVVAL [0:6] RW value= 0x0 */ - /* FRACIN [6:24] RW value= 0x0 */ - /* RESERVE00 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_1) -/*SSCG registers 1 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_1 0x00000000UL - /* DOWNSPREAD [0:1] RW value= 0x0 */ - /* SSMD [1:5] RW value= 0x0 */ - /* FRACMOD [6:24] RO */ - /* RESERVE01 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_2) -/*SSCG registers 2 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_2 0x00000019UL - /* INTIN [0:12] RW value= 0x19 */ - /* INTMOD [12:12] RO */ - /* RESERVE02 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_3) -/*SSCG registers 3 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_3 0x00000001UL - /* SSE_B [0:1] RW value= 0x1 */ - /* SEL_EXTWAVE [1:2] RW value= 0x0 */ - /* EXT_MAXADDR [3:8] RW value= 0x0 */ - /* TBLADDR [11:8] RO */ - /* RANDOM_FILTER [19:1] RW value= 0x0 */ - /* RANDOM_SEL [20:2] RW value= 0x0 */ - /* RESERVE03 [22:1] RSVD */ - /* RESERVE04 [23:9] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_SGMII_PLL_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sysreg.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sysreg.h deleted file mode 100644 index 0923b4b..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_clk_sysreg.h +++ /dev/null @@ -1,67 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_sysreg.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_sysreg.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_SYSREG_H_ -#define HW_CLK_SYSREG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR) -/*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */ -#define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR 0x00000024UL - /* DIVIDER_CPU [0:2] RW value= 0x0 */ - /* DIVIDER_AXI [2:2] RW value= 0x1 */ - /* DIVIDER_APB_AHB [4:2] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_MSS_RTC_CLOCK_CR) -/*RTC clock divider */ -#define LIBERO_SETTING_MSS_RTC_CLOCK_CR 0x00000064UL - /* PERIOD [0:12] RW value= 0x64 */ -#endif -#if !defined (LIBERO_SETTING_MSS_ENVM_CR) -/*ENVM AHB Controller setup - - Clock period = (Value+1) * (1000/AHBFREQMHZ) -e.g. 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz */ -#define LIBERO_SETTING_MSS_ENVM_CR 0x40050006UL - /* CLOCK_PERIOD [0:6] RW value= 0x6 */ - /* CLOCK_CONTINUOUS [8:1] RW value= 0x0 */ - /* CLOCK_SUPPRESS [9:1] RW value= 0x0 */ - /* READAHEAD [16:1] RW value= 0x1 */ - /* SLOWREAD [17:1] RW value= 0x0 */ - /* INTERRUPT_ENABLE [18:1] RW value= 0x1 */ - /* TIMER [24:8] RW value= 0x40 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_SYSREG_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_mss_clks.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_mss_clks.h deleted file mode 100644 index 72f1274..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/clocks/hw_mss_clks.h +++ /dev/null @@ -1,73 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mss_clks.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mss_clks.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MSS_CLKS_H_ -#define HW_MSS_CLKS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK) -/*Ref Clock rate in MHz */ -#define LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK 100000000 - /* MSS_EXT_SGMII_REF_CLK [0:32] RW value= 100000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK) -/*CPU Clock rate in MHz */ -#define LIBERO_SETTING_MSS_COREPLEX_CPU_CLK 600000000 - /* MSS_COREPLEX_CPU_CLK [0:32] RW value= 600000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_SYSTEM_CLK) -/*System Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_SYSTEM_CLK 600000000 - /* MSS_SYSTEM_CLK [0:32] RW value= 600000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_RTC_TOGGLE_CLK) -/*RTC toggle Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_RTC_TOGGLE_CLK 1000000 - /* MSS_RTC_TOGGLE_CLK [0:32] RW value= 1000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_AXI_CLK) -/*AXI Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_AXI_CLK 300000000 - /* MSS_AXI_CLK [0:32] RW value= 300000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_APB_AHB_CLK) -/*AXI Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_APB_AHB_CLK 150000000 - /* MSS_APB_AHB_CLK [0:32] RW value= 150000000 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MSS_CLKS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_io_bank.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_io_bank.h deleted file mode 100644 index 6e59d98..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_io_bank.h +++ /dev/null @@ -1,142 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_io_bank.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_io_bank.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_IO_BANK_H_ -#define HW_DDR_IO_BANK_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DPC_BITS) -/*DPC Bits Register */ -#define LIBERO_SETTING_DPC_BITS 0x0004C422UL - /* DPC_VS [0:4] RW value= 0x2 */ - /* DPC_VRGEN_H [4:6] RW value= 0x2 */ - /* DPC_VRGEN_EN_H [10:1] RW value= 0x1 */ - /* DPC_MOVE_EN_H [11:1] RW value= 0x0 */ - /* DPC_VRGEN_V [12:6] RW value= 0xC */ - /* DPC_VRGEN_EN_V [18:1] RW value= 0x1 */ - /* DPC_MOVE_EN_V [19:1] RW value= 0x0 */ - /* RESERVE01 [20:12] RSVD */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_DQ) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_DQ 0x00000006UL - /* RPC_ODT_DQ [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_DQS) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006UL - /* RPC_ODT_DQS [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_ADDCMD) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000004UL - /* RPC_ODT_ADDCMD [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_CLK) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002UL - /* RPC_ODT_CLK [0:32] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQ) -/*0x2000 73A8 (rpc10_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_DQ 0x00000005UL - /* RPC_ODT_STATIC_DQ [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQS) -/*0x2000 73AC (rpc11_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_DQS 0x00000005UL - /* RPC_ODT_STATIC_DQS [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD) -/*0x2000 739C (rpc7_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD 0x00000007UL - /* RPC_ODT_STATIC_ADDCMD [0:32] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKP) -/*0x2000 73A4 (rpc9_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_CLKP 0x00000007UL - /* RPC_ODT_STATIC_CLKP [0:32] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKN) -/*0x2000 73A0 (rpc8_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_CLKN 0x00000007UL - /* RPC_ODT_STATIC_CLKN [0:32] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_ADDCMD) -/*0x2000 757C (rpc95) */ -#define LIBERO_SETTING_RPC_IBUFMD_ADDCMD 0x00000003UL - /* RPC_IBUFMD_ADDCMD [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_CLK) -/*0x2000 7580 (rpc96) */ -#define LIBERO_SETTING_RPC_IBUFMD_CLK 0x00000004UL - /* RPC_IBUFMD_CLK [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQ) -/*0x2000 7584 (rpc97) */ -#define LIBERO_SETTING_RPC_IBUFMD_DQ 0x00000003UL - /* RPC_IBUFMD_DQ [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQS) -/*0x2000 7588 (rpc98) */ -#define LIBERO_SETTING_RPC_IBUFMD_DQS 0x00000004UL - /* RPC_IBUFMD_DQS [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_RPC_SPARE0_DQ) -/*bits 15:14 connect to pc_ibufmx DQ/DQS/DM bits 13:12 connect to pc_ibufmx -CA/CK Check at ioa pc bit */ -#define LIBERO_SETTING_RPC_SPARE0_DQ 0x00008000UL - /* RPC_SPARE0_DQ [0:32] RW value= 0x8000 */ -#endif -#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10) -/*0x2000 7428 OVRT10 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000000UL - /* RPC_EN_ADDCMD1_OVRT10 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11) -/*0x2000 742C OVRT11 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000120UL - /* RPC_EN_ADDCMD2_OVRT11 [0:32] RW value= 0x120 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_IO_BANK_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_mode.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_mode.h deleted file mode 100644 index 8d191a2..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_mode.h +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_mode.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_mode.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_MODE_H_ -#define HW_DDR_MODE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DDRPHY_MODE) -/*DDRPHY MODE (binary)- 000 ddr3, 001 ddr33L, 010 ddr4, 011 LPDDR3, 100 LPDDR4, -111 OFF_MODE */ -#define LIBERO_SETTING_DDRPHY_MODE 0x00014B04UL - /* DDRMODE [0:3] RW value= 0x4 */ - /* ECC [3:1] RW value= 0x0 */ - /* CRC [4:1] RW value= 0x0 */ - /* BUS_WIDTH [5:3] RW value= 0x0 */ - /* DMI_DBI [8:1] RW value= 0x1 */ - /* DQ_DRIVE [9:2] RW value= 0x1 */ - /* DQS_DRIVE [11:2] RW value= 0x1 */ - /* ADD_CMD_DRIVE [13:2] RW value= 0x2 */ - /* CLOCK_OUT_DRIVE [15:2] RW value= 0x2 */ - /* DQ_TERMINATION [17:2] RW value= 0x0 */ - /* DQS_TERMINATION [19:2] RW value= 0x0 */ - /* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */ - /* PRESET_ODT_CLK [23:2] RW value= 0x0 */ - /* POWER_DOWN [25:1] RW value= 0x0 */ - /* RANK [26:1] RW value= 0x0 */ - /* RESERVED [27:5] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DATA_LANES_USED) -/*number of lanes used for data- does not include ECC, infer from mode register -*/ -#define LIBERO_SETTING_DATA_LANES_USED 0x00000002UL - /* DATA_LANES [0:3] RW value= 0x2 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_MODE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_off_mode.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_off_mode.h deleted file mode 100644 index 3ae39cb..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_off_mode.h +++ /dev/null @@ -1,75 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_off_mode.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_off_mode.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_OFF_MODE_H_ -#define HW_DDR_OFF_MODE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DDRPHY_MODE_OFF) -/*DDRPHY MODE Register, ddr off */ -#define LIBERO_SETTING_DDRPHY_MODE_OFF 0x00000000UL - /* DDRMODE [0:3] RW value= 0x0 */ - /* ECC [3:1] RW value= 0x0 */ - /* CRC [4:1] RW value= 0x0 */ - /* BUS_WIDTH [5:3] RW value= 0x0 */ - /* DMI_DBI [8:1] RW value= 0x0 */ - /* DQ_DRIVE [9:2] RW value= 0x0 */ - /* DQS_DRIVE [11:2] RW value= 0x0 */ - /* ADD_CMD_DRIVE [13:2] RW value= 0x0 */ - /* CLOCK_OUT_DRIVE [15:2] RW value= 0x0 */ - /* DQ_TERMINATION [17:2] RW value= 0x0 */ - /* DQS_TERMINATION [19:2] RW value= 0x0 */ - /* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */ - /* PRESET_ODT_CLK [23:2] RW value= 0x0 */ - /* POWER_DOWN [25:1] RW value= 0x0 */ - /* RANK [26:1] RW value= 0x0 */ - /* RESERVED [27:5] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DPC_BITS_OFF_MODE) -/*DPC Bits Register off mode */ -#define LIBERO_SETTING_DPC_BITS_OFF_MODE 0x00000000UL - /* DPC_VS [0:4] RW value= 0x0 */ - /* DPC_VRGEN_H [4:6] RW value= 0x0 */ - /* DPC_VRGEN_EN_H [10:1] RW value= 0x0 */ - /* DPC_MOVE_EN_H [11:1] RW value= 0x0 */ - /* DPC_VRGEN_V [12:6] RW value= 0x0 */ - /* DPC_VRGEN_EN_V [18:1] RW value= 0x0 */ - /* DPC_MOVE_EN_V [19:1] RW value= 0x0 */ - /* RESERVE01 [20:12] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_OFF_MODE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_options.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_options.h deleted file mode 100644 index 197b954..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_options.h +++ /dev/null @@ -1,79 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_options.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_options.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_OPTIONS_H_ -#define HW_DDR_OPTIONS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING) -/*Tip config: Referenced receivers in the CA bus are turned on for CA training. -These burn static power.(0x01 => turn off ; 0x00 => no action ) */ -#define LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING 0x00000001UL - /* CA_BUS_RX_OFF_POST_TRAINING [0:1] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN) -/*Tip config: 1 => 1 rank, 3 => 2 ranks */ -#define LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN 0x00000001UL - /* USER_INPUT_PHY_RANKS_TO_TRAIN [0:2] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_TRAINING_SKIP_SETTING) -/*Tip config: Pick what trainings we want performed by the TIP, default is 0x1F -*/ -#define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000002UL - /* SKIP_BCLKSCLK_TIP_TRAINING [0:1] RW value= 0x0 */ - /* SKIP_ADDCMD_TIP_TRAINING [1:1] RW value= 0x1 */ - /* SKIP_WRLVL_TIP_TRAINING [2:1] RW value= 0x0 */ - /* SKIP_RDGATE_TIP_TRAINING [3:1] RW value= 0x0 */ - /* SKIP_DQ_DQS_OPT_TIP_TRAINING [4:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_TIP_CFG_PARAMS) -/*Tip config: default: 0x2,0x4,0x0,0x1F,0x1F */ -#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02AUL - /* ADDCMD_OFFSET [0:3] RW value= 0x2 */ - /* BCKLSCLK_OFFSET [3:3] RW value= 0x5 */ - /* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */ - /* READ_GATE_MIN_READS [13:8] RW value= 0x7F */ - /* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET) -/*in simulation we need to set this to 2, for hardware it will be dependent on -the trace lengths */ -#define LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET 0x00000002UL - /* TIP_CONFIG_PARAMS_BCLK_VCOPHS [0:32] RW value= 0x02 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_OPTIONS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_segs.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_segs.h deleted file mode 100644 index 1fd6308..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddr_segs.h +++ /dev/null @@ -1,155 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_segs.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_segs.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_SEGS_H_ -#define HW_DDR_SEGS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SEG0_0) -/*Cached access at 0x00_8000_0000 (-0x80+0x00) */ -#define LIBERO_SETTING_SEG0_0 0x00007F80UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7F80 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_1) -/*Cached access at 0x10_0000_000 */ -#define LIBERO_SETTING_SEG0_1 0x00007000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7000 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_2) -/*not used */ -#define LIBERO_SETTING_SEG0_2 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_3) -/*not used */ -#define LIBERO_SETTING_SEG0_3 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_4) -/*not used */ -#define LIBERO_SETTING_SEG0_4 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_5) -/*not used */ -#define LIBERO_SETTING_SEG0_5 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:6] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_6) -/*not used */ -#define LIBERO_SETTING_SEG0_6 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_7) -/*not used */ -#define LIBERO_SETTING_SEG0_7 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_0) -/*not used */ -#define LIBERO_SETTING_SEG1_0 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_1) -/*not used */ -#define LIBERO_SETTING_SEG1_1 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_2) -/*Non-Cached access at 0x00_c000_0000 */ -#define LIBERO_SETTING_SEG1_2 0x00007F40UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7F40 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_3) -/*Non-Cached access at 0x14_0000_0000 */ -#define LIBERO_SETTING_SEG1_3 0x00006C00UL - /* ADDRESS_OFFSET [0:15] RW value= 0x6C00 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_4) -/*Non-Cached WCB access at 0x00_d000_0000 */ -#define LIBERO_SETTING_SEG1_4 0x00007F30UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7F30 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_5) -/*Non-Cached WCB 0x18_0000_0000 */ -#define LIBERO_SETTING_SEG1_5 0x00006800UL - /* ADDRESS_OFFSET [0:15] RW value= 0x6800 */ - /* RESERVED [15:6] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_6) -/*Trace - Trace not in use here so can be left as 0 */ -#define LIBERO_SETTING_SEG1_6 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_7) -/*not used */ -#define LIBERO_SETTING_SEG1_7 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_SEGS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddrc.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddrc.h deleted file mode 100644 index 38f0e2a..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/ddr/hw_ddrc.h +++ /dev/null @@ -1,1888 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddrc.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddrc.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDRC_H_ -#define HW_DDRC_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP 0x00000000UL - /* CFG_MANUAL_ADDRESS_MAP [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CHIPADDR_MAP) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_CHIPADDR_MAP 0x0000001DUL - /* CFG_CHIPADDR_MAP [0:32] RW value= 0x00001D */ -#endif -#if !defined (LIBERO_SETTING_CFG_CIDADDR_MAP) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_CIDADDR_MAP 0x00000000UL - /* CFG_CIDADDR_MAP [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW 0x00000004UL - /* CFG_MB_AUTOPCH_COL_BIT_POS_LOW [0:32] RW value= 0x00000004 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH 0x0000000AUL - /* CFG_MB_AUTOPCH_COL_BIT_POS_HIGH [0:32] RW value= 0x0000000A */ -#endif -#if !defined (LIBERO_SETTING_CFG_BANKADDR_MAP_0) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_BANKADDR_MAP_0 0x0000C2CAUL - /* CFG_BANKADDR_MAP_0 [0:32] RW value= 0x00C2CA */ -#endif -#if !defined (LIBERO_SETTING_CFG_BANKADDR_MAP_1) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_BANKADDR_MAP_1 0x00000000UL - /* CFG_BANKADDR_MAP_1 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_0) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_0 0x9140F38DUL - /* CFG_ROWADDR_MAP_0 [0:32] RW value= 0x9140F38D */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_1) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_1 0x75955134UL - /* CFG_ROWADDR_MAP_1 [0:32] RW value= 0x75955134 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_2) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_2 0x71B69961UL - /* CFG_ROWADDR_MAP_2 [0:32] RW value= 0x71B69961 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_3) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_3 0x00000000UL - /* CFG_ROWADDR_MAP_3 [0:32] RW value= 0x000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_0) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_COLADDR_MAP_0 0x440C2040UL - /* CFG_COLADDR_MAP_0 [0:32] RW value= 0x440C2040 */ -#endif -#if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_1) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_COLADDR_MAP_1 0x02481C61UL - /* CFG_COLADDR_MAP_1 [0:32] RW value= 0x02481C61 */ -#endif -#if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_2) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_COLADDR_MAP_2 0x00000000UL - /* CFG_COLADDR_MAP_2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VRCG_ENABLE) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_VRCG_ENABLE 0x00000140UL - /* CFG_VRCG_ENABLE [0:32] RW value= 0x00000140 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VRCG_DISABLE) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_VRCG_DISABLE 0x000000A0UL - /* CFG_VRCG_DISABLE [0:32] RW value= 0x000000A0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_LATENCY_SET) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_LATENCY_SET 0x00000000UL - /* CFG_WRITE_LATENCY_SET [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_THERMAL_OFFSET) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_THERMAL_OFFSET 0x00000000UL - /* CFG_THERMAL_OFFSET [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_SOC_ODT) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_SOC_ODT 0x00000006UL - /* CFG_SOC_ODT [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODTE_CK) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_ODTE_CK 0x00000000UL - /* CFG_ODTE_CK [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODTE_CS) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_ODTE_CS 0x00000000UL - /* CFG_ODTE_CS [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODTD_CA) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_ODTD_CA 0x00000000UL - /* CFG_ODTD_CA [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LPDDR4_FSP_OP) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_LPDDR4_FSP_OP 0x00000001UL - /* CFG_LPDDR4_FSP_OP [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX 0x00000001UL - /* CFG_GENERATE_REFRESH_ON_SRX [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DBI_CL) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_DBI_CL 0x00000016UL - /* CFG_DBI_CL [0:32] RW value= 0x00000016 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NON_DBI_CL) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_NON_DBI_CL 0x00000016UL - /* CFG_NON_DBI_CL [0:32] RW value= 0x00000016 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0 0x00000000UL - /* INIT_FORCE_WRITE_DATA_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_CRC) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_CRC 0x00000000UL - /* CFG_WRITE_CRC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MPR_READ_FORMAT) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_MPR_READ_FORMAT 0x00000000UL - /* CFG_MPR_READ_FORMAT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM 0x00000000UL - /* CFG_WR_CMD_LAT_CRC_DM [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE 0x00000000UL - /* CFG_FINE_GRAN_REF_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT 0x00000000UL - /* CFG_TEMP_SENSOR_READOUT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN 0x00000000UL - /* CFG_PER_DRAM_ADDR_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_GEARDOWN_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_GEARDOWN_MODE 0x00000000UL - /* CFG_GEARDOWN_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_PREAMBLE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WR_PREAMBLE 0x00000001UL - /* CFG_WR_PREAMBLE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_PREAMBLE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RD_PREAMBLE 0x00000000UL - /* CFG_RD_PREAMBLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE 0x00000000UL - /* CFG_RD_PREAMB_TRN_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_SR_ABORT) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_SR_ABORT 0x00000000UL - /* CFG_SR_ABORT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY 0x00000000UL - /* CFG_CS_TO_CMDADDR_LATENCY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_INT_VREF_MON) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_INT_VREF_MON 0x00000000UL - /* CFG_INT_VREF_MON [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE 0x00000000UL - /* CFG_TEMP_CTRL_REF_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE 0x00000000UL - /* CFG_TEMP_CTRL_REF_RANGE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE 0x00000000UL - /* CFG_MAX_PWR_DOWN_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_DBI) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_READ_DBI 0x00000000UL - /* CFG_READ_DBI [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_DBI) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_DBI 0x00000000UL - /* CFG_WRITE_DBI [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DATA_MASK) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_DATA_MASK 0x00000001UL - /* CFG_DATA_MASK [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR 0x00000000UL - /* CFG_CA_PARITY_PERSIST_ERR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTT_PARK) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RTT_PARK 0x00000000UL - /* CFG_RTT_PARK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_INBUF_4_PD) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_INBUF_4_PD 0x00000000UL - /* CFG_ODT_INBUF_4_PD [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS 0x00000000UL - /* CFG_CA_PARITY_ERR_STATUS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CRC_ERROR_CLEAR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CRC_ERROR_CLEAR 0x00000000UL - /* CFG_CRC_ERROR_CLEAR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_PARITY_LATENCY) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CA_PARITY_LATENCY 0x00000000UL - /* CFG_CA_PARITY_LATENCY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CCD_S) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CCD_S 0x00000005UL - /* CFG_CCD_S [0:32] RW value= 0x00000005 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CCD_L) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CCD_L 0x00000006UL - /* CFG_CCD_L [0:32] RW value= 0x00000006 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE 0x00000000UL - /* CFG_VREFDQ_TRN_ENABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE 0x00000000UL - /* CFG_VREFDQ_TRN_RANGE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE 0x00000000UL - /* CFG_VREFDQ_TRN_VALUE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD_S) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RRD_S 0x00000004UL - /* CFG_RRD_S [0:32] RW value= 0x00000004 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD_L) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RRD_L 0x00000003UL - /* CFG_RRD_L [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_S) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_S 0x00000003UL - /* CFG_WTR_S [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_L) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_L 0x00000003UL - /* CFG_WTR_L [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_S_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_S_CRC_DM 0x00000003UL - /* CFG_WTR_S_CRC_DM [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_L_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_L_CRC_DM 0x00000003UL - /* CFG_WTR_L_CRC_DM [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WR_CRC_DM 0x00000006UL - /* CFG_WR_CRC_DM [0:32] RW value= 0x00000006 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC1 0x00000036UL - /* CFG_RFC1 [0:32] RW value= 0x00000036 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC2) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC2 0x00000036UL - /* CFG_RFC2 [0:32] RW value= 0x00000036 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC4) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC4 0x00000036UL - /* CFG_RFC4 [0:32] RW value= 0x00000036 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NIBBLE_DEVICES) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_NIBBLE_DEVICES 0x00000000UL - /* CFG_NIBBLE_DEVICES [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0 0x81881881UL - /* CFG_BIT_MAP_INDEX_CS0_0 [0:32] RW value= 0x81881881 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1 0x00008818UL - /* CFG_BIT_MAP_INDEX_CS0_1 [0:32] RW value= 0x00008818 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0 0xA92A92A9UL - /* CFG_BIT_MAP_INDEX_CS1_0 [0:32] RW value= 0xa92a92a9 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1 0x00002A92UL - /* CFG_BIT_MAP_INDEX_CS1_1 [0:32] RW value= 0x00002a92 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0 0xC28C28C2UL - /* CFG_BIT_MAP_INDEX_CS2_0 [0:32] RW value= 0xc28c28c2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1 0x00008C28UL - /* CFG_BIT_MAP_INDEX_CS2_1 [0:32] RW value= 0x00008c28 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0 0xEA2EA2EAUL - /* CFG_BIT_MAP_INDEX_CS3_0 [0:32] RW value= 0xea2ea2ea */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1 0x00002EA2UL - /* CFG_BIT_MAP_INDEX_CS3_1 [0:32] RW value= 0x00002ea2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0 0x03903903UL - /* CFG_BIT_MAP_INDEX_CS4_0 [0:32] RW value= 0x03903903 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1 0x00009039UL - /* CFG_BIT_MAP_INDEX_CS4_1 [0:32] RW value= 0x00009039 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0 0x2B32B32BUL - /* CFG_BIT_MAP_INDEX_CS5_0 [0:32] RW value= 0x2b32b32b */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1 0x000032B3UL - /* CFG_BIT_MAP_INDEX_CS5_1 [0:32] RW value= 0x000032b3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0 0x44944944UL - /* CFG_BIT_MAP_INDEX_CS6_0 [0:32] RW value= 0x44944944 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1 0x00009449UL - /* CFG_BIT_MAP_INDEX_CS6_1 [0:32] RW value= 0x00009449 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0 0x6C36C36CUL - /* CFG_BIT_MAP_INDEX_CS7_0 [0:32] RW value= 0x6c36c36c */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1 0x000036C3UL - /* CFG_BIT_MAP_INDEX_CS7_1 [0:32] RW value= 0x000036c3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0 0x85985985UL - /* CFG_BIT_MAP_INDEX_CS8_0 [0:32] RW value= 0x85985985 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1 0x00009859UL - /* CFG_BIT_MAP_INDEX_CS8_1 [0:32] RW value= 0x00009859 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0 0xAD3AD3ADUL - /* CFG_BIT_MAP_INDEX_CS9_0 [0:32] RW value= 0xad3ad3ad */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1 0x00003AD3UL - /* CFG_BIT_MAP_INDEX_CS9_1 [0:32] RW value= 0x00003ad3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0 0xC69C69C6UL - /* CFG_BIT_MAP_INDEX_CS10_0 [0:32] RW value= 0xc69c69c6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1 0x00009C69UL - /* CFG_BIT_MAP_INDEX_CS10_1 [0:32] RW value= 0x00009c69 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0 0xEE3EE3EEUL - /* CFG_BIT_MAP_INDEX_CS11_0 [0:32] RW value= 0xee3ee3ee */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1 0x00003EE3UL - /* CFG_BIT_MAP_INDEX_CS11_1 [0:32] RW value= 0x00003ee3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0 0x07A07A07UL - /* CFG_BIT_MAP_INDEX_CS12_0 [0:32] RW value= 0x07a07a07 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1 0x0000A07AUL - /* CFG_BIT_MAP_INDEX_CS12_1 [0:32] RW value= 0x0000a07a */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0 0x2F42F42FUL - /* CFG_BIT_MAP_INDEX_CS13_0 [0:32] RW value= 0x2f42f42f */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1 0x000042F4UL - /* CFG_BIT_MAP_INDEX_CS13_1 [0:32] RW value= 0x000042f4 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0 0x48A48A48UL - /* CFG_BIT_MAP_INDEX_CS14_0 [0:32] RW value= 0x48a48a48 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1 0x0000A48AUL - /* CFG_BIT_MAP_INDEX_CS14_1 [0:32] RW value= 0x0000a48a */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0 0x70470470UL - /* CFG_BIT_MAP_INDEX_CS15_0 [0:32] RW value= 0x70470470 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1 0x00004704UL - /* CFG_BIT_MAP_INDEX_CS15_1 [0:32] RW value= 0x00004704 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS 0x00000000UL - /* CFG_NUM_LOGICAL_RANKS_PER_3DS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC_DLR1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC_DLR1 0x00000048UL - /* CFG_RFC_DLR1 [0:32] RW value= 0x00000048 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC_DLR2) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC_DLR2 0x0000002CUL - /* CFG_RFC_DLR2 [0:32] RW value= 0x0000002C */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC_DLR4) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC_DLR4 0x00000020UL - /* CFG_RFC_DLR4 [0:32] RW value= 0x00000020 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD_DLR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RRD_DLR 0x00000004UL - /* CFG_RRD_DLR [0:32] RW value= 0x00000004 */ -#endif -#if !defined (LIBERO_SETTING_CFG_FAW_DLR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_FAW_DLR 0x00000010UL - /* CFG_FAW_DLR [0:32] RW value= 0x00000010 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY 0x00000000UL - /* CFG_ADVANCE_ACTIVATE_READY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CTRLR_SOFT_RESET_N) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CTRLR_SOFT_RESET_N 0x00000001UL - /* CTRLR_SOFT_RESET_N [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LOOKAHEAD_PCH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LOOKAHEAD_PCH 0x00000000UL - /* CFG_LOOKAHEAD_PCH [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LOOKAHEAD_ACT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LOOKAHEAD_ACT 0x00000000UL - /* CFG_LOOKAHEAD_ACT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_INIT_AUTOINIT_DISABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_AUTOINIT_DISABLE 0x00000000UL - /* INIT_AUTOINIT_DISABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_RESET) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_RESET 0x00000000UL - /* INIT_FORCE_RESET [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_GEARDOWN_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_GEARDOWN_EN 0x00000000UL - /* INIT_GEARDOWN_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DISABLE_CKE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_DISABLE_CKE 0x00000000UL - /* INIT_DISABLE_CKE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CS 0x00000000UL - /* INIT_CS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_PRECHARGE_ALL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_PRECHARGE_ALL 0x00000000UL - /* INIT_PRECHARGE_ALL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_REFRESH 0x00000000UL - /* INIT_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ZQ_CAL_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ZQ_CAL_REQ 0x00000000UL - /* INIT_ZQ_CAL_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BL 0x00000000UL - /* CFG_BL [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CTRLR_INIT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CTRLR_INIT 0x00000000UL - /* CTRLR_INIT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AUTO_REF_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AUTO_REF_EN 0x00000001UL - /* CFG_AUTO_REF_EN [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RAS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RAS 0x00000022UL - /* CFG_RAS [0:32] RW value= 0x22 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RCD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RCD 0x0000000FUL - /* CFG_RCD [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RRD 0x00000008UL - /* CFG_RRD [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RP 0x00000011UL - /* CFG_RP [0:32] RW value= 0x11 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RC 0x00000033UL - /* CFG_RC [0:32] RW value= 0x33 */ -#endif -#if !defined (LIBERO_SETTING_CFG_FAW) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_FAW 0x00000020UL - /* CFG_FAW [0:32] RW value= 0x20 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RFC 0x00000130UL - /* CFG_RFC [0:32] RW value= 0x130 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RTP 0x00000008UL - /* CFG_RTP [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WR 0x00000010UL - /* CFG_WR [0:32] RW value= 0x10 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WTR 0x00000008UL - /* CFG_WTR [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PASR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PASR 0x00000000UL - /* CFG_PASR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XP 0x00000006UL - /* CFG_XP [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XSR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XSR 0x0000001FUL - /* CFG_XSR [0:32] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CFG_CL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CL 0x00000005UL - /* CFG_CL [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_WRITE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_WRITE 0x0000000FUL - /* CFG_READ_TO_WRITE [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_WRITE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_WRITE 0x0000000FUL - /* CFG_WRITE_TO_WRITE [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_READ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_READ 0x0000000FUL - /* CFG_READ_TO_READ [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_READ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_READ 0x0000001FUL - /* CFG_WRITE_TO_READ [0:32] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_WRITE_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_WRITE_ODT 0x00000001UL - /* CFG_READ_TO_WRITE_ODT [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT 0x00000000UL - /* CFG_WRITE_TO_WRITE_ODT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_READ_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_READ_ODT 0x00000001UL - /* CFG_READ_TO_READ_ODT [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_READ_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_READ_ODT 0x00000001UL - /* CFG_WRITE_TO_READ_ODT [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MIN_READ_IDLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MIN_READ_IDLE 0x00000001UL - /* CFG_MIN_READ_IDLE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRD 0x0000000CUL - /* CFG_MRD [0:32] RW value= 0xC */ -#endif -#if !defined (LIBERO_SETTING_CFG_BT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BT 0x00000000UL - /* CFG_BT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DS 0x00000006UL - /* CFG_DS [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_QOFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_QOFF 0x00000000UL - /* CFG_QOFF [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RTT 0x00000002UL - /* CFG_RTT [0:32] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DLL_DISABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DLL_DISABLE 0x00000000UL - /* CFG_DLL_DISABLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REF_PER) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_REF_PER 0x00000C34UL - /* CFG_REF_PER [0:32] RW value= 0xC34 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARTUP_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_STARTUP_DELAY 0x00027100UL - /* CFG_STARTUP_DELAY [0:32] RW value= 0x27100 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_COLBITS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEM_COLBITS 0x0000000AUL - /* CFG_MEM_COLBITS [0:32] RW value= 0xA */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_ROWBITS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEM_ROWBITS 0x00000010UL - /* CFG_MEM_ROWBITS [0:32] RW value= 0x10 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_BANKBITS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEM_BANKBITS 0x00000003UL - /* CFG_MEM_BANKBITS [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS0) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS0 0x00000000UL - /* CFG_ODT_RD_MAP_CS0 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS1 0x00000000UL - /* CFG_ODT_RD_MAP_CS1 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS2) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS2 0x00000000UL - /* CFG_ODT_RD_MAP_CS2 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS3) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS3 0x00000000UL - /* CFG_ODT_RD_MAP_CS3 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS4) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS4 0x00000000UL - /* CFG_ODT_RD_MAP_CS4 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS5) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS5 0x00000000UL - /* CFG_ODT_RD_MAP_CS5 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS6) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS6 0x00000000UL - /* CFG_ODT_RD_MAP_CS6 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS7) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS7 0x00000000UL - /* CFG_ODT_RD_MAP_CS7 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS0) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS0 0x00000000UL - /* CFG_ODT_WR_MAP_CS0 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS1 0x00000000UL - /* CFG_ODT_WR_MAP_CS1 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS2) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS2 0x00000000UL - /* CFG_ODT_WR_MAP_CS2 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS3) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS3 0x00000000UL - /* CFG_ODT_WR_MAP_CS3 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS4) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS4 0x00000000UL - /* CFG_ODT_WR_MAP_CS4 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS5) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS5 0x00000000UL - /* CFG_ODT_WR_MAP_CS5 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS6) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS6 0x00000000UL - /* CFG_ODT_WR_MAP_CS6 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS7) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS7 0x00000000UL - /* CFG_ODT_WR_MAP_CS7 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_TURN_ON) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_TURN_ON 0x00000000UL - /* CFG_ODT_RD_TURN_ON [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_TURN_ON) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_TURN_ON 0x00000000UL - /* CFG_ODT_WR_TURN_ON [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_TURN_OFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_TURN_OFF 0x00000000UL - /* CFG_ODT_RD_TURN_OFF [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_TURN_OFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_TURN_OFF 0x00000000UL - /* CFG_ODT_WR_TURN_OFF [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EMR3) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_EMR3 0x00000000UL - /* CFG_EMR3 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TWO_T) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_TWO_T 0x00000000UL - /* CFG_TWO_T [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE 0x00000001UL - /* CFG_TWO_T_SEL_CYCLE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REGDIMM) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_REGDIMM 0x00000000UL - /* CFG_REGDIMM [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MOD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MOD 0x0000000CUL - /* CFG_MOD [0:32] RW value= 0xC */ -#endif -#if !defined (LIBERO_SETTING_CFG_XS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XS 0x00000005UL - /* CFG_XS [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XSDLL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XSDLL 0x00000200UL - /* CFG_XSDLL [0:32] RW value= 0x00000200 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XPR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XPR 0x00000005UL - /* CFG_XPR [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AL_MODE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AL_MODE 0x00000000UL - /* CFG_AL_MODE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CWL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CWL 0x00000005UL - /* CFG_CWL [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BL_MODE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BL_MODE 0x00000000UL - /* CFG_BL_MODE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TDQS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_TDQS 0x00000000UL - /* CFG_TDQS [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTT_WR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RTT_WR 0x00000000UL - /* CFG_RTT_WR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LP_ASR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LP_ASR 0x00000000UL - /* CFG_LP_ASR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AUTO_SR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AUTO_SR 0x00000000UL - /* CFG_AUTO_SR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_SRT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_SRT 0x00000000UL - /* CFG_SRT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ADDR_MIRROR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ADDR_MIRROR 0x00000000UL - /* CFG_ADDR_MIRROR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_TYPE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_TYPE 0x00000001UL - /* CFG_ZQ_CAL_TYPE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_PER) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_PER 0x00027100UL - /* CFG_ZQ_CAL_PER [0:32] RW value= 0x27100 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN 0x00000000UL - /* CFG_AUTO_ZQ_CAL_EN [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEMORY_TYPE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEMORY_TYPE 0x00000400UL - /* CFG_MEMORY_TYPE [0:32] RW value= 0x400 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ONLY_SRANK_CMDS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ONLY_SRANK_CMDS 0x00000000UL - /* CFG_ONLY_SRANK_CMDS [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NUM_RANKS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_NUM_RANKS 0x00000001UL - /* CFG_NUM_RANKS [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_QUAD_RANK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_QUAD_RANK 0x00000000UL - /* CFG_QUAD_RANK [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START 0x00000000UL - /* CFG_EARLY_RANK_TO_WR_START [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START 0x00000000UL - /* CFG_EARLY_RANK_TO_RD_START [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PASR_BANK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PASR_BANK 0x00000000UL - /* CFG_PASR_BANK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PASR_SEG) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PASR_SEG 0x00000000UL - /* CFG_PASR_SEG [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MRR_MODE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MRR_MODE 0x00000000UL - /* INIT_MRR_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_W_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_W_REQ 0x00000000UL - /* INIT_MR_W_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_ADDR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_ADDR 0x00000000UL - /* INIT_MR_ADDR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_WR_DATA) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_WR_DATA 0x00000000UL - /* INIT_MR_WR_DATA [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_WR_MASK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_WR_MASK 0x00000000UL - /* INIT_MR_WR_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_NOP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_NOP 0x00000000UL - /* INIT_NOP [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_INIT_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_INIT_DURATION 0x00000640UL - /* CFG_INIT_DURATION [0:32] RW value= 0x640 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION 0x00000000UL - /* CFG_ZQINIT_CAL_DURATION [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION 0x00000000UL - /* CFG_ZQ_CAL_L_DURATION [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION 0x00000000UL - /* CFG_ZQ_CAL_S_DURATION [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION 0x00000028UL - /* CFG_ZQ_CAL_R_DURATION [0:32] RW value= 0x28 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRR 0x00000008UL - /* CFG_MRR [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRW) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRW 0x0000000AUL - /* CFG_MRW [0:32] RW value= 0xA */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_POWERDOWN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_POWERDOWN 0x00000000UL - /* CFG_ODT_POWERDOWN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WL 0x00000008UL - /* CFG_WL [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RL 0x0000000EUL - /* CFG_RL [0:32] RW value= 0xE */ -#endif -#if !defined (LIBERO_SETTING_CFG_CAL_READ_PERIOD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CAL_READ_PERIOD 0x00000000UL - /* CFG_CAL_READ_PERIOD [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NUM_CAL_READS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_NUM_CAL_READS 0x00000001UL - /* CFG_NUM_CAL_READS [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_INIT_SELF_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_SELF_REFRESH 0x00000000UL - /* INIT_SELF_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_POWER_DOWN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_POWER_DOWN 0x00000000UL - /* INIT_POWER_DOWN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_WRITE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_WRITE 0x00000000UL - /* INIT_FORCE_WRITE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_WRITE_CS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_WRITE_CS 0x00000000UL - /* INIT_FORCE_WRITE_CS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE 0x00000000UL - /* CFG_CTRLR_INIT_DISABLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_INIT_RDIMM_COMPLETE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_RDIMM_COMPLETE 0x00000000UL - /* INIT_RDIMM_COMPLETE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RDIMM_LAT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RDIMM_LAT 0x00000000UL - /* CFG_RDIMM_LAT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT 0x00000001UL - /* CFG_RDIMM_BSIDE_INVERT [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LRDIMM) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LRDIMM 0x00000000UL - /* CFG_LRDIMM [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MEMORY_RESET_MASK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MEMORY_RESET_MASK 0x00000000UL - /* INIT_MEMORY_RESET_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE 0x00000000UL - /* CFG_RD_PREAMB_TOGGLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_POSTAMBLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RD_POSTAMBLE 0x00000000UL - /* CFG_RD_POSTAMBLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PU_CAL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PU_CAL 0x00000001UL - /* CFG_PU_CAL [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DQ_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DQ_ODT 0x00000002UL - /* CFG_DQ_ODT [0:32] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CA_ODT 0x00000004UL - /* CFG_CA_ODT [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQLATCH_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQLATCH_DURATION 0x00000018UL - /* CFG_ZQLATCH_DURATION [0:32] RW value= 0x18 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_SELECT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_SELECT 0x00000000UL - /* INIT_CAL_SELECT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_R_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_R_REQ 0x00000000UL - /* INIT_CAL_L_R_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_B_SIZE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_B_SIZE 0x00000000UL - /* INIT_CAL_L_B_SIZE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_RWFIFO) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_RWFIFO 0x00000000UL - /* INIT_RWFIFO [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_RD_DQCAL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_RD_DQCAL 0x00000000UL - /* INIT_RD_DQCAL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_START_DQSOSC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_START_DQSOSC 0x00000000UL - /* INIT_START_DQSOSC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_STOP_DQSOSC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_STOP_DQSOSC 0x00000000UL - /* INIT_STOP_DQSOSC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ZQ_CAL_START) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ZQ_CAL_START 0x00000000UL - /* INIT_ZQ_CAL_START [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_POSTAMBLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WR_POSTAMBLE 0x00000000UL - /* CFG_WR_POSTAMBLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_ADDR_0) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_ADDR_0 0x00000000UL - /* INIT_CAL_L_ADDR_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_ADDR_1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_ADDR_1 0x00000000UL - /* INIT_CAL_L_ADDR_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLUPD_TRIG) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLUPD_TRIG 0x00000000UL - /* CFG_CTRLUPD_TRIG [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLUPD_START_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLUPD_START_DELAY 0x00000000UL - /* CFG_CTRLUPD_START_DELAY [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX 0x00000000UL - /* CFG_DFI_T_CTRLUPD_MAX [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_SEL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_SEL 0x00000000UL - /* CFG_CTRLR_BUSY_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE 0x00000000UL - /* CFG_CTRLR_BUSY_VALUE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY 0x00000000UL - /* CFG_CTRLR_BUSY_TURN_OFF_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW 0x00000000UL - /* CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF 0x00000000UL - /* CFG_CTRLR_BUSY_RESTART_HOLDOFF [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY 0x00000000UL - /* CFG_PARITY_RDIMM_DELAY [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE 0x00000000UL - /* CFG_CTRLR_BUSY_ENABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ASYNC_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ASYNC_ODT 0x00000000UL - /* CFG_ASYNC_ODT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_DURATION 0x00000320UL - /* CFG_ZQ_CAL_DURATION [0:32] RW value= 0x320 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRRI) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRRI 0x00000012UL - /* CFG_MRRI [0:32] RW value= 0x12 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ODT_FORCE_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ODT_FORCE_EN 0x00000000UL - /* INIT_ODT_FORCE_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ODT_FORCE_RANK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ODT_FORCE_RANK 0x00000000UL - /* INIT_ODT_FORCE_RANK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY 0x00000000UL - /* CFG_PHYUPD_ACK_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1 0x00000000UL - /* CFG_MIRROR_X16_BG0_BG1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_PDA_MR_W_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_PDA_MR_W_REQ 0x00000000UL - /* INIT_PDA_MR_W_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT 0x00000000UL - /* INIT_PDA_NIBBLE_SELECT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH 0x00000000UL - /* CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CKSRE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CKSRE 0x00000008UL - /* CFG_CKSRE [0:32] RW value= 0x00000008 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CKSRX) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CKSRX 0x0000000BUL - /* CFG_CKSRX [0:32] RW value= 0x0000000b */ -#endif -#if !defined (LIBERO_SETTING_CFG_RCD_STAB) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RCD_STAB 0x00000000UL - /* CFG_RCD_STAB [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY 0x00000000UL - /* CFG_DFI_T_CTRL_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE 0x00000000UL - /* CFG_DFI_T_DRAM_CLK_ENABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH 0x00000000UL - /* CFG_IDLE_TIME_TO_SELF_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN 0x00000000UL - /* CFG_IDLE_TIME_TO_POWER_DOWN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF 0x00000000UL - /* CFG_BURST_RW_REFRESH_HOLDOFF [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BG_INTERLEAVE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BG_INTERLEAVE 0x00000001UL - /* CFG_BG_INTERLEAVE [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING 0x00000000UL - /* CFG_REFRESH_DURING_PHY_TRAINING [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0 0x00000000UL - /* CFG_STARVE_TIMEOUT_P0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1 0x00000000UL - /* CFG_STARVE_TIMEOUT_P1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2 0x00000000UL - /* CFG_STARVE_TIMEOUT_P2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3 0x00000000UL - /* CFG_STARVE_TIMEOUT_P3 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4 0x00000000UL - /* CFG_STARVE_TIMEOUT_P4 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5 0x00000000UL - /* CFG_STARVE_TIMEOUT_P5 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6 0x00000000UL - /* CFG_STARVE_TIMEOUT_P6 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7 0x00000000UL - /* CFG_STARVE_TIMEOUT_P7 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REORDER_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_REORDER_EN 0x00000001UL - /* CFG_REORDER_EN [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REORDER_QUEUE_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_REORDER_QUEUE_EN 0x00000001UL - /* CFG_REORDER_QUEUE_EN [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN 0x00000000UL - /* CFG_INTRAPORT_REORDER_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MAINTAIN_COHERENCY) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_MAINTAIN_COHERENCY 0x00000001UL - /* CFG_MAINTAIN_COHERENCY [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_Q_AGE_LIMIT) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_Q_AGE_LIMIT 0x000000FFUL - /* CFG_Q_AGE_LIMIT [0:32] RW value= 0x000000FF */ -#endif -#if !defined (LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY 0x00000000UL - /* CFG_RO_CLOSED_PAGE_POLICY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REORDER_RW_ONLY) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_REORDER_RW_ONLY 0x00000000UL - /* CFG_REORDER_RW_ONLY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RO_PRIORITY_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_RO_PRIORITY_EN 0x00000000UL - /* CFG_RO_PRIORITY_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DM_EN) -/*IP Blk = RMW Access=RW */ -#define LIBERO_SETTING_CFG_DM_EN 0x00000001UL - /* CFG_DM_EN [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RMW_EN) -/*IP Blk = RMW Access=RW */ -#define LIBERO_SETTING_CFG_RMW_EN 0x00000000UL - /* CFG_RMW_EN [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ECC_CORRECTION_EN) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_CFG_ECC_CORRECTION_EN 0x00000000UL - /* CFG_ECC_CORRECTION_EN [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ECC_BYPASS) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_CFG_ECC_BYPASS 0x00000000UL - /* CFG_ECC_BYPASS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN 0x00000000UL - /* INIT_WRITE_DATA_1B_ECC_ERROR_GEN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN 0x00000000UL - /* INIT_WRITE_DATA_2B_ECC_ERROR_GEN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH 0x00000000UL - /* CFG_ECC_1BIT_INT_THRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_READ_CAPTURE_ADDR) -/*IP Blk = READ_CAPT Access=RW */ -#define LIBERO_SETTING_INIT_READ_CAPTURE_ADDR 0x00000000UL - /* INIT_READ_CAPTURE_ADDR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ERROR_GROUP_SEL) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_ERROR_GROUP_SEL 0x00000000UL - /* CFG_ERROR_GROUP_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DATA_SEL) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_DATA_SEL 0x00000000UL - /* CFG_DATA_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MODE) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MODE 0x00000000UL - /* CFG_TRIG_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_POST_TRIG_CYCS) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_POST_TRIG_CYCS 0x00000000UL - /* CFG_POST_TRIG_CYCS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MASK) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MASK 0x00000000UL - /* CFG_TRIG_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EN_MASK) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_EN_MASK 0x00000000UL - /* CFG_EN_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_ADDR) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_ADDR 0x00000000UL - /* MTC_ACQ_ADDR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MT_ADDR_0) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MT_ADDR_0 0x00000000UL - /* CFG_TRIG_MT_ADDR_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MT_ADDR_1) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MT_ADDR_1 0x00000000UL - /* CFG_TRIG_MT_ADDR_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_0) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_0 0x00000000UL - /* CFG_TRIG_ERR_MASK_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_1) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_1 0x00000000UL - /* CFG_TRIG_ERR_MASK_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_2) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_2 0x00000000UL - /* CFG_TRIG_ERR_MASK_2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_3) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_3 0x00000000UL - /* CFG_TRIG_ERR_MASK_3 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_4) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_4 0x00000000UL - /* CFG_TRIG_ERR_MASK_4 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_0) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_WR_DATA_0 0x00000000UL - /* MTC_ACQ_WR_DATA_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_1) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_WR_DATA_1 0x00000000UL - /* MTC_ACQ_WR_DATA_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_2) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_WR_DATA_2 0x00000000UL - /* MTC_ACQ_WR_DATA_2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PRE_TRIG_CYCS) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_PRE_TRIG_CYCS 0x00000000UL - /* CFG_PRE_TRIG_CYCS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR 0x00000000UL - /* CFG_DATA_SEL_FIRST_ERROR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DQ_WIDTH) -/*IP Blk = DYN_WIDTH_ADJ Access=RW */ -#define LIBERO_SETTING_CFG_DQ_WIDTH 0x00000001UL - /* CFG_DQ_WIDTH [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ACTIVE_DQ_SEL) -/*IP Blk = DYN_WIDTH_ADJ Access=RW */ -#define LIBERO_SETTING_CFG_ACTIVE_DQ_SEL 0x00000000UL - /* CFG_ACTIVE_DQ_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ) -/*IP Blk = CA_PAR_ERR Access=RW */ -#define LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ 0x00000000UL - /* INIT_CA_PARITY_ERROR_GEN_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD) -/*IP Blk = CA_PAR_ERR Access=RW */ -#define LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD 0x00000000UL - /* INIT_CA_PARITY_ERROR_GEN_CMD [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_RDDATA_EN) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_RDDATA_EN 0x00000015UL - /* CFG_DFI_T_RDDATA_EN [0:32] RW value= 0x15 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT 0x00000006UL - /* CFG_DFI_T_PHY_RDLAT [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT 0x00000003UL - /* CFG_DFI_T_PHY_WRLAT [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_PHYUPD_EN) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_PHYUPD_EN 0x00000001UL - /* CFG_DFI_PHYUPD_EN [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_LP_DATA_REQ) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_LP_DATA_REQ 0x00000000UL - /* INIT_DFI_LP_DATA_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ 0x00000000UL - /* INIT_DFI_LP_CTRL_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_LP_WAKEUP) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_LP_WAKEUP 0x00000000UL - /* INIT_DFI_LP_WAKEUP [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE 0x00000000UL - /* INIT_DFI_DRAM_CLK_DISABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE 0x00000000UL - /* CFG_DFI_DATA_BYTE_DISABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_LVL_SEL) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_LVL_SEL 0x00000000UL - /* CFG_DFI_LVL_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_LVL_PERIODIC) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_LVL_PERIODIC 0x00000000UL - /* CFG_DFI_LVL_PERIODIC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_LVL_PATTERN) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_LVL_PATTERN 0x00000000UL - /* CFG_DFI_LVL_PATTERN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_DFI_INIT_START) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_PHY_DFI_INIT_START 0x00000001UL - /* PHY_DFI_INIT_START [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI1_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI1_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI2_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI2_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0 0xFFFFFFFFUL - /* CFG_AXI_END_ADDRESS_AXI1_0 [0:32] RW value= 0xFFFFFFFF */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1 0x00000003UL - /* CFG_AXI_END_ADDRESS_AXI1_1 [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 0xFFFFFFFFUL - /* CFG_AXI_END_ADDRESS_AXI2_0 [0:32] RW value= 0xFFFFFFFF */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 0x00000003UL - /* CFG_AXI_END_ADDRESS_AXI2_1 [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI1_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI1_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI2_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI2_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1 0x00000000UL - /* CFG_ENABLE_BUS_HOLD_AXI1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2 0x00000000UL - /* CFG_ENABLE_BUS_HOLD_AXI2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_AUTO_PCH) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_AUTO_PCH 0x00000000UL - /* CFG_AXI_AUTO_PCH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_RESET_CONTROL) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_RESET_CONTROL 0x00008001UL - /* PHY_RESET_CONTROL [0:32] RW value= 0x8001 */ -#endif -#if !defined (LIBERO_SETTING_PHY_PC_RANK) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_PC_RANK 0x00000001UL - /* PHY_PC_RANK [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_PHY_RANKS_TO_TRAIN) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_RANKS_TO_TRAIN 0x00000001UL - /* PHY_RANKS_TO_TRAIN [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_PHY_WRITE_REQUEST) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_WRITE_REQUEST 0x00000000UL - /* PHY_WRITE_REQUEST [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_READ_REQUEST) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_READ_REQUEST 0x00000000UL - /* PHY_READ_REQUEST [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY 0x00000000UL - /* PHY_WRITE_LEVEL_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_GATE_TRAIN_DELAY) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_GATE_TRAIN_DELAY 0x0000003FUL - /* PHY_GATE_TRAIN_DELAY [0:32] RW value= 0x3F */ -#endif -#if !defined (LIBERO_SETTING_PHY_EYE_TRAIN_DELAY) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_EYE_TRAIN_DELAY 0x0000003FUL - /* PHY_EYE_TRAIN_DELAY [0:32] RW value= 0x3F */ -#endif -#if !defined (LIBERO_SETTING_PHY_EYE_PAT) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_EYE_PAT 0x00000000UL - /* PHY_EYE_PAT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_START_RECAL) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_START_RECAL 0x00000000UL - /* PHY_START_RECAL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC 0x00000000UL - /* PHY_CLR_DFI_LVL_PERIODIC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE 0x00000018UL - /* PHY_TRAIN_STEP_ENABLE [0:32] RW value= 0x18 */ -#endif -#if !defined (LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT 0x00000000UL - /* PHY_LPDDR_DQ_CAL_PAT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_INDPNDT_TRAINING) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_INDPNDT_TRAINING 0x00000001UL - /* PHY_INDPNDT_TRAINING [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_PHY_ENCODED_QUAD_CS) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_ENCODED_QUAD_CS 0x00000000UL - /* PHY_ENCODED_QUAD_CS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE 0x00000000UL - /* PHY_HALF_CLK_DLY_ENABLE [0:32] RW value= 0x00000000 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDRC_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/general/hw_gen_peripherals.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/general/hw_gen_peripherals.h deleted file mode 100644 index ccc37c1..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/general/hw_gen_peripherals.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_gen_peripherals.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_gen_peripherals.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_GEN_PERIPHERALS_H_ -#define HW_GEN_PERIPHERALS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_GPIO_CR) -/*GPIO Blocks reset control- (soft_reset options chossen in Libero confgurator) -*/ -#define LIBERO_SETTING_GPIO_CR 0x000F0703UL - /* GPIO0_SOFT_RESET_SELECT [0:2] RW value= 0x3 */ - /* GPIO0_DEFAULT [4:2] RW value= 0x0 */ - /* GPIO1_SOFT_RESET_SELECT [8:3] RW value= 0x7 */ - /* GPIO1_DEFAULT [12:3] RW value= 0x0 */ - /* GPIO2_SOFT_RESET_SELECT [16:4] RW value= 0xF */ - /* GPIO2_DEFAULT [20:4] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_CR_INFO) -/*Information on how Crypto setup on this MPFS */ -#define LIBERO_SETTING_CRYPTO_CR_INFO 0x00000000UL - /* MSS_MODE [0:2] RO */ - /* RESERVED [2:1] RO */ - /* STREAM_ENABLE [3:1] RO */ - /* RESERVED1 [4:28] RO */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_GEN_PERIPHERALS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/hw_platform.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/hw_platform.h deleted file mode 100644 index 60e645b..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/hw_platform.h +++ /dev/null @@ -1,79 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_platform.h - * @author Embedded Software - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_platform.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PLATFORM_H_ -#define HW_PLATFORM_H_ - -#include "memory_map/hw_memory.h" -#include "memory_map/hw_apb_split.h" -#include "memory_map/hw_cache.h" -#include "memory_map/hw_pmp_hart0.h" -#include "memory_map/hw_pmp_hart1.h" -#include "memory_map/hw_pmp_hart2.h" -#include "memory_map/hw_pmp_hart3.h" -#include "memory_map/hw_pmp_hart4.h" -#include "memory_map/hw_mpu_fic0.h" -#include "memory_map/hw_mpu_fic1.h" -#include "memory_map/hw_mpu_fic2.h" -#include "memory_map/hw_mpu_crypto.h" -#include "memory_map/hw_mpu_gem0.h" -#include "memory_map/hw_mpu_gem1.h" -#include "memory_map/hw_mpu_usb.h" -#include "memory_map/hw_mpu_mmc.h" -#include "memory_map/hw_mpu_scb.h" -#include "memory_map/hw_mpu_trace.h" -#include "io/hw_mssio_mux.h" -#include "io/hw_hsio_mux.h" -#include "sgmii/hw_sgmii_tip.h" -#include "ddr/hw_ddr_options.h" -#include "ddr/hw_ddr_io_bank.h" -#include "ddr/hw_ddr_mode.h" -#include "ddr/hw_ddr_off_mode.h" -#include "ddr/hw_ddr_segs.h" -#include "ddr/hw_ddrc.h" -#include "clocks/hw_mss_clks.h" -#include "clocks/hw_clk_sysreg.h" -#include "clocks/hw_clk_mss_pll.h" -#include "clocks/hw_clk_sgmii_pll.h" -#include "clocks/hw_clk_ddr_pll.h" -#include "clocks/hw_clk_mss_cfm.h" -#include "clocks/hw_clk_sgmii_cfm.h" -#include "general/hw_gen_peripherals.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* No content in this file, used for referencing header */ - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PLATFORM_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/io/hw_hsio_mux.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/io/hw_hsio_mux.h deleted file mode 100644 index e857172..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/io/hw_hsio_mux.h +++ /dev/null @@ -1,61 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_hsio_mux.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_hsio_mux.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_HSIO_MUX_H_ -#define HW_HSIO_MUX_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_TRIM_OPTIONS) -/*User trim options- set option to 1 to use */ -#define LIBERO_SETTING_TRIM_OPTIONS 0x00000000UL - /* TRIM_DDR_OPTION [0:1] */ - /* TRIM_SGMII_OPTION [1:1] */ -#endif -#if !defined (LIBERO_SETTING_DDR_IOC_REG0) -/*Manual trim values */ -#define LIBERO_SETTING_DDR_IOC_REG0 0x00000000UL - /* BANK_PCODE [0:6] RW value= 0x0 */ - /* BANK_NCODE [6:6] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_IOC_REG0) -/*Manual trim values */ -#define LIBERO_SETTING_SGMII_IOC_REG0 0x00000000UL - /* BANK_PCODE [0:6] RW value= 0x0 */ - /* BANK_NCODE [6:6] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_HSIO_MUX_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/io/hw_mssio_mux.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/io/hw_mssio_mux.h deleted file mode 100644 index 40d9c20..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/io/hw_mssio_mux.h +++ /dev/null @@ -1,313 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mssio_mux.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mssio_mux.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MSSIO_MUX_H_ -#define HW_MSSIO_MUX_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_IOMUX0_CR) -/*Selects whether the peripheral is connected to the Fabric or IOMUX structure. -*/ -#define LIBERO_SETTING_IOMUX0_CR 0x00000000UL - /* SPI0_FABRIC [0:1] RW value= 0x0 */ - /* SPI1_FABRIC [1:1] RW value= 0x0 */ - /* I2C0_FABRIC [2:1] RW value= 0x0 */ - /* I2C1_FABRIC [3:1] RW value= 0x0 */ - /* CAN0_FABRIC [4:1] RW value= 0x0 */ - /* CAN1_FABRIC [5:1] RW value= 0x0 */ - /* QSPI_FABRIC [6:1] RW value= 0x0 */ - /* MMUART0_FABRIC [7:1] RW value= 0x0 */ - /* MMUART1_FABRIC [8:1] RW value= 0x0 */ - /* MMUART2_FABRIC [9:1] RW value= 0x0 */ - /* MMUART3_FABRIC [10:1] RW value= 0x0 */ - /* MMUART4_FABRIC [11:1] RW value= 0x0 */ - /* MDIO0_FABRIC [12:1] RW value= 0x0 */ - /* MDIO1_FABRIC [13:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_IOMUX1_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX1_CR 0xFFFFFFFFUL - /* PAD0 [0:4] RW value= 0xF */ - /* PAD1 [4:4] RW value= 0xF */ - /* PAD2 [8:4] RW value= 0xF */ - /* PAD3 [12:4] RW value= 0xF */ - /* PAD4 [16:4] RW value= 0xF */ - /* PAD5 [20:4] RW value= 0xF */ - /* PAD6 [24:4] RW value= 0xF */ - /* PAD7 [28:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX2_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX2_CR 0x00FFFFFFUL - /* PAD8 [0:4] RW value= 0xF */ - /* PAD9 [4:4] RW value= 0xF */ - /* PAD10 [8:4] RW value= 0xF */ - /* PAD11 [12:4] RW value= 0xF */ - /* PAD12 [16:4] RW value= 0xF */ - /* PAD13 [20:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX3_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX3_CR 0x5555555FUL - /* PAD14 [0:4] RW value= 0xF */ - /* PAD15 [4:4] RW value= 0x5 */ - /* PAD16 [8:4] RW value= 0x5 */ - /* PAD17 [12:4] RW value= 0x5 */ - /* PAD18 [16:4] RW value= 0x5 */ - /* PAD19 [20:4] RW value= 0x5 */ - /* PAD20 [24:4] RW value= 0x5 */ - /* PAD21 [28:4] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_IOMUX4_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX4_CR 0xFFFFF555UL - /* PAD22 [0:4] RW value= 0x5 */ - /* PAD23 [4:4] RW value= 0x5 */ - /* PAD24 [8:4] RW value= 0x5 */ - /* PAD25 [12:4] RW value= 0xF */ - /* PAD26 [16:4] RW value= 0xF */ - /* PAD27 [20:4] RW value= 0xF */ - /* PAD28 [24:4] RW value= 0xF */ - /* PAD29 [28:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX5_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX5_CR 0xFFFFFFFFUL - /* PAD30 [0:4] RW value= 0xF */ - /* PAD31 [4:4] RW value= 0xF */ - /* PAD32 [8:4] RW value= 0xF */ - /* PAD33 [12:4] RW value= 0xF */ - /* PAD34 [16:4] RW value= 0xF */ - /* PAD35 [20:4] RW value= 0xF */ - /* PAD36 [24:4] RW value= 0xF */ - /* PAD37 [28:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX6_CR) -/*Sets whether the MMC/SD Voltage select lines are inverted on entry to the -IOMUX structure */ -#define LIBERO_SETTING_IOMUX6_CR 0x00000000UL - /* VLT_SEL [0:1] RW value= 0x0 */ - /* VLT_EN [1:1] RW value= 0x0 */ - /* VLT_CMD_DIR [2:1] RW value= 0x0 */ - /* VLT_DIR_0 [3:1] RW value= 0x0 */ - /* VLT_DIR_1_3 [4:1] RW value= 0x0 */ - /* SD_LED [5:1] RW value= 0x0 */ - /* SD_VOLT_0 [6:1] RW value= 0x0 */ - /* SD_VOLT_1 [7:1] RW value= 0x0 */ - /* SD_VOLT_2 [8:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_CFG_CR) -/*Configures the MSSIO block using SCB write */ -#define LIBERO_SETTING_MSSIO_BANK4_CFG_CR 0x00080907UL - /* BANK_PCODE [0:6] RW value= 0x7 */ - /* RESERVED0 [6:2] RW value= 0x00 */ - /* BANK_NCODE [8:6] RW value= 0x9 */ - /* RESERVED1 [14:2] RW value= 0x0 */ - /* VS [16:4] RW value= 0x8 */ - /* RESERVED2 [20:12] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR 0x08290829UL - /* IO_CFG_0 [0:16] RW value= 0x0829 */ - /* IO_CFG_1 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR 0x08290829UL - /* IO_CFG_2 [0:16] RW value= 0x0829 */ - /* IO_CFG_3 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR 0x08290829UL - /* IO_CFG_4 [0:16] RW value= 0x0829 */ - /* IO_CFG_5 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR 0x08290829UL - /* IO_CFG_6 [0:16] RW value= 0x0829 */ - /* IO_CFG_7 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR 0x08290829UL - /* IO_CFG_8 [0:16] RW value= 0x0829 */ - /* IO_CFG_9 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR 0x08290829UL - /* IO_CFG_10 [0:16] RW value= 0x0829 */ - /* IO_CFG_11 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR 0x08290829UL - /* IO_CFG_12 [0:16] RW value= 0x0829 */ - /* IO_CFG_13 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_CFG_CR) -/*Configures the MSSIO block using SCB write */ -#define LIBERO_SETTING_MSSIO_BANK2_CFG_CR 0x00080907UL - /* BANK_PCODE [0:6] RW value= 0x7 */ - /* RESERVED0 [6:2] RW value= 0x00 */ - /* BANK_NCODE [8:6] RW value= 0x9 */ - /* RESERVED1 [14:2] RW value= 0x0 */ - /* VS [16:4] RW value= 0x8 */ - /* RESERVED2 [20:12] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR 0x08290829UL - /* IO_CFG_0 [0:16] RW value= 0x0829 */ - /* IO_CFG_1 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR 0x08290829UL - /* IO_CFG_2 [0:16] RW value= 0x0829 */ - /* IO_CFG_3 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR 0x08290829UL - /* IO_CFG_4 [0:16] RW value= 0x0829 */ - /* IO_CFG_5 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR 0x08290829UL - /* IO_CFG_6 [0:16] RW value= 0x0829 */ - /* IO_CFG_7 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR 0x08290829UL - /* IO_CFG_8 [0:16] RW value= 0x0829 */ - /* IO_CFG_9 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR 0x08290829UL - /* IO_CFG_10 [0:16] RW value= 0x0829 */ - /* IO_CFG_11 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR 0x08290829UL - /* IO_CFG_12 [0:16] RW value= 0x0829 */ - /* IO_CFG_13 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR 0x08290829UL - /* IO_CFG_14 [0:16] RW value= 0x0829 */ - /* IO_CFG_15 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR 0x08290829UL - /* IO_CFG_16 [0:16] RW value= 0x0829 */ - /* IO_CFG_17 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR 0x08290829UL - /* IO_CFG_18 [0:16] RW value= 0x0829 */ - /* IO_CFG_19 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR 0x08290829UL - /* IO_CFG_20 [0:16] RW value= 0x0829 */ - /* IO_CFG_21 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR 0x08290829UL - /* IO_CFG_22 [0:16] RW value= 0x0829 */ - /* IO_CFG_23 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_VB2_CFG) -/*default dpc values for MSSIO bank 2 */ -#define LIBERO_SETTING_MSSIO_VB2_CFG 0x00000828UL - /* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */ - /* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */ - /* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */ - /* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */ - /* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */ - /* RESERVED [15:17] R */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_VB4_CFG) -/*default dpc values for MSSIO bank 4 */ -#define LIBERO_SETTING_MSSIO_VB4_CFG 0x00000828UL - /* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */ - /* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */ - /* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */ - /* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */ - /* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */ - /* RESERVED [15:17] R */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MSSIO_MUX_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_apb_split.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_apb_split.h deleted file mode 100644 index e9e7187..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_apb_split.h +++ /dev/null @@ -1,74 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_apb_split.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_apb_split.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_APB_SPLIT_H_ -#define HW_APB_SPLIT_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_APBBUS_CR) -/*AMP Mode peripheral mapping register. When the register bit is '0' the -peripheral is mapped into the 0x2000000 address range using AXI bus 5 from the -Coreplex. When the register bit is '1' the peripheral is mapped into the -0x28000000 address range using AXI bus 6 from the Coreplex. */ -#define LIBERO_SETTING_APBBUS_CR 0x00000000UL - /* MMUART0 [0:1] RWC */ - /* MMUART1 [1:1] RWC */ - /* MMUART2 [2:1] RWC */ - /* MMUART3 [3:1] RWC */ - /* MMUART4 [4:1] RWC */ - /* WDOG0 [5:1] RWC */ - /* WDOG1 [6:1] RWC */ - /* WDOG2 [7:1] RWC */ - /* WDOG3 [8:1] RWC */ - /* WDOG4 [9:1] RWC */ - /* SPI0 [10:1] RWC */ - /* SPI1 [11:1] RWC */ - /* I2C0 [12:1] RWC */ - /* I2C1 [13:1] RWC */ - /* CAN0 [14:1] RWC */ - /* CAN1 [15:1] RWC */ - /* GEM0 [16:1] RWC */ - /* GEM1 [17:1] RWC */ - /* TIMER [18:1] RWC */ - /* GPIO0 [19:1] RWC */ - /* GPIO1 [20:1] RWC */ - /* GPIO2 [21:1] RWC */ - /* RTC [22:1] RWC */ - /* H2FINT [23:1] RWC */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_APB_SPLIT_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_cache.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_cache.h deleted file mode 100644 index edbbf47..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_cache.h +++ /dev/null @@ -1,149 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_cache.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_cache.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CACHE_H_ -#define HW_CACHE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_WAY_ENABLE) -/*Way indexes less than or equal to this register value may be used by the -cache */ -#define LIBERO_SETTING_WAY_ENABLE 0x00000007UL - /* WAY_ENABLE [0:8] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M0) -/*Way mask register master 0 (hart0) */ -#define LIBERO_SETTING_WAY_MASK_M0 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M1) -/*Way mask register master 1 (hart1) */ -#define LIBERO_SETTING_WAY_MASK_M1 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M2) -/*Way mask register master 2 (hart2) */ -#define LIBERO_SETTING_WAY_MASK_M2 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M3) -/*Way mask register master 3 (hart3) */ -#define LIBERO_SETTING_WAY_MASK_M3 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M4) -/*Way mask register master 4 (hart4) */ -#define LIBERO_SETTING_WAY_MASK_M4 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CACHE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_memory.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_memory.h deleted file mode 100644 index ee347e6..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_memory.h +++ /dev/null @@ -1,98 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_memory.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_memory.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MEMORY_H_ -#define HW_MEMORY_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART0) -/*Reset vector hart0 */ -#define LIBERO_SETTING_RESET_VECTOR_HART0 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART0_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART1) -/*Reset vector hart1 */ -#define LIBERO_SETTING_RESET_VECTOR_HART1 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART1_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART2) -/*Reset vector hart2 */ -#define LIBERO_SETTING_RESET_VECTOR_HART2 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART2_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART3) -/*Reset vector hart3 */ -#define LIBERO_SETTING_RESET_VECTOR_HART3 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART3_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART4) -/*Reset vector hart4 */ -#define LIBERO_SETTING_RESET_VECTOR_HART4 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART4_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_32_CACHE) -/*example instance of memory */ -#define LIBERO_SETTING_DDR_32_CACHE 0x80000000 -#define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_32_NON_CACHE) -/*example instance */ -#define LIBERO_SETTING_DDR_32_NON_CACHE 0xC0000000 -#define LIBERO_SETTING_DDR_32_NON_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_64_CACHE) -/*64 bit address */ -#define LIBERO_SETTING_DDR_64_CACHE 0x1000000000 -#define LIBERO_SETTING_DDR_64_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_64_NON_CACHE) -/*64 bit address */ -#define LIBERO_SETTING_DDR_64_NON_CACHE 0x1400000000 -#define LIBERO_SETTING_DDR_64_NON_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_32_WCB) -/*example instance */ -#define LIBERO_SETTING_DDR_32_WCB 0xD0000000 -#define LIBERO_SETTING_DDR_32_WCB_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_64_WCB) -/*64 bit address */ -#define LIBERO_SETTING_DDR_64_WCB 0x1800000000 -#define LIBERO_SETTING_DDR_64_WCB_SIZE 0x100000 /* Length of memory block*/ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MEMORY_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_crypto.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_crypto.h deleted file mode 100644 index 43d505e..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_crypto.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_crypto.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_crypto.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_CRYPTO_H_ -#define HW_MPU_CRYPTO_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_CRYPTO_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic0.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic0.h deleted file mode 100644 index 553581f..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic0.h +++ /dev/null @@ -1,155 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_fic0.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_fic0.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_FIC0_H_ -#define HW_MPU_FIC0_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP8) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP9) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP10) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP11) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP12) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP13) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP14) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP15) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_FIC0_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic1.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic1.h deleted file mode 100644 index 2cfac91..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic1.h +++ /dev/null @@ -1,155 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_fic1.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_fic1.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_FIC1_H_ -#define HW_MPU_FIC1_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP8) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP9) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP10) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP11) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP12) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP13) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP14) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP15) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_FIC1_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic2.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic2.h deleted file mode 100644 index 1a803c6..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic2.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_fic2.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_fic2.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_FIC2_H_ -#define HW_MPU_FIC2_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_FIC2_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem0.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem0.h deleted file mode 100644 index 418aa95..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem0.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_gem0.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_gem0.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_GEM0_H_ -#define HW_MPU_GEM0_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_GEM0_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem1.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem1.h deleted file mode 100644 index 14fa46d..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem1.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_gem1.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_gem1.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_GEM1_H_ -#define HW_MPU_GEM1_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_GEM1_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_mmc.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_mmc.h deleted file mode 100644 index a36d15c..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_mmc.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_mmc.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_mmc.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_MMC_H_ -#define HW_MPU_MMC_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_MMC_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_scb.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_scb.h deleted file mode 100644 index 810182e..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_scb.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_scb.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_scb.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_SCB_H_ -#define HW_MPU_SCB_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_SCB_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_trace.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_trace.h deleted file mode 100644 index 34309bb..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_trace.h +++ /dev/null @@ -1,57 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_trace.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_trace.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_TRACE_H_ -#define HW_MPU_TRACE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_TRACE_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_TRACE_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_TRACE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_usb.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_usb.h deleted file mode 100644 index 45e8cd2..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_mpu_usb.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_usb.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_usb.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_USB_H_ -#define HW_MPU_USB_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_USB_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart0.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart0.h deleted file mode 100644 index b822a87..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart0.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart0.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart0.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART0_H_ -#define HW_PMP_HART0_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART0_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x00 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x00 */ - /* PMP3CFG [24:8] RW value= 0x00 */ - /* PMP4CFG [32:8] RW value= 0x00 */ - /* PMP5CFG [40:8] RW value= 0x00 */ - /* PMP6CFG [48:8] RW value= 0x00 */ - /* PMP7CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART0_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x00 */ - /* PMP9CFG [8:8] RW value= 0x00 */ - /* PMP10CFG [16:8] RW value= 0x00 */ - /* PMP11CFG [24:8] RW value= 0x00 */ - /* PMP12CFG [32:8] RW value= 0x00 */ - /* PMP13CFG [40:8] RW value= 0x00 */ - /* PMP14CFG [48:8] RW value= 0x00 */ - /* PMP15CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x00 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART0_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart1.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart1.h deleted file mode 100644 index 966b27d..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart1.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart1.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart1.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART1_H_ -#define HW_PMP_HART1_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART1_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x00 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x00 */ - /* PMP3CFG [24:8] RW value= 0x00 */ - /* PMP4CFG [32:8] RW value= 0x00 */ - /* PMP5CFG [40:8] RW value= 0x00 */ - /* PMP6CFG [48:8] RW value= 0x00 */ - /* PMP7CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART1_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x00 */ - /* PMP9CFG [8:8] RW value= 0x00 */ - /* PMP10CFG [16:8] RW value= 0x00 */ - /* PMP11CFG [24:8] RW value= 0x00 */ - /* PMP12CFG [32:8] RW value= 0x00 */ - /* PMP13CFG [40:8] RW value= 0x00 */ - /* PMP14CFG [48:8] RW value= 0x00 */ - /* PMP15CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x00 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART1_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart2.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart2.h deleted file mode 100644 index 011e2e1..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart2.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart2.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart2.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART2_H_ -#define HW_PMP_HART2_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART2_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x0 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x0 */ - /* PMP3CFG [24:8] RW value= 0x0 */ - /* PMP4CFG [32:8] RW value= 0x0 */ - /* PMP5CFG [40:8] RW value= 0x0 */ - /* PMP6CFG [48:8] RW value= 0x0 */ - /* PMP7CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART2_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x0 */ - /* PMP9CFG [8:8] RW value= 0x0 */ - /* PMP10CFG [16:8] RW value= 0x0 */ - /* PMP11CFG [24:8] RW value= 0x0 */ - /* PMP12CFG [32:8] RW value= 0x0 */ - /* PMP13CFG [40:8] RW value= 0x0 */ - /* PMP14CFG [48:8] RW value= 0x0 */ - /* PMP15CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART2_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart3.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart3.h deleted file mode 100644 index 2cb3ae0..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart3.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart3.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart3.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART3_H_ -#define HW_PMP_HART3_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART3_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x0 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x0 */ - /* PMP3CFG [24:8] RW value= 0x0 */ - /* PMP4CFG [32:8] RW value= 0x0 */ - /* PMP5CFG [40:8] RW value= 0x0 */ - /* PMP6CFG [48:8] RW value= 0x0 */ - /* PMP7CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART3_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x0 */ - /* PMP9CFG [8:8] RW value= 0x0 */ - /* PMP10CFG [16:8] RW value= 0x0 */ - /* PMP11CFG [24:8] RW value= 0x0 */ - /* PMP12CFG [32:8] RW value= 0x0 */ - /* PMP13CFG [40:8] RW value= 0x0 */ - /* PMP14CFG [48:8] RW value= 0x0 */ - /* PMP15CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART3_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart4.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart4.h deleted file mode 100644 index d2ce0d0..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart4.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart4.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart4.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART4_H_ -#define HW_PMP_HART4_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART4_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x0 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x0 */ - /* PMP3CFG [24:8] RW value= 0x0 */ - /* PMP4CFG [32:8] RW value= 0x0 */ - /* PMP5CFG [40:8] RW value= 0x0 */ - /* PMP6CFG [48:8] RW value= 0x0 */ - /* PMP7CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART4_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x0 */ - /* PMP9CFG [8:8] RW value= 0x0 */ - /* PMP10CFG [16:8] RW value= 0x0 */ - /* PMP11CFG [24:8] RW value= 0x0 */ - /* PMP12CFG [32:8] RW value= 0x0 */ - /* PMP13CFG [40:8] RW value= 0x0 */ - /* PMP14CFG [48:8] RW value= 0x0 */ - /* PMP15CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART4_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/sgmii/hw_sgmii_tip.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/sgmii/hw_sgmii_tip.h deleted file mode 100644 index e11f33e..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_config/sgmii/hw_sgmii_tip.h +++ /dev/null @@ -1,197 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_sgmii_tip.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_sgmii_tip.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_SGMII_TIP_H_ -#define HW_SGMII_TIP_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SGMII_MODE) -/*SGMII mode control (SEU) */ -#define LIBERO_SETTING_SGMII_MODE 0x08C0E60CUL - /* REG_PLL_EN [0:1] RW value= 0x0 */ - /* REG_DLL_EN [1:1] RW value= 0x0 */ - /* REG_PVT_EN [2:1] RW value= 0x1 */ - /* REG_BC_VRGEN_EN [3:1] RW value= 0x1 */ - /* REG_TX0_EN [4:1] RW value= 0x0 */ - /* REG_RX0_EN [5:1] RW value= 0x0 */ - /* REG_TX1_EN [6:1] RW value= 0x0 */ - /* REG_RX1_EN [7:1] RW value= 0x0 */ - /* REG_DLL_LOCK_FLT [8:2] RW value= 0x2 */ - /* REG_DLL_ADJ_CODE [10:4] RW value= 0x9 */ - /* REG_CH0_CDR_RESET_B [14:1] RW value= 0x1 */ - /* REG_CH1_CDR_RESET_B [15:1] RW value= 0x1 */ - /* REG_BC_VRGEN [16:6] RW value= 0x00 */ - /* REG_CDR_MOVE_STEP [22:1] RW value= 0x1 */ - /* REG_REFCLK_EN_RDIFF [23:1] RW value= 0x1 */ - /* REG_BC_VS [24:4] RW value= 0x8 */ - /* REG_REFCLK_EN_UDRIVE_P [28:1] RW value= 0x0 */ - /* REG_REFCLK_EN_INS_HYST_P [29:1] RW value= 0x0 */ - /* REG_REFCLK_EN_UDRIVE_N [30:1] RW value= 0x0 */ - /* REG_REFCLK_EN_INS_HYST_N [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_PLL_CNTL) -/*PLL control register (SEU) */ -#define LIBERO_SETTING_PLL_CNTL 0x80140101UL - /* REG_PLL_POSTDIV [0:7] RW value= 0x01 */ - /* ARO_PLL0_LOCK [7:1] RO */ - /* REG_PLL_RFDIV [8:6] RW value= 0x01 */ - /* REG_PLL_REG_RFCLK_SEL [14:1] RW value= 0x0 */ - /* REG_PLL_LP_REQUIRES_LOCK [15:1] RW value= 0x0 */ - /* REG_PLL_INTIN [16:12] RW value= 0x014 */ - /* REG_PLL_BWI [28:2] RW value= 0x0 */ - /* REG_PLL_BWP [30:2] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_CH0_CNTL) -/*Channel0 control register */ -#define LIBERO_SETTING_CH0_CNTL 0x00FC0000UL - /* REG_TX0_WPU_P [0:1] RW value= 0x0 */ - /* REG_TX0_WPD_P [1:1] RW value= 0x0 */ - /* REG_TX0_SLEW_P [2:2] RW value= 0x0 */ - /* REG_TX0_DRV_P [4:4] RW value= 0x0 */ - /* REG_TX0_ODT_P [8:4] RW value= 0x0 */ - /* REG_TX0_ODT_STATIC_P [12:3] RW value= 0x0 */ - /* REG_RX0_TIM_LONG [15:1] RW value= 0x0 */ - /* REG_RX0_WPU_P [16:1] RW value= 0x0 */ - /* REG_RX0_WPD_P [17:1] RW value= 0x0 */ - /* REG_RX0_IBUFMD_P [18:3] RW value= 0x7 */ - /* REG_RX0_EYEWIDTH_P [21:3] RW value= 0x7 */ - /* REG_RX0_ODT_P [24:4] RW value= 0x0 */ - /* REG_RX0_ODT_STATIC_P [28:3] RW value= 0x0 */ - /* REG_RX0_EN_FLAG_N [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CH1_CNTL) -/*Channel1 control register */ -#define LIBERO_SETTING_CH1_CNTL 0x00FC0000UL - /* REG_TX1_WPU_P [0:1] RW value= 0x0 */ - /* REG_TX1_WPD_P [1:1] RW value= 0x0 */ - /* REG_TX1_SLEW_P [2:2] RW value= 0x0 */ - /* REG_TX1_DRV_P [4:4] RW value= 0x0 */ - /* REG_TX1_ODT_P [8:4] RW value= 0x0 */ - /* REG_TX1_ODT_STATIC_P [12:3] RW value= 0x0 */ - /* REG_RX1_TIM_LONG [15:1] RW value= 0x0 */ - /* REG_RX1_WPU_P [16:1] RW value= 0x0 */ - /* REG_RX1_WPD_P [17:1] RW value= 0x0 */ - /* REG_RX1_IBUFMD_P [18:3] RW value= 0x7 */ - /* REG_RX1_EYEWIDTH_P [21:3] RW value= 0x7 */ - /* REG_RX1_ODT_P [24:4] RW value= 0x0 */ - /* REG_RX1_ODT_STATIC_P [28:3] RW value= 0x0 */ - /* REG_RX1_EN_FLAG_N [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_RECAL_CNTL) -/*Recalibration control register */ -#define LIBERO_SETTING_RECAL_CNTL 0x000020C8UL - /* REG_RECAL_DIFF_RANGE [0:5] RW value= 0x8 */ - /* REG_RECAL_START_EN [5:1] RW value= 0x0 */ - /* REG_PVT_CALIB_START [6:1] RW value= 0x1 */ - /* REG_PVT_CALIB_LOCK [7:1] RW value= 0x1 */ - /* REG_RECAL_UPD [8:1] RW value= 0x0 */ - /* BC_VRGEN_DIRECTION [9:1] RW value= 0x0 */ - /* BC_VRGEN_LOAD [10:1] RW value= 0x0 */ - /* BC_VRGEN_MOVE [11:1] RW value= 0x0 */ - /* REG_PVT_REG_CALIB_CLKDIV [12:2] RW value= 0x2 */ - /* REG_PVT_REG_CALIB_DIFFR_VSEL [14:2] RW value= 0x0 */ - /* SRO_DLL_90_CODE [16:7] RO */ - /* SRO_DLL_LOCK [23:1] RO */ - /* SRO_DLL_ST_CODE [24:7] RO */ - /* SRO_RECAL_START [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_CLK_CNTL) -/*Clock input and routing control registers */ -#define LIBERO_SETTING_CLK_CNTL 0xF00050CCUL - /* REG_REFCLK_EN_TERM_P [0:2] RW value= 0x0 */ - /* REG_REFCLK_EN_RXMODE_P [2:2] RW value= 0x3 */ - /* REG_REFCLK_EN_TERM_N [4:2] RW value= 0x0 */ - /* REG_REFCLK_EN_RXMODE_N [6:2] RW value= 0x3 */ - /* REG_REFCLK_CLKBUF_EN_PULLUP [8:1] RW value= 0x0 */ - /* REG_CLKMUX_FCLK_SEL [9:3] RW value= 0x0 */ - /* REG_CLKMUX_PLL0_RFCLK0_SEL [12:2] RW value= 0x1 */ - /* REG_CLKMUX_PLL0_RFCLK1_SEL [14:2] RW value= 0x1 */ - /* REG_CLKMUX_SPARE0 [16:16] RW value= 0xf000 */ -#endif -#if !defined (LIBERO_SETTING_DYN_CNTL) -/*Dynamic control registers */ -#define LIBERO_SETTING_DYN_CNTL 0x00000400UL - /* REG_PLL_DYNEN [0:1] RW value= 0x0 */ - /* REG_DLL_DYNEN [1:1] RW value= 0x0 */ - /* REG_PVT_DYNEN [2:1] RW value= 0x0 */ - /* REG_BC_DYNEN [3:1] RW value= 0x0 */ - /* REG_CLKMUX_DYNEN [4:1] RW value= 0x0 */ - /* REG_LANE0_DYNEN [5:1] RW value= 0x0 */ - /* REG_LANE1_DYNEN [6:1] RW value= 0x0 */ - /* BC_VRGEN_OOR [7:1] RO */ - /* REG_PLL_SOFT_RESET_PERIPH [8:1] RW value= 0x0 */ - /* REG_DLL_SOFT_RESET_PERIPH [9:1] RW value= 0x0 */ - /* REG_PVT_SOFT_RESET_PERIPH [10:1] RW value= 0x1 */ - /* REG_BC_SOFT_RESET_PERIPH [11:1] RW value= 0x0 */ - /* REG_CLKMUX_SOFT_RESET_PERIPH [12:1] RW value= 0x0 */ - /* REG_LANE0_SOFT_RESET_PERIPH [13:1] RW value= 0x0 */ - /* REG_LANE1_SOFT_RESET_PERIPH [14:1] RW value= 0x0 */ - /* PVT_CALIB_STATUS [15:1] RO */ - /* ARO_PLL0_VCO0PH_SEL [16:3] RO */ - /* ARO_PLL0_VCO1PH_SEL [19:3] RO */ - /* ARO_PLL0_VCO2PH_SEL [22:3] RO */ - /* ARO_PLL0_VCO3PH_SEL [25:3] RO */ - /* ARO_REF_DIFFR [28:4] RO */ -#endif -#if !defined (LIBERO_SETTING_PVT_STAT) -/*PVT calibrator status registers */ -#define LIBERO_SETTING_PVT_STAT 0x00000000UL - /* ARO_REF_PCODE [0:6] RO */ - /* ARO_IOEN_BNK [6:1] RO */ - /* ARO_IOEN_BNK_B [7:1] RO */ - /* ARO_REF_NCODE [8:6] RO */ - /* ARO_CALIB_STATUS [14:1] RO */ - /* ARO_CALIB_STATUS_B [15:1] RO */ - /* ARO_PCODE [16:6] RO */ - /* ARO_CALIB_INTRPT [22:1] RO */ - /* PVT_CALIB_INTRPT [23:1] RO */ - /* ARO_NCODE [24:6] RO */ - /* PVT_CALIB_LOCK [30:1] RW value= 0x0 */ - /* PVT_CALIB_START [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SPARE_CNTL) -/*Spare control register */ -#define LIBERO_SETTING_SPARE_CNTL 0xFF000000UL - /* REG_SPARE [0:32] RW value= 0xff000000 */ -#endif -#if !defined (LIBERO_SETTING_SPARE_STAT) -/*Spare status register */ -#define LIBERO_SETTING_SPARE_STAT 0x00000000UL - /* SRO_SPARE [0:32] RO */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_SGMII_TIP_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_fpga_design/xml/PFSOC_MSS_C0_0..xml b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_fpga_design/xml/PFSOC_MSS_C0_0..xml deleted file mode 100644 index 19226e4..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/custom-board/soc_fpga_design/xml/PFSOC_MSS_C0_0..xml +++ /dev/null @@ -1,3221 +0,0 @@ - - - 12.900.0.16-PFSOC_MSS:2.0.108 - PFSOC_MSS_C0 - MPFS250T_ES - FCVG484_Eval - 06-26-2020_16:18:34 - 0.3.8 - - - - - 0x20220000 - 0x20220000 - 0x20220000 - 0x20220000 - 0x20220000 - 0x80000000 - 0xC0000000 - 0x1000000000 - 0x1400000000 - 0xD0000000 - 0x1800000000 - - - - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 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0x0 - 0x0 - 0x0 - - - 0x0 - - - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - - - - - 0x1 - 0x1 - 0x0 - - - 0x5 - - - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x3 - 0x0 - 0x0 - 0x0 - 0x3 - 0x0 - 0x1 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - - - - - - - 0x3 - 0x0 - 0x7 - 0x0 - 0xF - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - - - - - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/drivers_config/readme.txt b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/drivers_config/readme.txt new file mode 100644 index 0000000..d05a6a9 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/drivers_config/readme.txt @@ -0,0 +1,5 @@ +contains user configuration of the drivers. +drivers config should follow the following format: +platform/config/drivers//_sw_cfg.h +e.g +platform/config/drivers/ddr/ddr_sw_cfg.h \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h new file mode 100644 index 0000000..70ad981 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h @@ -0,0 +1,404 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/******************************************************************************* + * + * Platform definitions + * Version based on requirements of MPFS MSS + * + */ + /*========================================================================*//** + @mainpage Sample file detailing how mss_sw_config.h should be constructed for + the MPFS MSS + + @section intro_sec Introduction + The mss_sw_config.h is to be located in the project + ./src/platform/config/software/mpfs_hal directory. + This file must be hand crafted when using the MPFS MSS. + + + @section + +*//*==========================================================================*/ + + +#ifndef USER_CONFIG_MSS_USER_CONFIG_H_ +#define USER_CONFIG_MSS_USER_CONFIG_H_ + +/*------------------------------------------------------------------------------ + * MPFS_HAL_FIRST_HART and MPFS_HAL_LAST_HART defines used to specify which + * harts to actually start. + * Set MPFS_HAL_FIRST_HART to a value other than 0 if you do not want your code + * to start and execute code on the E51 hart. + * Set MPFS_HAL_LAST_HART to a value smaller than 4 if you do not wish to use + * all U54 harts. + * Harts that are not started will remain in an infinite WFI loop unless used + * through some other method + */ +#ifndef MPFS_HAL_FIRST_HART +#define MPFS_HAL_FIRST_HART 0 +#endif + +#ifndef MPFS_HAL_LAST_HART +#define MPFS_HAL_LAST_HART 4 +#endif + +/*------------------------------------------------------------------------------ + * Markers used to indicate startup status of hart + */ +#define HLS_DATA_IN_WFI 0x12345678U +#define HLS_DATA_PASSED_WFI 0x87654321U + +/*------------------------------------------------------------------------------ + * Define the size of the HLS used + * In our HAL, we are using Hart Local storage for debug data storage only + * as well as flags for wfi instruction management. + * The TLS will take memory from top of the stack if allocated + * + */ +#define HLS_DEBUG_AREA_SIZE 64 + +/* define the required tick rate in Milliseconds */ +/* if this program is running on one hart only, only that particular hart value + * will be used */ +#define HART0_TICK_RATE_MS 5UL +#define HART1_TICK_RATE_MS 5UL +#define HART2_TICK_RATE_MS 5UL +#define HART3_TICK_RATE_MS 5UL +#define HART4_TICK_RATE_MS 5UL + +#define H2F_BASE_ADDRESS 0x20126000 /* or 0x28126000 */ + +/* + * define how you want the Bus Error Unit configured + */ +#define BEU_ENABLE 0x0ULL +#define BEU_PLIC_INT 0x0ULL +#define BEU_LOCAL_INT 0x0ULL + +/* + * Clear memory on startup + * 0 => do not clear DTIM and L2 + * 1 => Clears memory + */ +#ifndef MPFS_HAL_CLEAR_MEMORY +#define MPFS_HAL_CLEAR_MEMORY 1 +#endif + +/* + * MPFS_HAL_HW_CONFIG + * Conditional compile switch is used to determine if MPFS HAL will perform the + * hardware configurations or not. + * Defined => This program acts as a First stage bootloader and performs + * hardware configurations. + * Not defined => This program assumes that the hardware configurations are + * already performed (Typically by a previous boot stage) + * + * List of items initialised when MPFS_HAL_HW_CONFIG is enabled + * - load virtual rom (see load_virtual_rom(void) in system_startup.c) + * - l2 cache config + * - Bus error unit config + * - MPU config + * - pmp config + * - I/O, clock and clock mux's, DDR and SGMII + * - will start other harts, see text describing MPFS_HAL_FIRST_HART, + * MPFS_HAL_LAST_HART above + */ +#ifndef MPFS_HAL_HW_CONFIG +#define MPFS_HAL_HW_CONFIG +#endif + +/* + * If not using item, comment out line below + */ +//#define SGMII_SUPPORT +//#define DDR_SUPPORT +#define MSSIO_SUPPORT +//#define SIMULATION_TEST_FEEDBACK +//#define E51_ENTER_SLEEP_STATE + +/* + * DDR software options + */ +#define DDR_FULL_32BIT_NC_CHECK_EN + +#define PATTERN_INCREMENTAL (0x01U << 0U) +#define PATTERN_WALKING_ONE (0x01U << 1U) +#define PATTERN_WALKING_ZERO (0x01U << 2U) +#define PATTERN_RANDOM (0x01U << 3U) +#define PATTERN_0xCCCCCCCC (0x01U << 4U) +#define PATTERN_0x55555555 (0x01U << 5U) +#define PATTERN_ZEROS (0x01U << 6U) +#define MAX_NO_PATTERNS 7U +/* number of test writes to perform */ +#define SW_CFG_NUM_READS_WRITES 0x20000U +/* + * what test patterns to write/read on start-up + * */ +#define SW_CONFIG_PATTERN (PATTERN_INCREMENTAL|\ + PATTERN_WALKING_ONE|\ + PATTERN_WALKING_ZERO|\ + PATTERN_RANDOM|\ + PATTERN_0xCCCCCCCC|\ + PATTERN_0x55555555) +/* Training types status offsets */ +#define BCLK_SCLK_BIT (0x1U<<0U) +#define ADDCMD_BIT (0x1U<<1U) +#define WRLVL_BIT (0x1U<<2U) +#define RDGATE_BIT (0x1U<<3U) +#define DQ_DQS_BIT (0x1U<<4U) +/* The first five bits represent the currently supported training in the TIP */ +/* This value will not change unless more training possibilities are added to + * the TIP */ +#define TRAINING_MASK (BCLK_SCLK_BIT|\ + ADDCMD_BIT|\ + WRLVL_BIT|\ + RDGATE_BIT|\ + DQ_DQS_BIT) +/* + * Debug DDR startup through a UART + * Comment out in normal operation. May be useful for debug purposes in bring-up + * of a new board design. + * See the weak function setup_ddr_debug_port(mss_uart_instance_t * uart) + * If you need to edit this function, make a copy of of the function without the + * weak declaration in your application code. + * */ +#define DEBUG_DDR_INIT +#define DEBUG_DDR_RD_RW_FAIL +//#define DEBUG_DDR_RD_RW_PASS +//#define DEBUG_DDR_CFG_DDR_SGMII_PHY +#define DEBUG_DDR_DDRCFG + + +/* + * During development we need to locally overwrite some values coming from + * Libero + * These are placed below here + */ +/* + * If using DDR4, enable DDR4__CODE_TAG_0_2 define + */ +//#define DDR4__CODE_TAG_0_2 + +/* + * You can over write any on the settings coming from Libero here + * + * e.g. Define how you want SEG registers configured, if you want to change from + * the default settings + */ + +#define LIBERO_SETTING_SEG0_0 (-(0x0080000000LL >> 24U)) +#define LIBERO_SETTING_SEG0_1 (-(0x1000000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_2 (-(0x00C0000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_3 (-(0x1400000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_4 (-(0x00D0000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_5 (-(0x1800000000LL >> 24U)) + +/* comment out any of these defines if you do not want to sweep values + * SUPPORT_ADDR_CMD_OFFSET_SWEEP + * SUPPORT_BCLK_SCLK_SWEEP + * SUPPORT_DPC_SWEEP + * Alternatively, modify the sweep values. This helps when calibrating a new + * board design. Enabling DEBUG_DDR_INIT define above will display the + * calibration sweep. + */ +//#define SWEEP_ENABLED +#define SUPPORT_ADDR_CMD_OFFSET_SWEEP +#define SUPPORT_BCLK_SCLK_SWEEP +#define SUPPORT_DPC_SWEEP + +#define LIBERO_SETTING_MAX_ADDRESS_CMD_OFFSET 4UL +#define LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET 2UL +#define MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS ((LIBERO_SETTING_MAX_ADDRESS_CMD_OFFSET-LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET) +1U) + +#define LIBERO_SETTING_MAX_ADDRESS_BCLK_SCLK_OFFSET 5UL +#define LIBERO_SETTING_MIN_ADDRESS_BCLK_SCLK_OFFSET 5UL +#define MAX_NUMBER__BCLK_SCLK_OFFSET_SWEEPS ((LIBERO_SETTING_MAX_ADDRESS_BCLK_SCLK_OFFSET-LIBERO_SETTING_MIN_ADDRESS_BCLK_SCLK_OFFSET)+1U) + +#define LIBERO_SETTING_MAX_DPC_V_GEN 9UL +#define LIBERO_SETTING_MIN_DPC_V_GEN 9UL +#define MAX_NUMBER_DPC_V_GEN_SWEEPS ((LIBERO_SETTING_MAX_DPC_V_GEN-LIBERO_SETTING_MIN_DPC_V_GEN)+1U) + +#define LIBERO_SETTING_MAX_DPC_H_GEN 2UL +#define LIBERO_SETTING_MIN_DPC_H_GEN 2UL +#define MAX_NUMBER_DPC_H_GEN_SWEEPS ((LIBERO_SETTING_MAX_DPC_H_GEN-LIBERO_SETTING_MIN_DPC_H_GEN)+1U) + +#define LIBERO_SETTING_MAX_DPC_VS_GEN 2UL +#define LIBERO_SETTING_MIN_DPC_VS_GEN 2UL +#define MAX_NUMBER_DPC_VS_GEN_SWEEPS ((LIBERO_SETTING_MAX_DPC_VS_GEN-LIBERO_SETTING_MIN_DPC_VS_GEN)+1U) + +/* + * Define SW_CONFIG_LPDDR_WR_CALIB_FN if we want to use lpddr4 wr calib function + */ +//#define SW_CONFIG_LPDDR_WR_CALIB_FN +/* + * Temporally write Icicle/peripheral board differences here + */ +#define ICICLE_BOARD +#ifdef ICICLE_BOARD + +/* + * over-write value from Libero todo: remove once verified in Libero design + */ + +#define LIBERO_SETTING_MSSIO_BANK2_CFG_CR 0x00080907UL + /* BANK_PCODE [0:6] RW value= 0x7 */ + /* RESERVED0 [6:2] RW value= 0x00 */ + /* BANK_NCODE [8:6] RW value= 0x9 */ + /* RESERVED1 [14:2] RW value= 0x0 */ + /* VS [16:4] RW value= 0x8 */ + /* RESERVED2 [20:12] RW value= 0x0 */ +#define LIBERO_SETTING_MSSIO_BANK4_CFG_CR 0x00080907UL + /* BANK_PCODE [0:6] RW value= 0x7 */ + /* RESERVED0 [6:2] RW value= 0x00 */ + /* BANK_NCODE [8:6] RW value= 0x9 */ + /* RESERVED1 [14:2] RW value= 0x0 */ + /* VS [16:4] RW value= 0x8 */ + /* RESERVED2 [20:12] RW value= 0x0 */ + + +//#define LIBERO_SETTING_DPC_BITS 0x00049432UL +#define LIBERO_SETTING_DPC_BITS 0x00049432UL // Received from SVG 5/14/2020 +#define LIBERO_SETTING_DDRPHY_MODE 0x00014B24UL +#define LIBERO_SETTING_DATA_LANES_USED 0x00000004UL +#define LIBERO_SETTING_CFG_DQ_WIDTH 0x00000000UL + +#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02AUL // 0x07CFE02AUL//0x07CFE02AUL + /* ADDCMD_OFFSET [0:3] RW value= 0x2 5*/ + /* BCKLSCLK_OFFSET [3:3] RW value= 0x4 */ + /* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */ + /* READ_GATE_MIN_READS [13:8] RW value= 0x1F */ + /* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */ + +/* + * over write value from Libero + */ +#define LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT 0x00000003UL + +/* + * Temporarily over write values from Libero + */ +#define LIBERO_SETTING_RPC_ODT_ADDCMD 2 +#define LIBERO_SETTING_RPC_ODT_CLK 2 +#define LIBERO_SETTING_RPC_ODT_DQ 6 //6 +#define LIBERO_SETTING_RPC_ODT_DQS 6 //2 for peripheral board + +#else /* peripheral board */ +/* + * over-write value from Libero todo: remove once verifid in Libero design + */ +#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07C3E035UL //0x07C3E025UL + /* ADDCMD_OFFSET [0:3] RW value= 0x2 5*/ + /* BCKLSCLK_OFFSET [3:3] RW value= 0x4 */ + /* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */ + /* READ_GATE_MIN_READS [13:8] RW value= 0x1F */ + /* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */ + +/* + * over write value from Libero + */ +#define LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT 0x00000003UL + +/* + * Temporarily over write values from Libero + */ +#define LIBERO_SETTING_RPC_ODT_ADDCMD 2 +#define LIBERO_SETTING_RPC_ODT_CLK 2 +#define LIBERO_SETTING_RPC_ODT_DQ 6 +#define LIBERO_SETTING_RPC_ODT_DQS 2 + +#endif /* not ICICLE */ + +/* + * 0 implies all IP traing's used. This should be the default + * setting. + */ +#define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000000UL +/* + * 1 implies sw BCLK_SCK traing carried out before IP training. This should be + * the default + * setting. + */ +#define USE_SW_BCLK_SCK_TRAINING 0x00000001UL +#define SW_TRAING_BCLK_SCLK_OFFSET 0x00000006UL + +/* + * 0x6DU => setting vref_ca to 40% + * This (0x6DU) is the default setting. + * */ +#define DDR_MODE_REG_VREF_VALUE 0x6DU + +/* + * Will review address settings in Libero, tie in, sanity check with SEG + * settings + */ +#define LIBERO_SETTING_DDR_32_NON_CACHE 0xC0000000ULL + +/** + * \brief MPU configuration from Libero for FIC0 + * + */ +#define LIBERO_SETTING_FIC0_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for FIC1 0x1F00000FFFFFFFFF + * + */ +#define LIBERO_SETTING_FIC1_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for FIC2 + * + */ +#define LIBERO_SETTING_FIC2_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for ATHENA + * + */ +#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for GEM0 + * + */ +#define LIBERO_SETTING_GEM0_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for GEM1 + * + */ +#define LIBERO_SETTING_GEM1_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for MMC + * + */ +#define LIBERO_SETTING_MMC_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for SCB + * + */ +#define LIBERO_SETTING_SCB_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for USB + * + */ +#define LIBERO_SETTING_USB_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for TRACE + * + */ +#define LIBERO_SETTING_TRACE_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +#endif /* USER_CONFIG_MSS_USER_CONFIG_H_ */ + diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/readme.txt b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/readme.txt new file mode 100644 index 0000000..086c9f1 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/readme.txt @@ -0,0 +1,2 @@ +contains user configuration of the platform +e.g. division of memory between harts etc. \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h index 181e2d1..5e28a5f 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_ddr_pll.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h index 9f58ec0..fd52530 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_mss_cfm.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h index 553f6d3..0066c57 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_mss_pll.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h index 802611b..205e76a 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_sgmii_cfm.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h index 390dcfb..939ab74 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_sgmii_pll.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h index 15f5742..fcf24a2 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_sysreg.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h index 064aeac..ef17cf3 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mss_clks.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h index 3dacb22..40c6df9 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_io_bank.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, @@ -120,17 +120,388 @@ CA/CK Check at ioa pc bit */ #define LIBERO_SETTING_RPC_SPARE0_DQ 0x00008000UL /* RPC_SPARE0_DQ [0:32] RW value= 0x8000 */ #endif +#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000F00UL + /* MSS_DDR_CK0 [0:1] RW value= 0x0 */ + /* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */ + /* MSS_DDR_A0 [2:1] RW value= 0x0 */ + /* MSS_DDR_A1 [3:1] RW value= 0x0 */ + /* MSS_DDR_A2 [4:1] RW value= 0x0 */ + /* MSS_DDR_A3 [5:1] RW value= 0x0 */ + /* MSS_DDR_A4 [6:1] RW value= 0x0 */ + /* MSS_DDR_A5 [7:1] RW value= 0x0 */ + /* MSS_DDR_A6 [8:1] RW value= 0x1 */ + /* MSS_DDR_A7 [9:1] RW value= 0x1 */ + /* MSS_DDR_A8 [10:1] RW value= 0x1 */ + /* MSS_DDR_A9 [11:1] RW value= 0x1 */ +#endif #if !defined (LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10) -/*0x2000 7428 OVRT10 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000000UL - /* RPC_EN_ADDCMD1_OVRT10 [0:32] RW value= 0x0 */ +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000FFFUL + /* MSS_DDR_CK1 [0:1] RW value= 0x1 */ + /* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */ + /* MSS_DDR_A10 [2:1] RW value= 0x1 */ + /* MSS_DDR_A11 [3:1] RW value= 0x1 */ + /* MSS_DDR_A12 [4:1] RW value= 0x1 */ + /* MSS_DDR_A13 [5:1] RW value= 0x1 */ + /* MSS_DDR_A14 [6:1] RW value= 0x1 */ + /* MSS_DDR_A15 [7:1] RW value= 0x1 */ + /* MSS_DDR_A16 [8:1] RW value= 0x1 */ + /* MSS_DDR3_WE_N [9:1] RW value= 0x1 */ + /* MSS_DDR_BA0 [10:1] RW value= 0x1 */ + /* MSS_DDR_BA1 [11:1] RW value= 0x1 */ #endif #if !defined (LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11) -/*0x2000 742C OVRT11 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000120UL - /* RPC_EN_ADDCMD2_OVRT11 [0:32] RW value= 0x120 */ +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000FE6UL + /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */ + /* MSS_DDR_BG0 [1:1] RW value= 0x1 */ + /* MSS_DDR_BG1 [2:1] RW value= 0x1 */ + /* MSS_DDR_CS0 [3:1] RW value= 0x0 */ + /* MSS_DDR_CKE0 [4:1] RW value= 0x0 */ + /* MSS_DDR_ODT0 [5:1] RW value= 0x1 */ + /* MSS_DDR_CS1 [6:1] RW value= 0x1 */ + /* MSS_DDR_CKE1 [7:1] RW value= 0x1 */ + /* MSS_DDR_ODT1 [8:1] RW value= 0x1 */ + /* MSS_DDR_ACT_N [9:1] RW value= 0x1 */ + /* MSS_DDR_PARITY [10:1] RW value= 0x1 */ + /* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA0_OVRT12) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA0_OVRT12 0x00000000UL + /* MSS_DDR_DQ0 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ1 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ2 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ3 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ4 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ5 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ6 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ7 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM0 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA1_OVRT13) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA1_OVRT13 0x00000000UL + /* MSS_DDR_DQ8 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ9 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ10 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ11 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ12 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ13 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ14 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ15 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM1 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA2_OVRT14) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA2_OVRT14 0x00000000UL + /* MSS_DDR_DQ16 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ17 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ18 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ19 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ20 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ21 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ22 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ23 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM2 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA3_OVRT15) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA3_OVRT15 0x00000000UL + /* MSS_DDR_DQ24 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ25 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ26 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ27 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ28 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ29 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ30 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ31 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM3 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_ECC_OVRT16) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ECC_OVRT16 0x0000007FUL + /* MSS_DDR_DQ32 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ33 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ34 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ35 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */ + /* MSS_DDR_DM4 [6:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC235_WPD_ADD_CMD0) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC235_WPD_ADD_CMD0 0x00000000UL + /* MSS_DDR_CK0 [0:1] RW value= 0x0 */ + /* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */ + /* MSS_DDR_A0 [2:1] RW value= 0x0 */ + /* MSS_DDR_A1 [3:1] RW value= 0x0 */ + /* MSS_DDR_A2 [4:1] RW value= 0x0 */ + /* MSS_DDR_A3 [5:1] RW value= 0x0 */ + /* MSS_DDR_A4 [6:1] RW value= 0x0 */ + /* MSS_DDR_A5 [7:1] RW value= 0x0 */ + /* MSS_DDR_A6 [8:1] RW value= 0x0 */ + /* MSS_DDR_A7 [9:1] RW value= 0x0 */ + /* MSS_DDR_A8 [10:1] RW value= 0x0 */ + /* MSS_DDR_A9 [11:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC236_WPD_ADD_CMD1) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC236_WPD_ADD_CMD1 0x00000000UL + /* MSS_DDR_CK1 [0:1] RW value= 0x0 */ + /* MSS_DDR_CK_N1 [1:1] RW value= 0x0 */ + /* MSS_DDR_A10 [2:1] RW value= 0x0 */ + /* MSS_DDR_A11 [3:1] RW value= 0x0 */ + /* MSS_DDR_A12 [4:1] RW value= 0x0 */ + /* MSS_DDR_A13 [5:1] RW value= 0x0 */ + /* MSS_DDR_A14 [6:1] RW value= 0x0 */ + /* MSS_DDR_A15 [7:1] RW value= 0x0 */ + /* MSS_DDR_A16 [8:1] RW value= 0x0 */ + /* MSS_DDR3_WE_N [9:1] RW value= 0x0 */ + /* MSS_DDR_BA0 [10:1] RW value= 0x0 */ + /* MSS_DDR_BA1 [11:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC237_WPD_ADD_CMD2) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. Note: For LPDDR4 need +to over-ride MSS_DDR_ODT0 and MSS_DDR_ODT1 and eanble PU i.e. (set OVR_EN ==1 , +wpu == 0 , wpd == 1 ) */ +#define LIBERO_SETTING_RPC237_WPD_ADD_CMD2 0x00000120UL + /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */ + /* MSS_DDR_BG0 [1:1] RW value= 0x0 */ + /* MSS_DDR_BG1 [2:1] RW value= 0x0 */ + /* MSS_DDR_CS0 [3:1] RW value= 0x0 */ + /* MSS_DDR_CKE0 [4:1] RW value= 0x0 */ + /* MSS_DDR_ODT0 [5:1] RW value= 0x1 */ + /* MSS_DDR_CS1 [6:1] RW value= 0x0 */ + /* MSS_DDR_CKE1 [7:1] RW value= 0x0 */ + /* MSS_DDR_ODT1 [8:1] RW value= 0x1 */ + /* MSS_DDR_ACT_N [9:1] RW value= 0x0 */ + /* MSS_DDR_PARITY [10:1] RW value= 0x0 */ + /* MSS_DDR_ALERT_N [11:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC238_WPD_DATA0) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC238_WPD_DATA0 0x00000000UL + /* MSS_DDR_DQ0 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ1 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ2 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ3 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ4 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ5 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ6 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ7 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM0 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC239_WPD_DATA1) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC239_WPD_DATA1 0x00000000UL + /* MSS_DDR_DQ8 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ9 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ10 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ11 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ12 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ13 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ14 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ15 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM1 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC240_WPD_DATA2) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC240_WPD_DATA2 0x00000000UL + /* MSS_DDR_DQ16 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ17 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ18 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ19 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ20 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ21 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ22 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ23 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM2 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC241_WPD_DATA3) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC241_WPD_DATA3 0x00000000UL + /* MSS_DDR_DQ24 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ25 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ26 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ27 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ28 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ29 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ30 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ31 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM3 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC242_WPD_ECC) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC242_WPD_ECC 0x00000000UL + /* MSS_DDR_DQ32 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ33 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ34 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ35 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P4 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N4 [5:1] RW value= 0x0 */ + /* MSS_DDR_DM4 [6:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC243_WPU_ADD_CMD0) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC243_WPU_ADD_CMD0 0x00000FFFUL + /* MSS_DDR_CK0 [0:1] RW value= 0x1 */ + /* MSS_DDR_CK_N0 [1:1] RW value= 0x1 */ + /* MSS_DDR_A0 [2:1] RW value= 0x1 */ + /* MSS_DDR_A1 [3:1] RW value= 0x1 */ + /* MSS_DDR_A2 [4:1] RW value= 0x1 */ + /* MSS_DDR_A3 [5:1] RW value= 0x1 */ + /* MSS_DDR_A4 [6:1] RW value= 0x1 */ + /* MSS_DDR_A5 [7:1] RW value= 0x1 */ + /* MSS_DDR_A6 [8:1] RW value= 0x1 */ + /* MSS_DDR_A7 [9:1] RW value= 0x1 */ + /* MSS_DDR_A8 [10:1] RW value= 0x1 */ + /* MSS_DDR_A9 [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC244_WPU_ADD_CMD1) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC244_WPU_ADD_CMD1 0x00000FFFUL + /* MSS_DDR_CK1 [0:1] RW value= 0x1 */ + /* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */ + /* MSS_DDR_A10 [2:1] RW value= 0x1 */ + /* MSS_DDR_A11 [3:1] RW value= 0x1 */ + /* MSS_DDR_A12 [4:1] RW value= 0x1 */ + /* MSS_DDR_A13 [5:1] RW value= 0x1 */ + /* MSS_DDR_A14 [6:1] RW value= 0x1 */ + /* MSS_DDR_A15 [7:1] RW value= 0x1 */ + /* MSS_DDR_A16 [8:1] RW value= 0x1 */ + /* MSS_DDR3_WE_N [9:1] RW value= 0x1 */ + /* MSS_DDR_BA0 [10:1] RW value= 0x1 */ + /* MSS_DDR_BA1 [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC245_WPU_ADD_CMD2) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC245_WPU_ADD_CMD2 0x00000EDFUL + /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x1 */ + /* MSS_DDR_BG0 [1:1] RW value= 0x1 */ + /* MSS_DDR_BG1 [2:1] RW value= 0x1 */ + /* MSS_DDR_CS0 [3:1] RW value= 0x1 */ + /* MSS_DDR_CKE0 [4:1] RW value= 0x1 */ + /* MSS_DDR_ODT0 [5:1] RW value= 0x0 */ + /* MSS_DDR_CS1 [6:1] RW value= 0x1 */ + /* MSS_DDR_CKE1 [7:1] RW value= 0x1 */ + /* MSS_DDR_ODT1 [8:1] RW value= 0x0 */ + /* MSS_DDR_ACT_N [9:1] RW value= 0x1 */ + /* MSS_DDR_PARITY [10:1] RW value= 0x1 */ + /* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC246_WPU_DATA0) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC246_WPU_DATA0 0x000007FFUL + /* MSS_DDR_DQ0 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ1 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ2 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ3 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P0 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N0 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ4 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ5 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ6 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ7 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM0 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC247_WPU_DATA1) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC247_WPU_DATA1 0x000007FFUL + /* MSS_DDR_DQ8 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ9 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ10 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ11 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P1 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N1 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ12 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ13 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ14 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ15 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM1 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC248_WPU_DATA2) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC248_WPU_DATA2 0x000007FFUL + /* MSS_DDR_DQ16 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ17 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ18 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ19 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P2 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N2 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ20 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ21 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ22 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ23 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM2 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC249_WPU_DATA3) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC249_WPU_DATA3 0x000007FFUL + /* MSS_DDR_DQ24 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ25 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ26 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ27 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P3 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N3 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ28 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ29 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ30 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ31 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM3 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC250_WPU_ECC) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC250_WPU_ECC 0x0000007FUL + /* MSS_DDR_DQ32 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ33 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ34 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ35 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */ + /* MSS_DDR_DM4 [6:1] RW value= 0x1 */ #endif #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h index e94e36e..ac54f96 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_mode.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h index f5e283e..0bc2bd9 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_off_mode.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h index 1f00de1..2face17 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_options.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h index 98e090e..023b475 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_segs.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h index d62e5bd..47cae9c 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddrc.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h index 618b869..3e96472 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_gen_peripherals.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/hw_platform.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/hw_platform.h index c289132..5673b0f 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/hw_platform.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/hw_platform.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_platform.h * @author Embedded Software * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h index 9f945de..a5465bb 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_hsio_mux.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h index 76137cc..fb58c93 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mssio_mux.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h index 196c916..f5f423a 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_apb_split.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h index 0b12feb..172253b 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_cache.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, @@ -35,109 +35,397 @@ extern "C" { #if !defined (LIBERO_SETTING_WAY_ENABLE) /*Way indexes less than or equal to this register value may be used by the -cache */ +cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave +8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is +128KB. */ #define LIBERO_SETTING_WAY_ENABLE 0x00000007UL /* WAY_ENABLE [0:8] RW value= 0x7 */ #endif -#if !defined (LIBERO_SETTING_WAY_MASK_M0) -/*Way mask register master 0 (hart0) */ -#define LIBERO_SETTING_WAY_MASK_M0 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M1) -/*Way mask register master 1 (hart1) */ -#define LIBERO_SETTING_WAY_MASK_M1 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M2) -/*Way mask register master 2 (hart2) */ -#define LIBERO_SETTING_WAY_MASK_M2 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M3) -/*Way mask register master 3 (hart3) */ -#define LIBERO_SETTING_WAY_MASK_M3 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M4) -/*Way mask register master 4 (hart4) */ -#define LIBERO_SETTING_WAY_MASK_M4 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ +#if !defined (LIBERO_SETTING_WAY_MASK_DMA) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_DMA 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_0) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_1) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_2) +/*Way mask registerAXI slave port 2. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_3) +/*Way mask register AXI slave port 3. Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_DCACHE) +/*Way mask register E51 data cache (hart0). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_ICACHE) +/*Way mask registerE52 instruction cache (hart0). Set field to zero to disable +way from this master. The available cache ways are 0 to number set in +WAY_ENABLE register. If using scratch pad memory, the ways you want reserved +for scrathpad are not available for selection, you must set to 0. e.g. If three +ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set +to zero for all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_DCACHE) +/*Way mask register data cache (hart1). Set field to zero to disable way from +this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_ICACHE) +/*Way mask register instruction cache (hart1). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_DCACHE) +/*Way mask register data cache (hart2). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_ICACHE) +/*Way mask register instruction cache (hart2). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_DCACHE) +/*Way mask register data cache (hart3). Set field to 1 to disable way from this +master.Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_ICACHE) +/*Way mask register instruction cache(hart3). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_DCACHE) +/*Way mask register data cache (hart4). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_ICACHE) +/*Way mask register instruction cache (hart4). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS) +/*Number of ways reserved for scratchpad. Note 1: This is not a register Note +2: each way is 128KB. Note 3: Embedded software expects cache ways allocated +for scratchpad start at way 0, and work up. */ +#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000000UL + /* NUM_OF_WAYS [0:8] RW value= 0x0 */ #endif #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h index 8b0c956..741f2a3 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_memory.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h index 2d3681c..095205d 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_crypto.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h index 2e8559a..4baf682 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_fic0.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h index 0709c67..dd362dd 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_fic1.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h index 7d1cf33..fc881af 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_fic2.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h index 6f399a0..70da65f 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_gem0.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h index 695c7f3..c2a1fcd 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_gem1.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h index 97998f9..c9fbf3a 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_mmc.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h index c199275..ebdbbc6 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_scb.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h index 55465f9..322307a 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_trace.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h index b147f46..850c32a 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_usb.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h index 63a0fd1..c0f9a4f 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart0.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h index ebaff07..bb89409 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart1.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h index 735afc1..efed373 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart2.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h index f74ba05..ac94a7b 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart3.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h index 14e5796..3c60ffd 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart4.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h index 1ca9d42..90cb36c 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_sgmii_tip.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, @@ -180,7 +180,7 @@ extern "C" { #if !defined (LIBERO_SETTING_SPARE_CNTL) /*Spare control register */ #define LIBERO_SETTING_SPARE_CNTL 0xFF000000UL - /* REG_SPARE [0:32] RW value= 0xff000000 */ + /* REG_SPARE [0:32] RW value= 0xFF000000 */ #endif #if !defined (LIBERO_SETTING_SPARE_STAT) /*Spare status register */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_fpga_design/xml/ICICLE_MSS_0.xml b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_fpga_design/xml/mss_pf_cache_rev1_mss_cfg_8_0_8.xml similarity index 82% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_fpga_design/xml/ICICLE_MSS_0.xml rename to examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_fpga_design/xml/mss_pf_cache_rev1_mss_cfg_8_0_8.xml index f4bef02..eaffea4 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_fpga_design/xml/ICICLE_MSS_0.xml +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/boards/icicle-kit-es/soc_fpga_design/xml/mss_pf_cache_rev1_mss_cfg_8_0_8.xml @@ -1,11 +1,11 @@ - 12.900.0.16-PFSOC_MSS:2.0.108 - ICICLE_MSS + 2.0 + mss_pf_cache_rev1 MPFS250T_ES - FCVG484_Eval - 06-26-2020_16:47:44 - 0.3.8 + FCVG484 + 10-14-2020_15:34:36 + 0.4.2 @@ -55,98 +55,281 @@ - + 0x7 - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 @@ -1320,7 +1503,7 @@ 0x0 - 0xff000000 + 0xFF000000 @@ -1411,11 +1594,314 @@ 0x8000 - - 0x0 - - - 0x120 + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 + 0x1 + 0x1 + 0x0 + 0x0 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x1 + 0x0 + 0x0 + 0x1 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x0 + 0x1 + 0x1 + 0x0 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/middleware/config/readme.txt b/examples/mss-rtc/mpfs-rtc-interrupt/src/middleware/config/readme.txt new file mode 100644 index 0000000..95f6cb2 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/middleware/config/readme.txt @@ -0,0 +1 @@ +contains files relating to configuration of third party modules \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/middleware/readme.txt b/examples/mss-rtc/mpfs-rtc-interrupt/src/middleware/readme.txt new file mode 100644 index 0000000..0ffaed9 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/middleware/readme.txt @@ -0,0 +1 @@ +contains files relating to third party modules \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.c index 7794e57..9a98eba 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.c @@ -7,7 +7,6 @@ */ #include #include "mpfs_hal/mss_hal.h" -#include "mss_rtc_regs.h" #include "mss_rtc.h" #ifdef __cplusplus @@ -42,6 +41,7 @@ extern "C" { #define MASK_32_BIT 0xFFFFFFFFu #define MAX_PRESCALAR_COUNT 0x03FFFFFFu #define CALENDAR_SHIFT 8u +#define COMPARE_ALL_BITS 0xFFFFFFFFu /*-------------------------------------------------------------------------*//** * Index into look-up table. diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.h index 7eecd8f..002b5d5 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc.h @@ -188,8 +188,6 @@ #ifndef MSS_RTC_H_ #define MSS_RTC_H_ -#include "mss_rtc_regs.h" - #ifdef __cplusplus extern "C" { #endif @@ -233,6 +231,13 @@ extern "C" { #define MSS_RTC_FRIDAY 6u #define MSS_RTC_SATURDAY 7u + +/**************************************************************************//** + MSS RTC module instance base addresses +*/ +#define MSS_RTC_LO_ADDR 0x20124000u +#define MSS_RTC_HI_ADDR 0x28124000u + /***************************************************************************//** MSS RTC base addresses. These definitions provides access to the MSS RTC mapped at two different @@ -273,6 +278,42 @@ typedef struct mss_rtc_calender uint8_t week; } mss_rtc_calender_t ; +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +typedef struct +{ + volatile uint32_t CONTROL_REG ; + volatile uint32_t MODE_REG ; + volatile uint32_t PRESCALER_REG ; + volatile uint32_t ALARM_LOWER_REG ; + volatile uint32_t ALARM_UPPER_REG ; + volatile uint32_t COMPARE_LOWER_REG ; + volatile uint32_t COMPARE_UPPER_REG ; + uint32_t RESERVED0 ; + volatile uint32_t DATE_TIME_LOWER_REG ; + volatile uint32_t DATE_TIME_UPPER_REG ; + + uint32_t RESERVED1[2] ; + volatile uint32_t SECONDS_REG ; + volatile uint32_t MINUTES_REG ; + volatile uint32_t HOURS_REG ; + volatile uint32_t DAY_REG ; + volatile uint32_t MONTH_REG ; + volatile uint32_t YEAR_REG ; + volatile uint32_t WEEKDAY_REG ; + volatile uint32_t WEEK_REG ; + + volatile uint32_t SECONDS_CNT_REG ; + volatile uint32_t MINUTES_CNT_REG ; + volatile uint32_t HOURS_CNT_REG ; + volatile uint32_t DAY_CNT_REG ; + volatile uint32_t MONTH_CNT_REG ; + volatile uint32_t YEAR_CNT_REG ; + volatile uint32_t WEEKDAY_CNT_REG ; + volatile uint32_t WEEK_CNT_REG ; +} RTC_TypeDef; + /*-------------------------------------------------------------------------*//** The MSS_RTC_init() function initializes the RTC driver and hardware to a known state. To initialize the RTC hardware, this function: diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc_regs.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc_regs.h deleted file mode 100644 index fbd580a..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/drivers/mss_rtc/mss_rtc_regs.h +++ /dev/null @@ -1,67 +0,0 @@ - /****************************************************************************** - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * Register bit offsets and masks definitions for PolarFire SoC MSS RTC Driver. - - */ -#ifndef MSS_RTC_REG_H__ -#define MSS_RTC_REG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "mpfs_hal/mss_hal.h" - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ -typedef struct -{ - volatile uint32_t CONTROL_REG ; - volatile uint32_t MODE_REG ; - volatile uint32_t PRESCALER_REG ; - volatile uint32_t ALARM_LOWER_REG ; - volatile uint32_t ALARM_UPPER_REG ; - volatile uint32_t COMPARE_LOWER_REG ; - volatile uint32_t COMPARE_UPPER_REG ; - uint32_t RESERVED0 ; - volatile uint32_t DATE_TIME_LOWER_REG ; - volatile uint32_t DATE_TIME_UPPER_REG ; - - uint32_t RESERVED1[2] ; - volatile uint32_t SECONDS_REG ; - volatile uint32_t MINUTES_REG ; - volatile uint32_t HOURS_REG ; - volatile uint32_t DAY_REG ; - volatile uint32_t MONTH_REG ; - volatile uint32_t YEAR_REG ; - volatile uint32_t WEEKDAY_REG ; - volatile uint32_t WEEK_REG ; - - volatile uint32_t SECONDS_CNT_REG ; - volatile uint32_t MINUTES_CNT_REG ; - volatile uint32_t HOURS_CNT_REG ; - volatile uint32_t DAY_CNT_REG ; - volatile uint32_t MONTH_CNT_REG ; - volatile uint32_t YEAR_CNT_REG ; - volatile uint32_t WEEKDAY_CNT_REG ; - volatile uint32_t WEEK_CNT_REG ; -} RTC_TypeDef; - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define MSS_RTC_LO_ADDR 0x20124000u -#define MSS_RTC_HI_ADDR 0x28124000u - -#define COMPARE_ALL_BITS 0xFFFFFFFFu - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_RTC_REG_H__ */ - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal.h index 282def4..d91def0 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal.h @@ -1,4 +1,4 @@ -/******************************************************************************* +/***************************************************************************//** * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT @@ -49,7 +49,7 @@ void HAL_enable_interrupts( void ); /***************************************************************************//** * Disable all interrupts at the processor core level. - * Return the interrupts enable state before disabling occured so that it can + * Return the interrupts enable state before disabling occurred so that it can * later be restored. */ psr_t HAL_disable_interrupts( void ); diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal_irq.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal_irq.c index d0187dc..2fea28e 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal_irq.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal_irq.c @@ -14,11 +14,7 @@ */ #include #include "hal/hal.h" -#include "mpfs_hal/atomic.h" -#include "mpfs_hal/encoding.h" -#include "mpfs_hal/mcall.h" -#include "mpfs_hal/mss_util.h" -#include "mpfs_hal/mtrap.h" +#include "mpfs_hal/common/mss_util.h" #ifdef __cplusplus extern "C" { diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal_version.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal_version.h new file mode 100644 index 0000000..7d4d31c --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hal_version.h @@ -0,0 +1,50 @@ +#ifndef HAL_VERSION_H +#define HAL_VERSION_H + +/******************************************************************************* + * Copyright 2019-2020 Microchip Corporation. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * + * + */ + +/******************************************************************************* + * @file mpfs_halversion.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief MICROCHIP FPGA Embedded Software Hardware Abstraction layer - HAL + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HAL_VERSION_MAJOR 1 +#define HAL_VERSION_MINOR 8 +#define HAL_VERSION_PATCH 0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_macros.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_macros.h index 2ed2fc6..cab0935 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_macros.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_macros.h @@ -10,15 +10,15 @@ * * Hardware registers access macros. * - * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW + * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USE FOR NEW * DEVELOPMENT. * - * These macros are used to access peripheral's registers. They allow access to + * These macros are used to access peripheral registers. They allow access to * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should * be done through these macros in order to ease porting across different * processors/bus architectures. * - * Some of these macros also allow to access a specific register field. + * Some of these macros also allow access to a specific register field. * */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.S b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.S index 5e8627f..31352f6 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.S +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.S @@ -1,12 +1,9 @@ -/******************************************************************************* +/***************************************************************************//** * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * MPFS HAL Embedded Software - * - */ -/***************************************************************************//** * * Hardware registers access functions. * The implementation of these function is platform and toolchain specific. @@ -45,7 +42,8 @@ HW_set_32bit_reg: * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral * register. * - * R0: addr_t reg_addr + * a0: addr_t reg_addr + * @return 32 bits value read from the peripheral register. */ HW_get_32bit_reg: @@ -106,6 +104,7 @@ HW_set_16bit_reg: * register. * * a0: addr_t reg_addr + * @return 16 bits value read from the peripheral register. */ HW_get_16bit_reg: @@ -167,6 +166,7 @@ HW_set_8bit_reg: * register. * * a0: addr_t reg_addr + * @return 8 bits value read from the peripheral register. */ HW_get_8bit_reg: diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.h index de25342..10ae546 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/hw_reg_access.h @@ -9,9 +9,9 @@ /***************************************************************************//** * * Hardware registers access functions. - * The implementation of these function is platform and toolchain specific. + * The implementation of these function is platform and tool-chain specific. * The functions declared here are implemented using assembler as part of the - * processor/toolchain specific HAL. + * processor/tool-chain specific HAL. * */ #ifndef HW_REG_ACCESS diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/readme.md b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/readme.md new file mode 100644 index 0000000..ce9ae8f --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/hal/readme.md @@ -0,0 +1,41 @@ +=============================================================================== +# hal folder +=============================================================================== + +The HAL folder provides support code for use by the bare metal drivers for the +fabric IP cores. +The HAL folder contains files using a combination of C and assembly source code. + +The hal folder should be included in a PolarFire SoC Embedded project under the +platform directory. See location in the drawing below. + +The hal folder contains: + +* register access functions +* assert macros + +### Project directory strucutre, showing where hal folder sits. + + +---------+ +-----------+ + | src +----->|application| + +---------+ | +-----------+ + | + | +-----------+ + +-->|modules | + | +-----------+ + | + | +-----------+ +---------+ + +-->|platform +---->|config | + +-----------+ | +---------+ + | + | +---------+ + +->|drivers | + | +---------+ + | + | +---------+ + +->|hal | + | +---------+ + | + | +---------+ + +->|mpfs_hal | + +---------+ \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/atomic.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/atomic.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/atomic.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/atomic.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/bits.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/bits.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/bits.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/bits.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/encoding.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/encoding.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/encoding.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/encoding.h index 0c5c256..c86fb17 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/encoding.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/encoding.h @@ -231,22 +231,22 @@ asm volatile ("mv %0, " #reg : "=r"(__tmp)); \ __tmp; }) -#define read_csr(reg) ({ unsigned long __tmp; \ +#define read_csr(reg) __extension__({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) -#define write_csr(reg, val) ({ \ +#define write_csr(reg, val) __extension__({ \ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) #define swap_csr(reg, val) ({ unsigned long __tmp; \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ __tmp; }) -#define set_csr(reg, bit) ({ unsigned long __tmp; \ +#define set_csr(reg, bit) __extension__({ unsigned long __tmp; \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ +#define clear_csr(reg, bit) __extension__({ unsigned long __tmp; \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_assert.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_assert.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_assert.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_assert.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_axiswitch.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.c similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_axiswitch.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.c diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_axiswitch.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_axiswitch.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_axiswitch.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_clint.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_clint.c new file mode 100644 index 0000000..051fe47 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_clint.c @@ -0,0 +1,167 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/******************************************************************************* + * + * @file mss_clint.c + * @author Microchip-FPGA Embedded Systems Solutions + * @brief CLINT access data structures and functions. + * + */ +#include "mpfs_hal/mss_hal.h" +#include + +static uint64_t g_systick_increment[5] = {0ULL,0ULL,0ULL,0ULL,0ULL}; + +/** + * call once at startup + * @return + */ +void reset_mtime(void) +{ +#if ROLLOVER_TEST + CLINT->MTIME = 0xFFFFFFFFFFFFF000ULL; +#else + CLINT->MTIME = 0ULL; +#endif +} + +/** + * readmtime + * @return mtime + */ +uint64_t readmtime(void) +{ + return (CLINT->MTIME); +} + +/** + * Configure system tick + * @return SUCCESS or FAIL + */ +uint32_t SysTick_Config(void) +{ + const uint32_t tick_rate[5] = {HART0_TICK_RATE_MS, HART1_TICK_RATE_MS ,HART2_TICK_RATE_MS ,HART3_TICK_RATE_MS ,HART4_TICK_RATE_MS}; + volatile uint32_t ret_val = ERROR; + + uint64_t mhart_id = read_csr(mhartid); + + /* + * We are assuming the tick rate is in milli-seconds + * + * convert RTC frequency into milliseconds and multiple by the tick rate + * + */ + + g_systick_increment[mhart_id] = ((LIBERO_SETTING_MSS_RTC_TOGGLE_CLK/1000U) * tick_rate[mhart_id]); + + if (g_systick_increment[mhart_id] > 0ULL) + { + + CLINT->MTIMECMP[mhart_id] = CLINT->MTIME + g_systick_increment[mhart_id]; + + set_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ + + __enable_irq(); + + ret_val = SUCCESS; + } + + return (ret_val); +} + +/** + * Disable system tick interrupt + */ +void disable_systick(void) +{ + clear_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ + return; +} + + +/*------------------------------------------------------------------------------ + * RISC-V interrupt handler for machine timer interrupts. + */ +void handle_m_timer_interrupt(void) +{ + + volatile uint64_t hart_id = read_csr(mhartid); + volatile uint32_t error_loop; + clear_csr(mie, MIP_MTIP); + + switch(hart_id) + { + case 0U: + SysTick_Handler_h0_IRQHandler(); + break; + case 1U: + SysTick_Handler_h1_IRQHandler(); + break; + case 2U: + SysTick_Handler_h2_IRQHandler(); + break; + case 3U: + SysTick_Handler_h3_IRQHandler(); + break; + case 4U: + SysTick_Handler_h4_IRQHandler(); + break; + default: + while (hart_id != 0U) + { + error_loop++; + } + break; + } + + CLINT->MTIMECMP[read_csr(mhartid)] = CLINT->MTIME + g_systick_increment[hart_id]; + + set_csr(mie, MIP_MTIP); + +} + + +/** + * + */ +void handle_m_soft_interrupt(void) +{ + volatile uint64_t hart_id = read_csr(mhartid); + volatile uint32_t error_loop; + + switch(hart_id) + { + case 0U: + Software_h0_IRQHandler(); + break; + case 1U: + Software_h1_IRQHandler(); + break; + case 2U: + Software_h2_IRQHandler(); + break; + case 3U: + Software_h3_IRQHandler(); + break; + case 4U: + Software_h4_IRQHandler(); + break; + default: + while (hart_id != 0U) + { + error_loop++; + } + break; + } + + /*Clear software interrupt*/ + clear_soft_interrupt(); +} + diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_clint.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_clint.h similarity index 83% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_clint.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_clint.h index 60c90a6..f8cf46e 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_clint.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_clint.h @@ -44,6 +44,7 @@ typedef struct CLINT_Type_t #define CLINT ((CLINT_Type *)CLINT_BASE) + /*============================================================================== * The function raise_soft_interrupt() raises a synchronous software interrupt by * writing into the MSIP register. @@ -70,6 +71,38 @@ static inline void clear_soft_interrupt(void) (void)reg; /* use reg to avoid compiler warning */ } +/* + * return mtime + */ +uint64_t readmtime(void); + +/** + * call once at startup + * @return + */ +void reset_mtime(void); + +/** + * Configure system tick + * @return SUCCESS or FAIL + */ +uint32_t SysTick_Config(void); + +/** + * Disable system tick interrupt + */ +void disable_systick(void); + +/*------------------------------------------------------------------------------ + * RISC-V interrupt handler for machine timer interrupts. + */ +void handle_m_timer_interrupt(void); + +/** + * + */ +void handle_m_soft_interrupt(void); + #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_h2f.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_h2f.c similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_h2f.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_h2f.c diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_h2f.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_h2f.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_h2f.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_h2f.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_hart_ints.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_hart_ints.h similarity index 56% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_hart_ints.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_hart_ints.h index f764087..5dc0553 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_hart_ints.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_hart_ints.h @@ -41,6 +41,12 @@ typedef struct BEU_Types_ volatile BEU_Type regs[5]; } BEU_Types; +#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL +#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL +#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL +#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL +#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL + #define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) /* @@ -217,6 +223,153 @@ typedef struct BEU_Types_ #define H2_FABRIC_F2H_31_U54_INT 47 +void handle_m_ext_interrupt(void); +void Software_h0_IRQHandler(void); +void Software_h1_IRQHandler(void); +void Software_h2_IRQHandler(void); +void Software_h3_IRQHandler(void); +void Software_h4_IRQHandler(void); +void SysTick_Handler_h0_IRQHandler(void); +void SysTick_Handler_h1_IRQHandler(void); +void SysTick_Handler_h2_IRQHandler(void); +void SysTick_Handler_h3_IRQHandler(void); +void SysTick_Handler_h4_IRQHandler(void); + +/* + * + * Local interrupt defines + * + */ +void maintenance_e51_local_IRQHandler_0(void); +void usoc_smb_interrupt_e51_local_IRQHandler_1(void); +void usoc_vc_interrupt_e51_local_IRQHandler_2(void); +void g5c_message_e51_local_IRQHandler_3(void); +void g5c_devrst_e51_local_IRQHandler_4(void); +void wdog4_tout_e51_local_IRQHandler_5(void); +void wdog3_tout_e51_local_IRQHandler_6(void); +void wdog2_tout_e51_local_IRQHandler_7(void); +void wdog1_tout_e51_local_IRQHandler_8(void); +void wdog0_tout_e51_local_IRQHandler_9(void); +void wdog0_mvrp_e51_local_IRQHandler_10(void); +void mmuart0_e51_local_IRQHandler_11(void); +void envm_e51_local_IRQHandler_12(void); +void ecc_correct_e51_local_IRQHandler_13(void); +void ecc_error_e51_local_IRQHandler_14(void); +void scb_interrupt_e51_local_IRQHandler_15(void); +void fabric_f2h_32_e51_local_IRQHandler_16(void); +void fabric_f2h_33_e51_local_IRQHandler_17(void); +void fabric_f2h_34_e51_local_IRQHandler_18(void); +void fabric_f2h_35_e51_local_IRQHandler_19(void); +void fabric_f2h_36_e51_local_IRQHandler_20(void); +void fabric_f2h_37_e51_local_IRQHandler_21(void); +void fabric_f2h_38_e51_local_IRQHandler_22(void); +void fabric_f2h_39_e51_local_IRQHandler_23(void); +void fabric_f2h_40_e51_local_IRQHandler_24(void); +void fabric_f2h_41_e51_local_IRQHandler_25(void); +void fabric_f2h_42_e51_local_IRQHandler_26(void); +void fabric_f2h_43_e51_local_IRQHandler_27(void); +void fabric_f2h_44_e51_local_IRQHandler_28(void); +void fabric_f2h_45_e51_local_IRQHandler_29(void); +void fabric_f2h_46_e51_local_IRQHandler_30(void); +void fabric_f2h_47_e51_local_IRQHandler_31(void); +void fabric_f2h_48_e51_local_IRQHandler_32(void); +void fabric_f2h_49_e51_local_IRQHandler_33(void); +void fabric_f2h_50_e51_local_IRQHandler_34(void); +void fabric_f2h_51_e51_local_IRQHandler_35(void); +void fabric_f2h_52_e51_local_IRQHandler_36(void); +void fabric_f2h_53_e51_local_IRQHandler_37(void); +void fabric_f2h_54_e51_local_IRQHandler_38(void); +void fabric_f2h_55_e51_local_IRQHandler_39(void); +void fabric_f2h_56_e51_local_IRQHandler_40(void); +void fabric_f2h_57_e51_local_IRQHandler_41(void); +void fabric_f2h_58_e51_local_IRQHandler_42(void); +void fabric_f2h_59_e51_local_IRQHandler_43(void); +void fabric_f2h_60_e51_local_IRQHandler_44(void); +void fabric_f2h_61_e51_local_IRQHandler_45(void); +void fabric_f2h_62_e51_local_IRQHandler_46(void); +void fabric_f2h_63_e51_local_IRQHandler_47(void); + +/* + * U54 + */ +void spare_u54_local_IRQHandler_0(void); +void spare_u54_local_IRQHandler_1(void); +void spare_u54_local_IRQHandler_2(void); + +void mac_mmsl_u54_1_local_IRQHandler_3(void); +void mac_emac_u54_1_local_IRQHandler_4(void); +void mac_queue3_u54_1_local_IRQHandler_5(void); +void mac_queue2_u54_1_local_IRQHandler_6(void); +void mac_queue1_u54_1_local_IRQHandler_7(void); +void mac_int_u54_1_local_IRQHandler_8(void); + +void mac_mmsl_u54_2_local_IRQHandler_3(void); +void mac_emac_u54_2_local_IRQHandler_4(void); +void mac_queue3_u54_2_local_IRQHandler_5(void); +void mac_queue2_u54_2_local_IRQHandler_6(void); +void mac_queue1_u54_2_local_IRQHandler_7(void); +void mac_int_u54_2_local_IRQHandler_8(void); + +void mac_mmsl_u54_3_local_IRQHandler_3(void); +void mac_emac_u54_3_local_IRQHandler_4(void); +void mac_queue3_u54_3_local_IRQHandler_5(void); +void mac_queue2_u54_3_local_IRQHandler_6(void); +void mac_queue1_u54_3_local_IRQHandler_7(void); +void mac_int_u54_3_local_IRQHandler_8(void); + +void mac_mmsl_u54_4_local_IRQHandler_3(void); +void mac_emac_u54_4_local_IRQHandler_4(void); +void mac_queue3_u54_4_local_IRQHandler_5(void); +void mac_queue2_u54_4_local_IRQHandler_6(void); +void mac_queue1_u54_4_local_IRQHandler_7(void); +void mac_int_u54_4_local_IRQHandler_8(void); + +void wdog_tout_u54_h1_local_IRQHandler_9(void); +void wdog_tout_u54_h2_local_IRQHandler_9(void); +void wdog_tout_u54_h3_local_IRQHandler_9(void); +void wdog_tout_u54_h4_local_IRQHandler_9(void); +void mvrp_u54_local_IRQHandler_10(void); +void mmuart_u54_h1_local_IRQHandler_11(void); +void mmuart_u54_h2_local_IRQHandler_11(void); +void mmuart_u54_h3_local_IRQHandler_11(void); +void mmuart_u54_h4_local_IRQHandler_11(void); +void spare_u54_local_IRQHandler_12(void); +void spare_u54_local_IRQHandler_13(void); +void spare_u54_local_IRQHandler_14(void); +void spare_u54_local_IRQHandler_15(void); +void fabric_f2h_0_u54_local_IRQHandler_16(void); +void fabric_f2h_1_u54_local_IRQHandler_17(void); +void fabric_f2h_2_u54_local_IRQHandler_18(void); +void fabric_f2h_3_u54_local_IRQHandler_19(void); +void fabric_f2h_4_u54_local_IRQHandler_20(void); +void fabric_f2h_5_u54_local_IRQHandler_21(void); +void fabric_f2h_6_u54_local_IRQHandler_22(void); +void fabric_f2h_7_u54_local_IRQHandler_23(void); +void fabric_f2h_8_u54_local_IRQHandler_24(void); +void fabric_f2h_9_u54_local_IRQHandler_25(void); +void fabric_f2h_10_u54_local_IRQHandler_26(void); +void fabric_f2h_11_u54_local_IRQHandler_27(void); +void fabric_f2h_12_u54_local_IRQHandler_28(void); +void fabric_f2h_13_u54_local_IRQHandler_29(void); +void fabric_f2h_14_u54_local_IRQHandler_30(void); +void fabric_f2h_15_u54_local_IRQHandler_31(void); +void fabric_f2h_16_u54_local_IRQHandler_32(void); +void fabric_f2h_17_u54_local_IRQHandler_33(void); +void fabric_f2h_18_u54_local_IRQHandler_34(void); +void fabric_f2h_19_u54_local_IRQHandler_35(void); +void fabric_f2h_20_u54_local_IRQHandler_36(void); +void fabric_f2h_21_u54_local_IRQHandler_37(void); +void fabric_f2h_22_u54_local_IRQHandler_38(void); +void fabric_f2h_23_u54_local_IRQHandler_39(void); +void fabric_f2h_24_u54_local_IRQHandler_40(void); +void fabric_f2h_25_u54_local_IRQHandler_41(void); +void fabric_f2h_26_u54_local_IRQHandler_42(void); +void fabric_f2h_27_u54_local_IRQHandler_43(void); +void fabric_f2h_28_u54_local_IRQHandler_44(void); +void fabric_f2h_29_u54_local_IRQHandler_45(void); +void fabric_f2h_30_u54_local_IRQHandler_46(void); +void fabric_f2h_31_u54_local_IRQHandler_47(void); + #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_stubs.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_stubs.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c index 198796b..80d9321 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_stubs.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c @@ -19,8 +19,8 @@ * same prototype in the user's application code. * */ +#include #include -#include "mss_hal.h" #ifdef __cplusplus extern "C" { diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_l2_cache.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.c similarity index 52% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_l2_cache.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.c index 67fed4e..165d9d2 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_l2_cache.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.c @@ -14,112 +14,20 @@ #include #include -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #include "mss_l2_cache.h" /*============================================================================== - * Define describing cache characteristics. + * Local defines */ -#define MAX_WAY_ENABLE 15 -#define NB_SETS 512 -#define NB_BANKS 4 -#define CACHE_BLOCK_BYTE_LENGTH 64 -#define UINT64_BYTE_LENGTH 8 -#define WAY_BYTE_LENGTH (CACHE_BLOCK_BYTE_LENGTH * NB_SETS * NB_BANKS) - -#define ZERO_DEVICE_BOTTOM 0x0A000000ULL -#define ZERO_DEVICE_TOP 0x0C000000ULL - -#define CACHE_CTRL_BASE 0x02010000ULL - -#define INIT_MARKER 0xC0FFEEBEC0010000ULL - +#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) static const uint64_t g_init_marker = INIT_MARKER; - -/*============================================================================== - * Cache controller registers definitions - */ -#define RO volatile const -#define RW volatile -#define WO volatile - -typedef struct { - RO uint8_t BANKS; - RO uint8_t WAYS; - RO uint8_t SETS; - RO uint8_t BYTES; -} CACHE_CONFIG_typedef; - -typedef struct { - CACHE_CONFIG_typedef CONFIG; - RO uint32_t RESERVED; - RW uint8_t WAY_ENABLE; - RO uint8_t RESERVED0[55]; - - WO uint32_t ECC_INJECT_ERROR; - RO uint32_t RESERVED1[47]; - - RO uint64_t ECC_DIR_FIX_ADDR; - RO uint32_t ECC_DIR_FIX_COUNT; - RO uint32_t RESERVED2[13]; - - RO uint64_t ECC_DATA_FIX_ADDR; - RO uint32_t ECC_DATA_FIX_COUNT; - RO uint32_t RESERVED3[5]; - - RO uint64_t ECC_DATA_FAIL_ADDR; - RO uint32_t ECC_DATA_FAIL_COUNT; - RO uint32_t RESERVED4[37]; - - WO uint64_t FLUSH64; - RO uint64_t RESERVED5[7]; - - WO uint32_t FLUSH32; - RO uint32_t RESERVED6[367]; - - RW uint64_t WAY_MASK_DMA; - - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_0; - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_1; - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_2; - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_3; - - RW uint64_t WAY_MASK_E51_DCACHE; - RW uint64_t WAY_MASK_E51_ICACHE; - - RW uint64_t WAY_MASK_U54_1_DCACHE; - RW uint64_t WAY_MASK_U54_1_ICACHE; - - RW uint64_t WAY_MASK_U54_2_DCACHE; - RW uint64_t WAY_MASK_U54_2_ICACHE; - - RW uint64_t WAY_MASK_U54_3_DCACHE; - RW uint64_t WAY_MASK_U54_3_ICACHE; - - RW uint64_t WAY_MASK_U54_4_DCACHE; - RW uint64_t WAY_MASK_U54_4_ICACHE; -} CACHE_CTRL_typedef; - -#define CACHE_CTRL ((CACHE_CTRL_typedef *) CACHE_CTRL_BASE) - +#endif /*============================================================================== * Local functions. */ -static void config_l2_scratchpad(void); -static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start); - -/** - * \brief L2 waymask configuration settings from Libero - * - */ -const uint64_t way_mask_values[] = { - LIBERO_SETTING_WAY_MASK_M0, - LIBERO_SETTING_WAY_MASK_M1, - LIBERO_SETTING_WAY_MASK_M2, - LIBERO_SETTING_WAY_MASK_M3, - LIBERO_SETTING_WAY_MASK_M4 -}; +static void check_config_l2_scratchpad(void); /*============================================================================== @@ -128,16 +36,114 @@ const uint64_t way_mask_values[] = { * - Set the number of cache ways used as cache based on the MSS Configurator * settings. * - Configure some of the enabled ways as scratchpad based on linker - * configuration. + * configuration and space allocated by configurator. */ -void config_l2_cache(void) +__attribute__((weak)) void config_l2_cache(void) { + ASSERT(LIBERO_SETTING_WAY_ENABLE < 16U); + /* * Set the number of ways that will be shared between cache and scratchpad. */ CACHE_CTRL->WAY_ENABLE = LIBERO_SETTING_WAY_ENABLE; - config_l2_scratchpad(); + /* + * shutdown L2 as directed + */ + SYSREG->L2_SHUTDOWN_CR = LIBERO_SETTING_L2_SHUTDOWN_CR; + + /* The scratchpad has already been set-up, first check enough space before copying */ + check_config_l2_scratchpad(); + + /* If you are not using scratchpad, no need to include the following code */ + + ASSERT(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS); + + + + /* + * Compute the mask used to specify ways that will be used by the + * scratchpad. + */ + + uint32_t scratchpad_ways_mask = 0U; +#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) + uint32_t inc; + uint32_t seed_ways_mask = 0x1U << LIBERO_SETTING_WAY_ENABLE; + for(inc = 0; inc < LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS; ++inc) + { + scratchpad_ways_mask |= (seed_ways_mask >> inc) ; + } +#endif + + /* + * Make sure ways are masked if being used as scratchpad + */ + ASSERT((LIBERO_SETTING_WAY_MASK_DMA & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_E51_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_E51_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_1_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_2_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_3_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_4_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_1_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_2_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_3_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_4_ICACHE & scratchpad_ways_mask) == 0UL); + + /* + * Setup all masters, apart from one we are using to setup scratch + */ + CACHE_CTRL->WAY_MASK_DMA = LIBERO_SETTING_WAY_MASK_DMA; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_0; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_1; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_2; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_3; + CACHE_CTRL->WAY_MASK_E51_DCACHE = LIBERO_SETTING_WAY_MASK_E51_ICACHE; + CACHE_CTRL->WAY_MASK_U54_1_DCACHE = LIBERO_SETTING_WAY_MASK_U54_1_DCACHE; + CACHE_CTRL->WAY_MASK_U54_1_ICACHE = LIBERO_SETTING_WAY_MASK_U54_1_ICACHE; + CACHE_CTRL->WAY_MASK_U54_2_DCACHE = LIBERO_SETTING_WAY_MASK_U54_2_DCACHE; + CACHE_CTRL->WAY_MASK_U54_2_ICACHE = LIBERO_SETTING_WAY_MASK_U54_2_ICACHE; + CACHE_CTRL->WAY_MASK_U54_3_DCACHE = LIBERO_SETTING_WAY_MASK_U54_3_DCACHE; + CACHE_CTRL->WAY_MASK_U54_3_ICACHE = LIBERO_SETTING_WAY_MASK_U54_3_ICACHE; + CACHE_CTRL->WAY_MASK_U54_4_DCACHE = LIBERO_SETTING_WAY_MASK_U54_4_DCACHE; + CACHE_CTRL->WAY_MASK_U54_4_ICACHE = LIBERO_SETTING_WAY_MASK_U54_4_ICACHE; + +#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) + /* + * Assign ways to Zero Device + */ + uint64_t * p_scratchpad = (uint64_t *)ZERO_DEVICE_BOTTOM; + uint32_t ways_inc; + uint64_t current_way = 0x1U << (((LIBERO_SETTING_WAY_ENABLE + 1U) - LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS) ); + for(ways_inc = 0; ways_inc < LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS; ++ways_inc) + { + /* + * Populate the scratchpad memory one way at a time. + */ + CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way; + /* + * Write to the first 64-bit location of each cache block. + */ + for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc) + { + *p_scratchpad = g_init_marker + inc; + p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH; + } + current_way = current_way << 1U; + mb(); + } +#endif /* (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) */ + /* + * Prevent E51 from evicting from scratchpad ways. + */ + CACHE_CTRL->WAY_MASK_E51_DCACHE = LIBERO_SETTING_WAY_MASK_E51_DCACHE; + mb(); + } @@ -147,17 +153,22 @@ void config_l2_cache(void) * __l2_scratchpad_vma_end * * These linker symbols specify the start address and length of the scratchpad. - * The scratchpad must be located within the Sero Device memory range. + * The scratchpad must be located within the Zero Device memory range. */ -static void config_l2_scratchpad(void) +static void check_config_l2_scratchpad(void) { extern char __l2_scratchpad_vma_start; extern char __l2_scratchpad_vma_end; + uint8_t n_scratchpad_ways; const uint64_t end = (const uint64_t)&__l2_scratchpad_vma_end; const uint64_t start = (const uint64_t)&__l2_scratchpad_vma_start; uint64_t modulo; + ASSERT(start >= (uint64_t)ZERO_DEVICE_BOTTOM); + ASSERT(end < (uint64_t)ZERO_DEVICE_TOP); + ASSERT(end >= start); + /* * Figure out how many cache ways will be required from linker script * symbols. @@ -169,12 +180,12 @@ static void config_l2_scratchpad(void) ++n_scratchpad_ways; } - if(n_scratchpad_ways > 0) - { - reserve_scratchpad_ways(n_scratchpad_ways, (uint64_t *)start); - } + ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways); } +#if 0 // todo - remove, no longer used + + /*============================================================================== * Reserve a number of cache ways to be used as scratchpad memory. * @@ -192,7 +203,6 @@ static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) uint64_t scratchpad_ways = 0; uint64_t non_scratchpad_ways; uint32_t inc; - int ways_inc; ASSERT(scratchpad_start >= (uint64_t *)ZERO_DEVICE_BOTTOM); ASSERT(scratchpad_start < (uint64_t *)ZERO_DEVICE_TOP); @@ -249,7 +259,7 @@ static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) * Assign ways to Zero Device */ uint64_t * p_scratchpad = scratchpad_start; - + int ways_inc; uint64_t current_way = 1; for(ways_inc = 0; ways_inc < nways; ++ways_inc) { @@ -275,3 +285,4 @@ static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) CACHE_CTRL->WAY_MASK_E51_DCACHE = non_scratchpad_ways; } } +#endif diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.h new file mode 100644 index 0000000..fce9015 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_l2_cache.h @@ -0,0 +1,532 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * @file mss_l2_cache.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief MACROs defines and prototypes associated with L2 Cache + * + */ +#ifndef MSS_L2_CACHE_H +#define MSS_L2_CACHE_H + +#include +#include "encoding.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The following defines will be present in configurator generated xml Q1 2021 + * In the interim, you can manually edit if required. + */ +#if !defined (LIBERO_SETTING_WAY_ENABLE) +/*Way indexes less than or equal to this register value may be used by the +cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave +8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is +128KB. */ +#define LIBERO_SETTING_WAY_ENABLE 0x00000007UL + /* WAY_ENABLE [0:8] RW value= 0x7 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_DMA) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_DMA 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_0) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_1) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_2) +/*Way mask registerAXI slave port 2. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_3) +/*Way mask register AXI slave port 3. Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_DCACHE) +/*Way mask register E51 data cache (hart0). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_ICACHE) +/*Way mask registerE52 instruction cache (hart0). Set field to zero to disable +way from this master. The available cache ways are 0 to number set in +WAY_ENABLE register. If using scratch pad memory, the ways you want reserved +for scrathpad are not available for selection, you must set to 0. e.g. If three +ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set +to zero for all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_DCACHE) +/*Way mask register data cache (hart1). Set field to zero to disable way from +this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_ICACHE) +/*Way mask register instruction cache (hart1). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_DCACHE) +/*Way mask register data cache (hart2). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_ICACHE) +/*Way mask register instruction cache (hart2). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_DCACHE) +/*Way mask register data cache (hart3). Set field to 1 to disable way from this +master.Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_ICACHE) +/*Way mask register instruction cache(hart3). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_DCACHE) +/*Way mask register data cache (hart4). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_ICACHE) +/*Way mask register instruction cache (hart4). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS) +/*Number of ways reserved for scratchpad. Note 1: This is not a register Note +2: each way is 128KB. Note 3: Embedded software expects cache ways allocated +for scratchpad start at way 0, and work up. */ +#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000000UL + /* NUM_OF_WAYS [0:8] RW value= 0x0 */ +#endif + + +#if !defined (LIBERO_SETTING_L2_SHUTDOWN_CR) +/*Number of ways reserved for scratchpad. Note 1: This is not a register Note +2: each way is 128KB. Note 3: Embedded software expects cache ways allocated +for scratchpad start at way 0, and work up. */ +#define LIBERO_SETTING_L2_SHUTDOWN_CR 0x00000000UL + /* NUM_OF_WAYS [0:8] RW value= 0x0 */ +#endif + + + +/*============================================================================== + * Define describing cache characteristics. + */ +#define MAX_WAY_ENABLE 15 +#define NB_SETS 512 +#define NB_BANKS 4 +#define CACHE_BLOCK_BYTE_LENGTH 64 +#define UINT64_BYTE_LENGTH 8 +#define WAY_BYTE_LENGTH (CACHE_BLOCK_BYTE_LENGTH * NB_SETS * NB_BANKS) + +#define ZERO_DEVICE_BOTTOM 0x0A000000ULL +#define ZERO_DEVICE_TOP 0x0C000000ULL + +#define CACHE_CTRL_BASE 0x02010000ULL + +#define INIT_MARKER 0xC0FFEEBEC0010000ULL + +#define SHUTDOWN_CACHE_CC24_00_07_MASK 0x01 +#define SHUTDOWN_CACHE_CC24_08_15_MASK 0x02 +#define SHUTDOWN_CACHE_CC24_16_23_MASK 0x04 +#define SHUTDOWN_CACHE_CC24_24_31_MASK 0x08 + + +/*============================================================================== + * Cache controller registers definitions + */ +#define RO volatile const +#define RW volatile +#define WO volatile + +typedef struct { + RO uint8_t BANKS; + RO uint8_t WAYS; + RO uint8_t SETS; + RO uint8_t BYTES; +} CACHE_CONFIG_typedef; + +typedef struct { + CACHE_CONFIG_typedef CONFIG; + RO uint32_t RESERVED; + RW uint8_t WAY_ENABLE; + RO uint8_t RESERVED0[55]; + + RW uint32_t ECC_INJECT_ERROR; + RO uint32_t RESERVED1[47]; + + RO uint64_t ECC_DIR_FIX_ADDR; + RO uint32_t ECC_DIR_FIX_COUNT; + RO uint32_t RESERVED2[13]; + + RO uint64_t ECC_DATA_FIX_ADDR; + RO uint32_t ECC_DATA_FIX_COUNT; + RO uint32_t RESERVED3[5]; + + RO uint64_t ECC_DATA_FAIL_ADDR; + RO uint32_t ECC_DATA_FAIL_COUNT; + RO uint32_t RESERVED4[37]; + + WO uint64_t FLUSH64; + RO uint64_t RESERVED5[7]; + + WO uint32_t FLUSH32; + RO uint32_t RESERVED6[367]; + + RW uint64_t WAY_MASK_DMA; + + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_0; + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_1; + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_2; + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_3; + + RW uint64_t WAY_MASK_E51_DCACHE; + RW uint64_t WAY_MASK_E51_ICACHE; + + RW uint64_t WAY_MASK_U54_1_DCACHE; + RW uint64_t WAY_MASK_U54_1_ICACHE; + + RW uint64_t WAY_MASK_U54_2_DCACHE; + RW uint64_t WAY_MASK_U54_2_ICACHE; + + RW uint64_t WAY_MASK_U54_3_DCACHE; + RW uint64_t WAY_MASK_U54_3_ICACHE; + + RW uint64_t WAY_MASK_U54_4_DCACHE; + RW uint64_t WAY_MASK_U54_4_ICACHE; +} CACHE_CTRL_typedef; + +#define CACHE_CTRL ((volatile CACHE_CTRL_typedef *) CACHE_CTRL_BASE) + +void config_l2_cache(void); +uint8_t check_num_scratch_ways(uint64_t *start, uint64_t *end); + +#ifdef __cplusplus +} +#endif + +#endif /* MSS_L2_CACHE_H */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_mpu.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mpu.c similarity index 59% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_mpu.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mpu.c index 31491db..5f9c4c7 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_mpu.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mpu.c @@ -18,7 +18,7 @@ *//*=========================================================================*/ #include #include -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #ifndef SIFIVE_HIFIVE_UNLEASHED @@ -178,107 +178,6 @@ const uint64_t mpu_trace_values[] = { LIBERO_SETTING_TRACE_MPU_CFG_PMP1, }; -/** - * \brief PMP configuration from Libero - * - */ -const uint64_t pmp_values[][18] = { - /* hart 0 */ - {LIBERO_SETTING_HART0_CSR_PMPCFG0, - LIBERO_SETTING_HART0_CSR_PMPCFG2, - LIBERO_SETTING_HART0_CSR_PMPADDR0, - LIBERO_SETTING_HART0_CSR_PMPADDR1, - LIBERO_SETTING_HART0_CSR_PMPADDR2, - LIBERO_SETTING_HART0_CSR_PMPADDR3, - LIBERO_SETTING_HART0_CSR_PMPADDR4, - LIBERO_SETTING_HART0_CSR_PMPADDR5, - LIBERO_SETTING_HART0_CSR_PMPADDR6, - LIBERO_SETTING_HART0_CSR_PMPADDR7, - LIBERO_SETTING_HART0_CSR_PMPADDR8, - LIBERO_SETTING_HART0_CSR_PMPADDR9, - LIBERO_SETTING_HART0_CSR_PMPADDR10, - LIBERO_SETTING_HART0_CSR_PMPADDR11, - LIBERO_SETTING_HART0_CSR_PMPADDR12, - LIBERO_SETTING_HART0_CSR_PMPADDR13, - LIBERO_SETTING_HART0_CSR_PMPADDR14, - LIBERO_SETTING_HART0_CSR_PMPADDR15}, - /* hart 1 */ - {LIBERO_SETTING_HART1_CSR_PMPCFG0, - LIBERO_SETTING_HART1_CSR_PMPCFG2, - LIBERO_SETTING_HART1_CSR_PMPADDR0, - LIBERO_SETTING_HART1_CSR_PMPADDR1, - LIBERO_SETTING_HART1_CSR_PMPADDR2, - LIBERO_SETTING_HART1_CSR_PMPADDR3, - LIBERO_SETTING_HART1_CSR_PMPADDR4, - LIBERO_SETTING_HART1_CSR_PMPADDR5, - LIBERO_SETTING_HART1_CSR_PMPADDR6, - LIBERO_SETTING_HART1_CSR_PMPADDR7, - LIBERO_SETTING_HART1_CSR_PMPADDR8, - LIBERO_SETTING_HART1_CSR_PMPADDR9, - LIBERO_SETTING_HART1_CSR_PMPADDR10, - LIBERO_SETTING_HART1_CSR_PMPADDR11, - LIBERO_SETTING_HART1_CSR_PMPADDR12, - LIBERO_SETTING_HART1_CSR_PMPADDR13, - LIBERO_SETTING_HART1_CSR_PMPADDR14, - LIBERO_SETTING_HART1_CSR_PMPADDR15}, - /* hart 2 */ - {LIBERO_SETTING_HART2_CSR_PMPCFG0, - LIBERO_SETTING_HART2_CSR_PMPCFG2, - LIBERO_SETTING_HART2_CSR_PMPADDR0, - LIBERO_SETTING_HART2_CSR_PMPADDR1, - LIBERO_SETTING_HART2_CSR_PMPADDR2, - LIBERO_SETTING_HART2_CSR_PMPADDR3, - LIBERO_SETTING_HART2_CSR_PMPADDR4, - LIBERO_SETTING_HART2_CSR_PMPADDR5, - LIBERO_SETTING_HART2_CSR_PMPADDR6, - LIBERO_SETTING_HART2_CSR_PMPADDR7, - LIBERO_SETTING_HART2_CSR_PMPADDR8, - LIBERO_SETTING_HART2_CSR_PMPADDR9, - LIBERO_SETTING_HART2_CSR_PMPADDR10, - LIBERO_SETTING_HART2_CSR_PMPADDR11, - LIBERO_SETTING_HART2_CSR_PMPADDR12, - LIBERO_SETTING_HART2_CSR_PMPADDR13, - LIBERO_SETTING_HART2_CSR_PMPADDR14, - LIBERO_SETTING_HART2_CSR_PMPADDR15}, - /* hart 3 */ - {LIBERO_SETTING_HART3_CSR_PMPCFG0, - LIBERO_SETTING_HART3_CSR_PMPCFG2, - LIBERO_SETTING_HART3_CSR_PMPADDR0, - LIBERO_SETTING_HART3_CSR_PMPADDR1, - LIBERO_SETTING_HART3_CSR_PMPADDR2, - LIBERO_SETTING_HART3_CSR_PMPADDR3, - LIBERO_SETTING_HART3_CSR_PMPADDR4, - LIBERO_SETTING_HART3_CSR_PMPADDR5, - LIBERO_SETTING_HART3_CSR_PMPADDR6, - LIBERO_SETTING_HART3_CSR_PMPADDR7, - LIBERO_SETTING_HART3_CSR_PMPADDR8, - LIBERO_SETTING_HART3_CSR_PMPADDR9, - LIBERO_SETTING_HART3_CSR_PMPADDR10, - LIBERO_SETTING_HART3_CSR_PMPADDR11, - LIBERO_SETTING_HART3_CSR_PMPADDR12, - LIBERO_SETTING_HART3_CSR_PMPADDR13, - LIBERO_SETTING_HART3_CSR_PMPADDR14, - LIBERO_SETTING_HART3_CSR_PMPADDR15}, - /* hart 4 */ - {LIBERO_SETTING_HART4_CSR_PMPCFG0, - LIBERO_SETTING_HART4_CSR_PMPCFG2, - LIBERO_SETTING_HART4_CSR_PMPADDR0, - LIBERO_SETTING_HART4_CSR_PMPADDR1, - LIBERO_SETTING_HART4_CSR_PMPADDR2, - LIBERO_SETTING_HART4_CSR_PMPADDR3, - LIBERO_SETTING_HART4_CSR_PMPADDR4, - LIBERO_SETTING_HART4_CSR_PMPADDR5, - LIBERO_SETTING_HART4_CSR_PMPADDR6, - LIBERO_SETTING_HART4_CSR_PMPADDR7, - LIBERO_SETTING_HART4_CSR_PMPADDR8, - LIBERO_SETTING_HART4_CSR_PMPADDR9, - LIBERO_SETTING_HART4_CSR_PMPADDR10, - LIBERO_SETTING_HART4_CSR_PMPADDR11, - LIBERO_SETTING_HART4_CSR_PMPADDR12, - LIBERO_SETTING_HART4_CSR_PMPADDR13, - LIBERO_SETTING_HART4_CSR_PMPADDR14, - LIBERO_SETTING_HART4_CSR_PMPADDR15}, -}; /***************************************************************************//** * MSS_MPU_auto_configure() @@ -289,43 +188,43 @@ const uint64_t pmp_values[][18] = { */ uint8_t mpu_configure(void) { - config_copy((void *)(&(MSS_MPU(MSS_MPU_FIC0)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC0)->PMPCFG)), &(mpu_fic0_values), sizeof(mpu_fic0_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_FIC1)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC1)->PMPCFG)), &(mpu_fic1_values), sizeof(mpu_fic1_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_FIC2)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC2)->PMPCFG)), &(mpu_fic2_values), sizeof(mpu_fic2_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_CRYPTO)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_CRYPTO)->PMPCFG)), &(mpu_crypto_values), sizeof(mpu_crypto_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_GEM0)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_GEM0)->PMPCFG)), &(mpu_gem0_values), sizeof(mpu_gem0_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_GEM1)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_GEM1)->PMPCFG)), &(mpu_gem1_values), sizeof(mpu_gem1_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_USB)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_USB)->PMPCFG)), &(mpu_usb_values), sizeof(mpu_usb_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_MMC)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_MMC)->PMPCFG)), &(mpu_mmc_values), sizeof(mpu_mmc_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_SCB)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_SCB)->PMPCFG)), &(mpu_scb_values), sizeof(mpu_scb_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_TRACE)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_TRACE)->PMPCFG)), &(mpu_trace_values), sizeof(mpu_trace_values)); @@ -431,36 +330,6 @@ static uint64_t pmp_get_napot_base_and_range(uint64_t reg, uint64_t *range) #endif -/***************************************************************************//** - * MPU_auto_configure() - * Set MPU's up with configuration from Libero - * - * - * @return - */ -uint8_t pmp_configure(uint8_t hart_id) /* set-up with settings from Libero */ -{ - write_csr(pmpcfg0, pmp_values[hart_id][0]); - write_csr(pmpcfg2, pmp_values[hart_id][1]); - write_csr(pmpaddr0, pmp_values[hart_id][2]); - write_csr(pmpaddr0, pmp_values[hart_id][3]); - write_csr(pmpaddr0, pmp_values[hart_id][4]); - write_csr(pmpaddr0, pmp_values[hart_id][5]); - write_csr(pmpaddr0, pmp_values[hart_id][6]); - write_csr(pmpaddr0, pmp_values[hart_id][7]); - write_csr(pmpaddr0, pmp_values[hart_id][8]); - write_csr(pmpaddr0, pmp_values[hart_id][9]); - write_csr(pmpaddr0, pmp_values[hart_id][10]); - write_csr(pmpaddr0, pmp_values[hart_id][11]); - write_csr(pmpaddr0, pmp_values[hart_id][12]); - write_csr(pmpaddr0, pmp_values[hart_id][13]); - write_csr(pmpaddr0, pmp_values[hart_id][14]); - write_csr(pmpaddr0, pmp_values[hart_id][15]); - write_csr(pmpaddr0, pmp_values[hart_id][16]); - write_csr(pmpaddr0, pmp_values[hart_id][17]); - - return(0); -} #ifdef __cplusplus } diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_mpu.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mpu.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_mpu.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mpu.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mtrap.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mtrap.c similarity index 88% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mtrap.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mtrap.c index d0f5742..150a449 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mtrap.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mtrap.c @@ -9,18 +9,18 @@ /*************************************************************************** * - * @file mtrap.h + * @file mss_mtrap.h * @author Microchip-FPGA Embedded Systems Solutions * @brief trap functions * */ -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #ifdef __cplusplus extern "C" { #endif -static uint64_t g_systick_increment[5] = {0ULL,0ULL,0ULL,0ULL,0ULL}; + void handle_local_interrupt(uint8_t interrupt_no); void handle_m_soft_interrupt(void); @@ -31,7 +31,6 @@ void misaligned_load_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc); void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc); void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc); void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc); -void reset_mtime(void); void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc) @@ -724,164 +723,29 @@ void handle_local_interrupt(uint8_t interrupt_no) #endif } - -/** - * call once at startup - * @return - */ -void reset_mtime(void) -{ -#if ROLLOVER_TEST - CLINT->MTIME = 0xFFFFFFFFFFFFF000ULL; -#else - CLINT->MTIME = 0ULL; -#endif -} - -/** - * Configure system tick - * @return SUCCESS or FAIL - */ -uint32_t SysTick_Config(void) -{ - const uint32_t tick_rate[5] = {HART0_TICK_RATE_MS, HART1_TICK_RATE_MS ,HART2_TICK_RATE_MS ,HART3_TICK_RATE_MS ,HART4_TICK_RATE_MS}; - volatile uint32_t ret_val = ERROR; - - uint64_t mhart_id = read_csr(mhartid); - - /* - * We are assuming the tick rate is in milli-seconds - * - * convert RTC frequency into milliseconds and multiple by the tick rate - * - */ - - g_systick_increment[mhart_id] = ((LIBERO_SETTING_MSS_RTC_TOGGLE_CLK/1000U) * tick_rate[mhart_id]); - - if (g_systick_increment[mhart_id] > 0ULL) - { - - CLINT->MTIMECMP[mhart_id] = CLINT->MTIME + g_systick_increment[mhart_id]; - - set_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ - - __enable_irq(); - - ret_val = SUCCESS; - } - - return (ret_val); -} - -/** - * Disable system tick interrupt - */ -void disable_systick(void) -{ - clear_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ - return; -} - - /*------------------------------------------------------------------------------ - * RISC-V interrupt handler for machine timer interrupts. - */ -void handle_m_timer_interrupt(void) -{ - - volatile uint64_t hart_id = read_csr(mhartid); - volatile uint32_t error_loop; - clear_csr(mie, MIP_MTIP); - - switch(hart_id) - { - case 0U: - SysTick_Handler_h0_IRQHandler(); - break; - case 1U: - SysTick_Handler_h1_IRQHandler(); - break; - case 2U: - SysTick_Handler_h2_IRQHandler(); - break; - case 3U: - SysTick_Handler_h3_IRQHandler(); - break; - case 4U: - SysTick_Handler_h4_IRQHandler(); - break; - default: - while (hart_id != 0U) - { - error_loop++; - } - break; - } - - CLINT->MTIMECMP[read_csr(mhartid)] = CLINT->MTIME + g_systick_increment[hart_id]; - - set_csr(mie, MIP_MTIP); - -} - - -/** * */ -void handle_m_soft_interrupt(void) -{ - volatile uint64_t hart_id = read_csr(mhartid); - volatile uint32_t error_loop; - - switch(hart_id) - { - case 0U: - Software_h0_IRQHandler(); - break; - case 1U: - Software_h1_IRQHandler(); - break; - case 2U: - Software_h2_IRQHandler(); - break; - case 3U: - Software_h3_IRQHandler(); - break; - case 4U: - Software_h4_IRQHandler(); - break; - default: - while (hart_id != 0U) - { - error_loop++; - } - break; - } - - /*Clear software interrupt*/ - clear_soft_interrupt(); -} - void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc) { uintptr_t mcause = read_csr(mcause); - if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) - { - handle_m_ext_interrupt(); - } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U)) + if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U)) { handle_local_interrupt((uint8_t)(mcause & MCAUSE_CAUSE)); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { - handle_m_timer_interrupt(); + handle_m_ext_interrupt(); } else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)) { handle_m_soft_interrupt(); } + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + { + handle_m_timer_interrupt(); + } else { uint32_t i; diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mtrap.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mtrap.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mtrap.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_mtrap.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_l2_cache.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_plic.c similarity index 61% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_l2_cache.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_plic.c index 8e78a57..bd747a8 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_l2_cache.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_plic.c @@ -7,26 +7,23 @@ * */ -/*************************************************************************** - * @file mss_l2_cache.h +/******************************************************************************* + * + * @file mss_plic.c * @author Microchip-FPGA Embedded Systems Solutions - * @brief MACROs defines and prototypes associated with L2 Cache + * @brief MPFS PLIC and PRCI access data structures and functions. + * + * PLIC related data which cannot be placed in mss_plic.h * */ -#ifndef MSS_L2_CACHE_H -#define MSS_L2_CACHE_H - -#include -#include "encoding.h" +#include "mpfs_hal/mss_hal.h" #ifdef __cplusplus extern "C" { #endif -void config_l2_cache(void); +const unsigned long plic_hart_lookup[5U] = {0U, 1U, 3U, 5U, 7U}; #ifdef __cplusplus } #endif - -#endif /* MSS_L2_CACHE_H */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_plic.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_plic.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_plic.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_plic.h index 99c0373..f60f564 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_plic.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_plic.h @@ -694,6 +694,8 @@ typedef struct #define TARGET_OFFSET_HART4_M 7U #define TARGET_OFFSET_HART4_S 8U +extern const unsigned long plic_hart_lookup[5U]; + /***************************************************************************//** * PLIC: Platform Level Interrupt Controller */ @@ -917,9 +919,7 @@ static inline uint32_t PLIC_ClaimIRQ(void) { uint64_t hart_id = read_csr(mhartid); - const unsigned long lookup[5U] = {0U, 1U, 3U, 5U, 7U}; - - return (PLIC->TARGET[lookup[hart_id]].CLAIM_COMPLETE); + return (PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE); } /***************************************************************************//** @@ -930,11 +930,9 @@ static inline void PLIC_CompleteIRQ(uint32_t source) { uint64_t hart_id = read_csr(mhartid); - const unsigned long lookup[5U] = {0U, 1U, 3U, 5U, 7U}; - ASSERT(source <= MAX_PLIC_INT); - PLIC->TARGET[lookup[hart_id]].CLAIM_COMPLETE = source; + PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE = source; } /***************************************************************************//** @@ -952,11 +950,10 @@ static inline void PLIC_CompleteIRQ(uint32_t source) static inline void PLIC_SetPriority_Threshold(uint32_t threshold) { uint64_t hart_id = read_csr(mhartid); - const unsigned long lookup[5U] = {0U, 1U, 3U, 5U, 7U}; ASSERT(threshold <= 7); - PLIC->TARGET[lookup[hart_id]].PRIORITY_THRESHOLD = threshold; + PLIC->TARGET[plic_hart_lookup[hart_id]].PRIORITY_THRESHOLD = threshold; } /***************************************************************************//** diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_pmp.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_pmp.c new file mode 100644 index 0000000..e778f25 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_pmp.c @@ -0,0 +1,159 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ +/******************************************************************************* + * @file mss_mpu.c + * @author Microchip-FPGA Embedded Systems Solutions + * @brief PolarFire SoC MSS MPU driver for configuring access regions for the + * external masters. + * + */ +/*=========================================================================*//** + + *//*=========================================================================*/ +#include +#include +#include "mpfs_hal/mss_hal.h" + +/** + * \brief PMP configuration from Libero + * + */ +const uint64_t pmp_values[][18] = { + /* hart 0 */ + {LIBERO_SETTING_HART0_CSR_PMPCFG0, + LIBERO_SETTING_HART0_CSR_PMPCFG2, + LIBERO_SETTING_HART0_CSR_PMPADDR0, + LIBERO_SETTING_HART0_CSR_PMPADDR1, + LIBERO_SETTING_HART0_CSR_PMPADDR2, + LIBERO_SETTING_HART0_CSR_PMPADDR3, + LIBERO_SETTING_HART0_CSR_PMPADDR4, + LIBERO_SETTING_HART0_CSR_PMPADDR5, + LIBERO_SETTING_HART0_CSR_PMPADDR6, + LIBERO_SETTING_HART0_CSR_PMPADDR7, + LIBERO_SETTING_HART0_CSR_PMPADDR8, + LIBERO_SETTING_HART0_CSR_PMPADDR9, + LIBERO_SETTING_HART0_CSR_PMPADDR10, + LIBERO_SETTING_HART0_CSR_PMPADDR11, + LIBERO_SETTING_HART0_CSR_PMPADDR12, + LIBERO_SETTING_HART0_CSR_PMPADDR13, + LIBERO_SETTING_HART0_CSR_PMPADDR14, + LIBERO_SETTING_HART0_CSR_PMPADDR15}, + /* hart 1 */ + {LIBERO_SETTING_HART1_CSR_PMPCFG0, + LIBERO_SETTING_HART1_CSR_PMPCFG2, + LIBERO_SETTING_HART1_CSR_PMPADDR0, + LIBERO_SETTING_HART1_CSR_PMPADDR1, + LIBERO_SETTING_HART1_CSR_PMPADDR2, + LIBERO_SETTING_HART1_CSR_PMPADDR3, + LIBERO_SETTING_HART1_CSR_PMPADDR4, + LIBERO_SETTING_HART1_CSR_PMPADDR5, + LIBERO_SETTING_HART1_CSR_PMPADDR6, + LIBERO_SETTING_HART1_CSR_PMPADDR7, + LIBERO_SETTING_HART1_CSR_PMPADDR8, + LIBERO_SETTING_HART1_CSR_PMPADDR9, + LIBERO_SETTING_HART1_CSR_PMPADDR10, + LIBERO_SETTING_HART1_CSR_PMPADDR11, + LIBERO_SETTING_HART1_CSR_PMPADDR12, + LIBERO_SETTING_HART1_CSR_PMPADDR13, + LIBERO_SETTING_HART1_CSR_PMPADDR14, + LIBERO_SETTING_HART1_CSR_PMPADDR15}, + /* hart 2 */ + {LIBERO_SETTING_HART2_CSR_PMPCFG0, + LIBERO_SETTING_HART2_CSR_PMPCFG2, + LIBERO_SETTING_HART2_CSR_PMPADDR0, + LIBERO_SETTING_HART2_CSR_PMPADDR1, + LIBERO_SETTING_HART2_CSR_PMPADDR2, + LIBERO_SETTING_HART2_CSR_PMPADDR3, + LIBERO_SETTING_HART2_CSR_PMPADDR4, + LIBERO_SETTING_HART2_CSR_PMPADDR5, + LIBERO_SETTING_HART2_CSR_PMPADDR6, + LIBERO_SETTING_HART2_CSR_PMPADDR7, + LIBERO_SETTING_HART2_CSR_PMPADDR8, + LIBERO_SETTING_HART2_CSR_PMPADDR9, + LIBERO_SETTING_HART2_CSR_PMPADDR10, + LIBERO_SETTING_HART2_CSR_PMPADDR11, + LIBERO_SETTING_HART2_CSR_PMPADDR12, + LIBERO_SETTING_HART2_CSR_PMPADDR13, + LIBERO_SETTING_HART2_CSR_PMPADDR14, + LIBERO_SETTING_HART2_CSR_PMPADDR15}, + /* hart 3 */ + {LIBERO_SETTING_HART3_CSR_PMPCFG0, + LIBERO_SETTING_HART3_CSR_PMPCFG2, + LIBERO_SETTING_HART3_CSR_PMPADDR0, + LIBERO_SETTING_HART3_CSR_PMPADDR1, + LIBERO_SETTING_HART3_CSR_PMPADDR2, + LIBERO_SETTING_HART3_CSR_PMPADDR3, + LIBERO_SETTING_HART3_CSR_PMPADDR4, + LIBERO_SETTING_HART3_CSR_PMPADDR5, + LIBERO_SETTING_HART3_CSR_PMPADDR6, + LIBERO_SETTING_HART3_CSR_PMPADDR7, + LIBERO_SETTING_HART3_CSR_PMPADDR8, + LIBERO_SETTING_HART3_CSR_PMPADDR9, + LIBERO_SETTING_HART3_CSR_PMPADDR10, + LIBERO_SETTING_HART3_CSR_PMPADDR11, + LIBERO_SETTING_HART3_CSR_PMPADDR12, + LIBERO_SETTING_HART3_CSR_PMPADDR13, + LIBERO_SETTING_HART3_CSR_PMPADDR14, + LIBERO_SETTING_HART3_CSR_PMPADDR15}, + /* hart 4 */ + {LIBERO_SETTING_HART4_CSR_PMPCFG0, + LIBERO_SETTING_HART4_CSR_PMPCFG2, + LIBERO_SETTING_HART4_CSR_PMPADDR0, + LIBERO_SETTING_HART4_CSR_PMPADDR1, + LIBERO_SETTING_HART4_CSR_PMPADDR2, + LIBERO_SETTING_HART4_CSR_PMPADDR3, + LIBERO_SETTING_HART4_CSR_PMPADDR4, + LIBERO_SETTING_HART4_CSR_PMPADDR5, + LIBERO_SETTING_HART4_CSR_PMPADDR6, + LIBERO_SETTING_HART4_CSR_PMPADDR7, + LIBERO_SETTING_HART4_CSR_PMPADDR8, + LIBERO_SETTING_HART4_CSR_PMPADDR9, + LIBERO_SETTING_HART4_CSR_PMPADDR10, + LIBERO_SETTING_HART4_CSR_PMPADDR11, + LIBERO_SETTING_HART4_CSR_PMPADDR12, + LIBERO_SETTING_HART4_CSR_PMPADDR13, + LIBERO_SETTING_HART4_CSR_PMPADDR14, + LIBERO_SETTING_HART4_CSR_PMPADDR15}, +}; + +/***************************************************************************//** + * MPU_auto_configure() + * Set MPU's up with configuration from Libero + * + * + * @return + */ +uint8_t pmp_configure(uint8_t hart_id) /* set-up with settings from Libero */ +{ + /* make sure enables are off */ + write_csr(pmpcfg0, 0); + write_csr(pmpcfg2, 0); + /* set required addressing */ + write_csr(pmpaddr0, pmp_values[hart_id][2]); + write_csr(pmpaddr1, pmp_values[hart_id][3]); + write_csr(pmpaddr2, pmp_values[hart_id][4]); + write_csr(pmpaddr3, pmp_values[hart_id][5]); + write_csr(pmpaddr4, pmp_values[hart_id][6]); + write_csr(pmpaddr5, pmp_values[hart_id][7]); + write_csr(pmpaddr6, pmp_values[hart_id][8]); + write_csr(pmpaddr7, pmp_values[hart_id][9]); + write_csr(pmpaddr8, pmp_values[hart_id][10]); + write_csr(pmpaddr9, pmp_values[hart_id][11]); + write_csr(pmpaddr10, pmp_values[hart_id][12]); + write_csr(pmpaddr11, pmp_values[hart_id][13]); + write_csr(pmpaddr12, pmp_values[hart_id][14]); + write_csr(pmpaddr13, pmp_values[hart_id][15]); + write_csr(pmpaddr14, pmp_values[hart_id][16]); + write_csr(pmpaddr15, pmp_values[hart_id][17]); + /* now set the enables */ + write_csr(pmpcfg0, pmp_values[hart_id][0]); + write_csr(pmpcfg2, pmp_values[hart_id][1]); + + return(0); +} diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_prci.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_pmp.h similarity index 50% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_prci.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_pmp.h index f723493..9e085f5 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_prci.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_pmp.h @@ -1,4 +1,4 @@ - /******************************************************************************* +/******************************************************************************* * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT @@ -6,30 +6,30 @@ * MPFS HAL Embedded Software * */ - /******************************************************************************* - * @file mss_prci.h + * @file mss_mpu.h * @author Microchip-FPGA Embedded Systems Solutions - * @brief PRCI: Power, Reset, Clock, Interrupt + * @brief PolarFire SoC MSS MPU driver APIS for configuring access regions for + * the external masters. * */ +/*=========================================================================*//** + + *//*=========================================================================*/ +#ifndef MSS_MPU_H +#define MSS_MPU_H -#ifndef MSS_PRCI_H -#define MSS_PRCI_H #ifdef __cplusplus extern "C" { #endif -/*============================================================================== - * PRCI: Power, Reset, Clock, Interrupt - */ -#define PRCI_BASE 0x10000000UL /* FU540-C000 on unleashed board- 0x10000000UL */ +uint8_t pmp_configure(uint8_t hart_id); #ifdef __cplusplus } #endif -#endif /* MSS_PRCI_H */ +#endif /* MSS_MPU_H */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_seg.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_seg.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_seg.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_seg.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_sysreg.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_sysreg.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_sysreg.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_sysreg.h index e37b6be..3ef4247 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_sysreg.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_sysreg.h @@ -64,8 +64,6 @@ extern "C" { cture member permissions */ #endif -#include "mss_peripheral_base_add.h" - /* Defines all Top Register offsets*/ /* Date of Source Revision File: 12-Jul-18*/ /* PROTOCOL=MSS; BASE=32'h20012000*/ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_util.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_util.c similarity index 83% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_util.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_util.c index afe40e4..f1e2ea2 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_util.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_util.c @@ -15,7 +15,7 @@ */ #include #include -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #ifdef __cplusplus extern "C" { @@ -91,46 +91,6 @@ void __disable_local_irq(uint8_t local_interrupt) } } -/* - * Functions - */ -uint64_t readmtime(void) -{ - volatile uint64_t hartid = read_csr(mhartid); - volatile uint64_t * mtime_hart = NULL; - uint64_t mtime = 0ULL; - - switch(hartid) { - case 0: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H0; - break; - - case 1: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H1; - break; - - case 2: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H2; - break; - - case 3: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H3; - break; - - case 4: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H4; - break; - - default: - return (0ULL); - break; - } - - mtime = *mtime_hart; - return (mtime); -} - - uint64_t readmcycle(void) { return (read_csr(mcycle)); diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_util.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_util.h similarity index 96% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_util.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_util.h index 3f052cb..ea20c2a 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_util.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/mss_util.h @@ -24,8 +24,6 @@ extern "C" { #endif -#define DDR_BASE (0x80000000ul) - /* * Useful macros */ @@ -38,8 +36,10 @@ extern "C" { #define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y)) #define READ_REG64(x) (*((volatile uint64_t *)(x))) +/* + * return mcycle + */ uint64_t readmcycle(void); -uint64_t readmtime(void); void sleep_ms(uint64_t msecs); void sleep_cycles(uint64_t ncycles); diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_cfm.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.c similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_cfm.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.c index 61e6633..e81f08d 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_cfm.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.c @@ -11,8 +11,7 @@ #include #include -#include "../../mpfs_hal/mss_hal.h" - +#include "mpfs_hal/mss_hal.h" #include "mss_cfm.h" diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_cfm.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_cfm.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_cfm.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.c similarity index 97% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.c index f3277bd..8063bf8 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr.c @@ -13,10 +13,10 @@ * @brief DDR related code * */ -#include "mpfs_hal/mss_hal.h" -#ifdef DDR_SUPPORT #include #include +#include "mpfs_hal/mss_hal.h" +#ifdef DDR_SUPPORT #include "mss_ddr_debug.h" #include "simulation.h" @@ -24,8 +24,16 @@ * Local Defines */ /* This string is updated if any change to ddr driver */ -#define DDR_DRIVER_VERSION_STRING "0.0.013" +#define DDR_DRIVER_VERSION_STRING "0.1.004" /* Version | Change */ +/* 0.1.004 | Corrected default RPC220 setting so dq/dqs window centred */ +/* 0.1.003 | refclk_phase correctly masked during bclk sclk sw training */ +/* 0.1.002 | Reset modified- corrects softreset on retry issue (1.8.x) */ +/* 0.1.001 | Reset modified- corrects softreset on retry issue (1.7.2) */ +/* 0.0.016 | Added #define DDR_FULL_32BIT_NC_CHECK_EN to mss_ddr.h */ +/* 0.0.016 | updated mss_ddr_debug.c with additio of 32-bit write test */ +/* 0.0.015 | DDR3L - Use Software Bclk Sclk training */ +/* 0.0.014 | DDR3 and DDR update to sync with SVG proven golden version */ /* 0.0.013 | Added code to turn off DM if DDR4 and using ECC */ /* 0.0.012 | Added support for turning off unused I/O from Libero */ @@ -107,12 +115,7 @@ static uint8_t get_best_sweep(sweep_index *good_index); * External function declarations */ extern void delay(uint32_t n); -#ifdef DDR_FULL_32BIT_NC_CHECK_EN -#ifndef HSS -extern uint32_t ddr_read_write_fn (uint64_t* DDR_word_ptr, uint32_t no_access,\ - uint32_t pattern); -#endif -#endif + #ifdef DEBUG_DDR_INIT extern mss_uart_instance_t *g_debug_uart; #ifdef DEBUG_DDR_DDRCFG @@ -220,7 +223,8 @@ static uint32_t ddr_setup(void) #endif ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + //config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); // config_copy((uint8_t *)&sweep_results[0U][0U][0U][0U][0U],0U, sizeof(sweep_results)); retry_count = 0U; #ifdef DEBUG_DDR_INIT @@ -415,7 +419,7 @@ static uint32_t ddr_setup(void) } ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x0U; /* reset controller */ DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; @@ -424,7 +428,7 @@ static uint32_t ddr_setup(void) #else /* we are not SWEEP_ENABLED */ ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x0U; /* reset controller */ DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; @@ -499,7 +503,7 @@ static uint32_t ddr_setup(void) */ ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x00000000U; /* reset controller */ DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x00000000U; @@ -758,26 +762,31 @@ static uint32_t ddr_setup(void) /* To verify if separate reset required for DDR4 - believe it is not */ #ifndef SPECIAL_TRAINIG_RESET CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; - +#ifndef SOFT_RESET_PRE_TAG_172 + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ + 0x00000000U; + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ + 0x00000001U; +#endif /* !SOFT_RESET_PRE_TAG_172 */ #else - /* Disable CKE */ - DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; - - /* Assert FORCE_RESET */ - DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; - delay(100); - /* release reset to memory here, set INIT_FORCE_RESET to 0 */ - DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; - delay(500000); - - /* Enable CKE */ - DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; - delay(1000); - + /* Disable CKE */ + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; + + /* Assert FORCE_RESET */ + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; + delay(100); + /* release reset to memory here, set INIT_FORCE_RESET to 0 */ + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; + delay(500000); + + /* Enable CKE */ + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; + delay(1000); + /* reset pin is bit [1] */ CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; -#endif +#endif ddr_training_state = DDR_TRAINING_ROTATE_CLK; break; case DDR_TRAINING_ROTATE_CLK: @@ -893,8 +902,10 @@ static uint32_t ddr_setup(void) /* * Initiate software training */ +#ifdef SOFT_RESET_PRE_TAG_172 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ 0x00000001U; +#endif ddr_training_state = DDR_TRAINING_IP_SM_BCLKSCLK_SW; } else @@ -903,10 +914,16 @@ static uint32_t ddr_setup(void) * Initiate IP training and wait for dfi_init_complete */ /*asserting training_reset */ - - CFG_DDR_SGMII_PHY->training_reset.training_reset =\ + if (ddr_type != DDR3) + { + CFG_DDR_SGMII_PHY->training_reset.training_reset =\ 0x00000000U; - + } + else + { + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ + 0x00000001U; + } ddr_training_state = DDR_TRAINING_IP_SM_START; } } @@ -982,7 +999,7 @@ static uint32_t ddr_setup(void) * refclk phase offset manually * We may need to sweep this */ - refclk_phase = (uint32_t)((answer+SW_TRAING_BCLK_SCLK_OFFSET + 5U + LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET ) << 2U); + refclk_phase = (uint32_t)(((answer+SW_TRAING_BCLK_SCLK_OFFSET + 5U + LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET ) & 0x07UL) << 2U); bclk_phase = ((answer+SW_TRAING_BCLK_SCLK_OFFSET) & 0x07UL ) << 8U; bclk90_phase= ((answer+SW_TRAING_BCLK_SCLK_OFFSET+2U) & 0x07UL ) << 11U; MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); @@ -1016,9 +1033,9 @@ static uint32_t ddr_setup(void) CFG_DDR_SGMII_PHY->rpc168.rpc168 = 0x0U; } #ifdef DDR_TRAINING_IP_SM_START_DELAY - delay(100); + delay(100); #endif - /* release reset to training */ + /* release reset to training */ CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000000U; #ifdef IP_SM_START_TRAINING_PAUSE /* todo: pause removed at Alister's request for test. Will @@ -1102,6 +1119,7 @@ static uint32_t ddr_setup(void) } else if(CFG_DDR_SGMII_PHY->training_status.training_status & ADDCMD_BIT) { + timeout = 0xFFFFF; ddr_training_state = DDR_TRAINING_IP_SM_WRLVL; } if(--timeout == 0U) @@ -1130,6 +1148,7 @@ static uint32_t ddr_setup(void) } else if(CFG_DDR_SGMII_PHY->training_status.training_status & WRLVL_BIT) { + timeout = 0xFFFFF; ddr_training_state = DDR_TRAINING_IP_SM_RDGATE; } if(--timeout == 0U) @@ -1245,7 +1264,7 @@ static uint32_t ddr_setup(void) } /* Check that DQ/DQS calculated window is above 5 taps. */ if(CFG_DDR_SGMII_PHY->dqdqs_status1.dqdqs_status1 < \ - DQ_DQS_NUM_TAPS) + DQ_DQS_NUM_TAPS) { t_status = t_status | 0x01U; } @@ -1260,16 +1279,16 @@ static uint32_t ddr_setup(void) /* * We can now set vref on the memory * mode register for lpddr4 - * May include other modes, and include a sweep - * Alister looking into this and will revert. + * May include other modes, and include a sweep + * Alister looking into this and will revert. */ if (ddr_type == LPDDR4) - { + { #ifdef SET_VREF_LPDDR4_MODE_REGS - mode_register_write(DDR_MODE_REG_VREF,\ + mode_register_write(DDR_MODE_REG_VREF,\ DDR_MODE_REG_VREF_VALUE); #endif - } + } ddr_training_state = DDR_TRAINING_SET_FINAL_MODE; } else /* fail, try again */ @@ -1328,6 +1347,8 @@ static uint32_t ddr_setup(void) if (ddr_type == LPDDR4) { uint8_t lane; + /* Changed default value to centre dq/dqs on window */ + CFG_DDR_SGMII_PHY->rpc220.rpc220 = 0xCUL; for(lane = 0U; lane < number_of_lanes_to_calibrate; lane++) { load_dq(lane); @@ -1339,11 +1360,11 @@ static uint32_t ddr_setup(void) write_calibration_lpddr4_using_mtc(\ number_of_lanes_to_calibrate); #else - error =\ + error =\ write_calibration_using_mtc(\ number_of_lanes_to_calibrate); -#endif - } +#endif + } else { SIM_FEEDBACK1(2U); @@ -1379,7 +1400,7 @@ static uint32_t ddr_setup(void) /* * Clear write calibration data */ - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); /* * Try the next offset */ @@ -1416,9 +1437,9 @@ static uint32_t ddr_setup(void) case DDR_SANITY_CHECKS: //setup_ddr_segments(); //todo: create state here, as no need to do further up - // Also, sw should set with default values here to allow full memory range check - // on non cached and cached as we are doing now - // and set to Libero values once DDR write/read verified + // Also, sw should set with default values here to allow full memory range check + // on non cached and cached as we are doing now + // and set to Libero values once DDR write/read verified /* * Now start the write calibration if training successful */ @@ -1458,11 +1479,11 @@ static uint32_t ddr_setup(void) * write and read back test from drr, non cached access */ { -#ifdef DDR_FULL_32BIT_NC_CHECK_EN +#if (DDR_FULL_32BIT_NC_CHECK_EN == 1) #ifndef HSS - error = ddr_read_write_fn((uint64_t*)MSS_BASE_ADD_DRC_NC,\ + error = ddr_read_write_fn((uint64_t*)LIBERO_SETTING_DDR_64_NON_CACHE,\ SW_CFG_NUM_READS_WRITES,\ - SW_CONFIG_PATTERN); + SW_CONFIG_PATTERN); #else bool HSS_MemTestDDRFast(void); #endif @@ -1572,7 +1593,7 @@ static uint32_t ddr_setup(void) */ #ifdef DEBUG_DDR_INIT { - tip_register_status (g_debug_uart); + tip_register_status (g_debug_uart); (void)uprint32(g_debug_uart, "\n\r\n\r DDR_TRAINING_PASS: ",\ ddr_training_state); (void)uprint32(g_debug_uart, "\n ****************************************************", 0); @@ -1873,18 +1894,18 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type) /* * If this define is not present, indicates older * Libero core (pre 2.0.109) - * So we run this code + * So we run this code */ CFG_DDR_SGMII_PHY->ovrt10.ovrt10 =\ LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10; - { - /* Use pull-ups to set the CMD/ADD ODT */ + { + /* Use pull-ups to set the CMD/ADD ODT */ CFG_DDR_SGMII_PHY->rpc245.rpc245 =\ - 0x00000000; + 0x00000000; CFG_DDR_SGMII_PHY->rpc237.rpc237 =\ - 0xffffffff; - } + 0xffffffff; + } /* OVRT_EN_ADDCMD2 (default 0xE06), register named ovrt12 */ CFG_DDR_SGMII_PHY->ovrt11.ovrt11 =\ @@ -2810,15 +2831,15 @@ static uint8_t \ for (laneToTest = 0x00U; laneToTest #include #include #include "mpfs_hal/mss_hal.h" -#include "mss_ddr_debug.h" /******************************************************************************* * Local Defines @@ -36,6 +36,9 @@ extern uint8_t sweep_results[MAX_NUMBER_DPC_VS_GEN_SWEEPS]\ [MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS]; #endif #endif +#ifdef DEBUG_DDR_INIT +extern mss_uart_instance_t *g_debug_uart; +#endif /******************************************************************************* * External function declarations @@ -46,12 +49,16 @@ extern void delay(uint32_t n); * Local function declarations */ static uint32_t ddr_write ( volatile uint64_t *DDR_word_ptr,\ - uint32_t no_of_access, uint8_t data_ptrn ); + uint32_t no_of_access, uint8_t data_ptrn, DDR_ACCESS_SIZE data_size ); static uint32_t ddr_read ( volatile uint64_t *DDR_word_ptr,\ - uint32_t no_of_access, uint8_t data_ptrn ); -#ifdef DEBUG_DDR_INIT -extern mss_uart_instance_t *g_debug_uart; -#endif + uint32_t no_of_access, uint8_t data_ptrn, DDR_ACCESS_SIZE data_size ); + + +__attribute__((weak)) int rand(void) +{ + return 0; +} + #ifdef DEBUG_DDR_INIT /***************************************************************************//** @@ -165,13 +172,18 @@ static uint32_t ddr_write ( volatile uint64_t *DDR_word_ptr, uint32_t no_of_access, - uint8_t data_ptrn + uint8_t data_ptrn, + DDR_ACCESS_SIZE data_size ) { uint32_t i; uint64_t DATA; uint32_t error_count = 0U; + uint32_t *DDR_32_ptr = (uint32_t *)DDR_word_ptr; + uint16_t *DDR_16_ptr = (uint16_t *)DDR_word_ptr; + uint8_t *DDR_8_ptr = (uint8_t *)DDR_word_ptr; + switch (data_ptrn) { case PATTERN_INCREMENTAL : DATA = 0x00000000; break; @@ -197,8 +209,30 @@ static uint32_t ddr_write for( i = 0; i< (no_of_access); i++) { - *DDR_word_ptr = DATA; - DDR_word_ptr = DDR_word_ptr + 1; + switch(data_size) + { + case DDR_8_BIT: + DATA &= 0xFFUL; + *DDR_8_ptr = (uint8_t)DATA; + DDR_8_ptr = DDR_8_ptr + 1; + break; + case DDR_16_BIT: + DATA &= 0xFFFFUL; + *DDR_16_ptr = (uint16_t)DATA; + DDR_16_ptr = DDR_16_ptr + 1; + break; + case DDR_32_BIT: + DATA &= 0xFFFFFFFFUL; + *DDR_32_ptr = (uint32_t)DATA; + DDR_32_ptr = DDR_32_ptr + 1; + break; + default: + case DDR_64_BIT: + *DDR_word_ptr = DATA; + DDR_word_ptr = DDR_word_ptr + 1; + break; + } + #ifdef DEBUG_DDR_INIT if((i%0x1000000UL) ==0UL) { @@ -254,7 +288,8 @@ uint32_t ddr_read ( volatile uint64_t *DDR_word_ptr, uint32_t no_of_access, - uint8_t data_ptrn + uint8_t data_ptrn, + DDR_ACCESS_SIZE data_size ) { uint32_t i; @@ -263,9 +298,16 @@ uint32_t ddr_read volatile uint64_t ddr_data; volatile uint64_t *DDR_word_pt_t, *first_DDR_word_pt_t; uint32_t rand_addr_offset; + uint8_t *DDR_8_pt_t; + uint16_t *DDR_16_pt_t; + uint32_t *DDR_32_pt_t; err_cnt = 0U; first_DDR_word_pt_t = DDR_word_ptr; + DDR_8_pt_t = (uint8_t *)DDR_word_ptr; + DDR_16_pt_t = (uint16_t *)DDR_word_ptr; + DDR_32_pt_t = (uint32_t *)DDR_word_ptr; + switch (data_ptrn) { case PATTERN_INCREMENTAL : DATA = 0x00000000; break; @@ -275,6 +317,9 @@ uint32_t ddr_read case PATTERN_RANDOM : DATA = (uint64_t)rand ( ); *DDR_word_ptr = DATA; + *DDR_8_pt_t = (uint8_t)DATA; + *DDR_16_pt_t = (uint16_t)DATA; + *DDR_32_pt_t = (uint32_t)DATA; break; case PATTERN_0xCCCCCCCC : DATA = 0xCCCCCCCCCCCCCCCC; @@ -295,8 +340,26 @@ uint32_t ddr_read } for( i = 0; i< (no_of_access); i++) { - DDR_word_pt_t = DDR_word_ptr; - ddr_data = *DDR_word_pt_t; + switch(data_size) + { + case DDR_8_BIT: + DATA &= 0xFFUL; + ddr_data = *DDR_8_pt_t; + break; + case DDR_16_BIT: + DATA &= 0xFFFFUL; + ddr_data = *DDR_16_pt_t; + break; + case DDR_32_BIT: + DATA &= 0xFFFFFFFFUL; + ddr_data = *DDR_32_pt_t; + break; + default: + case DDR_64_BIT: + DDR_word_pt_t = DDR_word_ptr; + ddr_data = *DDR_word_pt_t; + break; + } #ifdef DEBUG_DDR_INIT if((i%0x1000000UL) ==0UL) @@ -333,6 +396,9 @@ uint32_t ddr_read #endif } DDR_word_ptr = DDR_word_ptr + 1U; + DDR_8_pt_t = DDR_8_pt_t +1U; + DDR_16_pt_t = DDR_16_pt_t +1U; + DDR_32_pt_t = DDR_32_pt_t +1U; switch (data_ptrn) { case PATTERN_INCREMENTAL : DATA = DATA + 0x01; break; @@ -358,7 +424,13 @@ uint32_t ddr_read DATA = (uint64_t)rand ( ); rand_addr_offset = (uint32_t)(rand() & 0xFFFFCUL); DDR_word_ptr = first_DDR_word_pt_t + rand_addr_offset; - *DDR_word_ptr = DATA; + DDR_8_pt_t = (uint8_t *)(first_DDR_word_pt_t + rand_addr_offset); + DDR_16_pt_t = (uint16_t *)(first_DDR_word_pt_t + rand_addr_offset); + DDR_32_pt_t = (uint32_t *)(first_DDR_word_pt_t + rand_addr_offset); + *DDR_word_ptr = DATA; + *DDR_8_pt_t = (uint8_t)DATA; + *DDR_16_pt_t = (uint16_t)DATA; + *DDR_32_pt_t = (uint32_t)DATA; break; case PATTERN_0xCCCCCCCC : DATA = 0xCCCCCCCCCCCCCCCC; @@ -399,12 +471,24 @@ uint32_t ddr_read_write_fn (uint64_t* DDR_word_ptr, uint32_t no_access,\ #ifdef DEBUG_DDR_INIT uprint32(g_debug_uart,"\n\r\t Pattern: 0x", pattern_shift); #endif + +#if TEST_64BIT_ACCESS == 1 /* write the pattern */ error_cnt += ddr_write ((uint64_t *)DDR_word_ptr,\ - no_access, pattern_mask); + no_access, pattern_mask, DDR_64_BIT); /* read back and verifies */ error_cnt += ddr_read ((uint64_t *)DDR_word_ptr, \ - no_access, pattern_mask); + no_access, pattern_mask, DDR_64_BIT); +#endif + +#if TEST_32BIT_ACCESS == 1 + /* write the pattern */ + error_cnt += ddr_write ((uint64_t *)DDR_word_ptr,\ + no_access, pattern_mask, DDR_32_BIT); + /* read back and verifies */ + error_cnt += ddr_read ((uint64_t *)DDR_word_ptr, \ + no_access, pattern_mask, DDR_32_BIT); +#endif } } DDR_word_ptr++; /* increment the address */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_debug.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h similarity index 94% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_debug.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h index 3bd1f05..e8cf430 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_debug.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h @@ -40,13 +40,29 @@ #define __MSS_DDr_DEBUG_H_ 1 #ifdef DEBUG_DDR_INIT -#include "drivers/mss_uart/mss_uart.h" +#include "drivers/mss_mmuart/mss_uart.h" #endif #ifdef __cplusplus extern "C" { #endif +#ifndef TEST_64BIT_ACCESS +#define TEST_64BIT_ACCESS 1 +#endif + +#ifndef TEST_32BIT_ACCESS +#define TEST_32BIT_ACCESS 1 +#endif + +typedef enum DDR_ACCESS_SIZE_ +{ + DDR_8_BIT, + DDR_16_BIT, + DDR_32_BIT, + DDR_64_BIT +} DDR_ACCESS_SIZE; + /***************************************************************************//** The ddr_read_write_fn function is used to write/read test patterns to the DDR diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_defs.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_defs.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_sgmii_phy_defs.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_sgmii_phy_defs.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_sgmii_phy_defs.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_sgmii_phy_defs.h index 25d440d..3f0710d 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_sgmii_phy_defs.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_ddr_sgmii_phy_defs.h @@ -19,7 +19,7 @@ #define MSS_DDR_SGMII_PHY_DEFS_H_ -#include "mpfs_hal/mss_hal.h" +#include #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_io.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_io.c similarity index 97% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_io.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_io.c index cf7e0e2..c040578 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_io.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_io.c @@ -13,14 +13,14 @@ * @brief MSS IO related code * */ +#include #include #include -#include "mpfs_hal/mss_hal.h" /******************************************************************************* * external functions */ -extern g5_mss_top_scb_regs_TypeDef *SCB_REGS; + /* * IOMUX values from Libero @@ -154,7 +154,7 @@ static uint8_t io_mux_and_bank_config(void) * entry to the IOMUX structure * * */ - config_copy((void *)(&(SYSREG->IOMUX0_CR)), + config_32_copy((void *)(&(SYSREG->IOMUX0_CR)), &(iomux_config_values), sizeof(IOMUX_CONFIG)); @@ -186,11 +186,11 @@ static uint8_t io_mux_and_bank_config(void) | io_cfg_lp_bypass_en |14 | | * */ - config_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), + config_32_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), &(mssio_bank4_io_config), sizeof(MSSIO_BANK4_CONFIG)); - config_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), + config_32_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), &(mssio_bank2_io_config), sizeof(MSSIO_BANK2_CONFIG)); diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_io_config.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_io_config.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_io_config.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_io_config.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_nwc_init.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c similarity index 98% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_nwc_init.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c index b965195..03e186b 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_nwc_init.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c @@ -16,13 +16,12 @@ #include #include - #include "mpfs_hal/mss_hal.h" #include "mss_nwc_init.h" #include "simulation.h" #ifdef DEBUG_DDR_INIT -#include "drivers/mss_uart/mss_uart.h" +#include "drivers/mss_mmuart/mss_uart.h" extern mss_uart_instance_t *g_debug_uart ; uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); #endif @@ -48,13 +47,8 @@ void delay(uint32_t n); /******************************************************************************* * extern defined functions */ -extern void delay(uint32_t n); #ifndef SIFIVE_HIFIVE_UNLEASHED extern void mss_pll_config(void); -extern uint32_t sgmii_setup(void); -#ifdef MSSIO_SUPPORT -extern uint8_t mssio_setup(void); -#endif #endif #ifdef DEBUG_DDR_INIT uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); @@ -63,8 +57,6 @@ uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); /****************************************************************************** * Public Functions - API ******************************************************************************/ -uint8_t mss_nwc_init(void); - /** * MSS_DDR_init_simulation(void) diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_nwc_init.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_nwc_init.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_pll.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.c similarity index 97% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_pll.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.c index e5257a0..202b96f 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_pll.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.c @@ -65,7 +65,7 @@ static void copy_switch_code(void); * Public Functions - API * ******************************************************************************/ void mss_pll_config(void); - +void sgmii_mux_config(uint8_t option); /******************************************************************************* Local functions * @@ -302,11 +302,11 @@ __attribute__((section(".ram_codetext"))) \ } /***************************************************************************//** - * sgmii_mux_config_via_scb(uint8_t option) + * sgmii_mux_config(uint8_t option) * @param option 1 => soft reset, load RPC settings * 0 => write values using SCB ******************************************************************************/ -void sgmii_mux_config_via_scb(uint8_t option) +void sgmii_mux_config(uint8_t option) { switch(option) { @@ -321,7 +321,7 @@ void sgmii_mux_config_via_scb(uint8_t option) */ /* CFM_ETH - 0x3E200000 - - 0x08 */ MSS_SCB_CFM_SGMII_MUX->SGMII_CLKMUX =\ - LIBERO_SETTING_SGMII_SGMII_CLKMUX; + LIBERO_SETTING_SGMII_SGMII_CLKMUX; /* * SCB address: 0x3E20 0010 * Clock_Receiver @@ -360,7 +360,7 @@ void sgmii_mux_config_via_scb(uint8_t option) */ /* 0x05 => ref to SGMII and DDR */ MSS_SCB_CFM_SGMII_MUX->RFCKMUX =\ - LIBERO_SETTING_SGMII_SGMII_CLKMUX; + LIBERO_SETTING_SGMII_REFCLKMUX; break; case RPC_REG_UPDATE: @@ -373,18 +373,6 @@ void sgmii_mux_config_via_scb(uint8_t option) } } - -/***************************************************************************//** - * sgmii_mux_config_via_scb(option) - * @param option 1 => soft reset, load RPC settings - * 0 => write values using SCB - ******************************************************************************/ -void pre_configure_sgmii_and_ddr_pll_via_scb(uint8_t option) -{ - sgmii_mux_config_via_scb(option); -} - - /***************************************************************************//** * * On startup, MSS supplied with 80MHz SCB clock @@ -584,7 +572,7 @@ void ddr_pll_config(REG_LOAD_METHOD option) * CFG_DDR_SGMII_PHY->PLL_CAL_MAIN.PLL_CAL_MAIN =\ * LIBERO_SETTING_DDR_PLL_CAL; */ CFG_DDR_SGMII_PHY->PLL_PHADJ_MAIN.PLL_PHADJ_MAIN =\ - LIBERO_SETTING_MSS_PLL_PHADJ; + LIBERO_SETTING_DDR_PLL_PHADJ; /*__I CFG_DDR_SGMII_PHY_SSCG_REG_0_MAIN_TypeDef SSCG_REG_0_MAIN; */ /*__I CFG_DDR_SGMII_PHY_SSCG_REG_1_MAIN_TypeDef SSCG_REG_1_MAIN; */ CFG_DDR_SGMII_PHY->SSCG_REG_2_MAIN.SSCG_REG_2_MAIN =\ @@ -679,7 +667,7 @@ void sgmii_pll_config_scb(uint8_t option) /* PLL phase registers */ - MSS_SCB_SGMII_PLL->PLL_PHADJ = LIBERO_SETTING_MSS_PLL_PHADJ; + MSS_SCB_SGMII_PLL->PLL_PHADJ = LIBERO_SETTING_SGMII_PLL_PHADJ; MSS_SCB_SGMII_PLL->PLL_CTRL = (LIBERO_SETTING_SGMII_PLL_CTRL)\ | 0x01U; /* bit 0 == REG_POWERDOWN_B */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_pll.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_pll.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_pll.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_scb_nwc_regs.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_scb_nwc_regs.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h index fe58e91..77aa5ea 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_scb_nwc_regs.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h @@ -17,7 +17,7 @@ #ifndef MSS_DDR_SGMII_MSS_SCB_NWC_REGS_H_ #define MSS_DDR_SGMII_MSS_SCB_NWC_REGS_H_ -#include "mpfs_hal/mss_hal.h" +#include #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_sgmii.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.c similarity index 98% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_sgmii.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.c index d93ca4b..47a79da 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_sgmii.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.c @@ -23,12 +23,14 @@ * local functions */ static void setup_sgmii_rpc_per_config(void); +#ifdef SGMII_SUPPORT static uint32_t sgmii_channel_setup(void); +#endif /* * extern functions */ -extern void pre_configure_sgmii_and_ddr_pll_via_scb(uint8_t option); +extern void sgmii_mux_config(uint8_t option); uint32_t sgmii_setup(void) @@ -44,15 +46,13 @@ uint32_t sgmii_setup(void) } else { - pre_configure_sgmii_and_ddr_pll_via_scb(0U); /* 0U => configure - using the SCB */ sgmii_off_mode(); + sgmii_mux_config(RPC_REG_UPDATE); } #else { - pre_configure_sgmii_and_ddr_pll_via_scb(0U); /* 0U => configure - using the SCB */ sgmii_off_mode(); + sgmii_mux_config(RPC_REG_UPDATE); } #endif return(0UL); @@ -64,6 +64,7 @@ uint32_t sgmii_setup(void) * @param sgmii_instruction * @return */ +#ifdef SGMII_SUPPORT static uint32_t sgmii_channel_setup(void) { /* @@ -283,7 +284,7 @@ static uint32_t sgmii_channel_setup(void) */ SIM_FEEDBACK1(9U); /* 0U => configure using scb, 1U => NVMAP reset */ - pre_configure_sgmii_and_ddr_pll_via_scb(1U); + sgmii_mux_config(RPC_REG_UPDATE); SIM_FEEDBACK1(10U); /* 0U => configure using scb, 1U => NVMAP reset */ sgmii_pll_config_scb(1U); @@ -398,7 +399,7 @@ static uint32_t sgmii_channel_setup(void) return(0U); } - +#endif /** * setup_sgmii_rpc_per_config diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_sgmii.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_sgmii.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/mss_sgmii.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/readme.md b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/readme.md similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/readme.md rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/readme.md diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/simulation.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/simulation.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/simulation.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/nwc/simulation.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/readme.md b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/readme.md new file mode 100644 index 0000000..f2ad581 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/common/readme.md @@ -0,0 +1,121 @@ +=============================================================================== +# mpfs_hal +=============================================================================== + +The PolarFire-SoC MSS HAL provides the initial boot code, interrupt handling, +and hardware access methods for the MPFS MSS. The terms PolarFire-SoC HAL and +MPFS HAL are used interchangeably but in the main the term PolarFire-SoC MSS HAL +is preferred. +The PolarFire-SoC MSS hal is a combination of C and assembly source code. + +The mpfs_hal folder is included in an PolarFire Embedded project under the +platform directory. + +It contains : + +* Start-up code executing from reset +* Interrupt handling support +* Exception handling support +* Memory protection configuration, PMP and MPU +* DDR configuration +* SGMII configuration +* MSSIO setup + +## Inputs to the mss_hal +There are two configuration sources. + +1. Libero design + + Libero input through header files located in the config/hardware under the + platform directory. These files are generated using the PF SoC embedded + software configuration generator. It takes an xml file generated in the Libero + design flow and produces header files based on the xml content in a suitable + form for consumption by the hal. + +2. Software configuration + Software configuration settings are located in the mpfs_hal_config folder. + + +### Example Project directory structure, showing where mpfs_hal folder sits. + +~~~~ + + +---------+ + | project | + +----+----+ +---------+ +-----------+ + +-----+| src |----->|application| + +---------+ | +-----------+ + | + | +-----------+ + +-->|boards | + + +----+------+ + | | +---------------+ + | +---------+|icicle-kit-es | + | +---+-----------+ + | | + | | +---------------+ + | +->|platform_config| + | | +---------------+ + | | + | | +---------------+ + | |---------|drivers_config | + | | +---------------+ + | | + | | +---------------+ + | |---------|linker | + | | +---------------+ + | | + | | +---------------+ + | |---------|mpfs_hal_config| + | | +---------------+ + | | + | | + | | +---------------+ + | +>|soc_config | + | | +---+-----------+ + | | | + | | | +---------------+------------------------+ + | | +->|multiple folders with fpga config for sw| + | | +----------------------------------------+ + | | + | | + | | + | | +---------------+ + | +>|soc_fpga_design| + | +--+------------+ + | | + | | +---------------+ + | +-->|libero_tcl | + | | +---------------+ + | | + | +-----------+ | +---------------+ + +--+|middleware + +-->|xml | + | +-----------+ +---------------+ + | + + + | +-----------+ + +--+|platform | + +----+------+ + | +---------------+ + +---------+|drivers | + | +---------------+ + | + | +---------------+ + +---------+|hal | + | +---------------+ + | + | +---------------+ + +---------+|mpfs_hal | + | +---------------+ + | + | +-------------------------+ + +---------+|platform_config_reference| + | +-------------------------+ + | + | +---------------------+ + +---------+|soc_config_generator | + +---------------------+ +~~~~ + +Please see the user guide for further details on +use. diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mcall.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mcall.h deleted file mode 100644 index faf2db5..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mcall.h +++ /dev/null @@ -1,35 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * -*/ - -/*********************************************************************************** - * @file mcall.h - * @author Microchip-FPGA Embedded Systems Solutions - * @brief mcall definitions - - */ -#ifndef RISCV_SBI_H -#define RISCV_SBI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define SBI_SET_TIMER 0 -#define SBI_CLEAR_IPI 3 -#define SBI_SEND_IPI 4 -#define SBI_REMOTE_FENCE_I 5 -#define SBI_REMOTE_SFENCE_VMA 6 -#define SBI_REMOTE_SFENCE_VMA_ASID 7 - -#ifdef __cplusplus -} -#endif - -#endif //RISCV_SBI_H - diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mpfs_hal_version.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mpfs_hal_version.h new file mode 100644 index 0000000..7fb26dd --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mpfs_hal_version.h @@ -0,0 +1,50 @@ +#ifndef MPFS_HAL_VERSION_H +#define MPFS_HAL_VERSION_H + +/******************************************************************************* + * Copyright 2019-2020 Microchip Corporation. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * + * + */ + +/******************************************************************************* + * @file mpfs_halversion.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief PolareFire SoC Hardware Abstraction layer - MPFS HAL version. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MPFS_HAL_VERSION_MAJOR 1 +#define MPFS_HAL_VERSION_MINOR 8 +#define MPFS_HAL_VERSION_PATCH 0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_coreplex.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_coreplex.h deleted file mode 100644 index 8d35fc6..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_coreplex.h +++ /dev/null @@ -1,100 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ - -/*************************************************************************** - * @file mss_coreplex.h - * @author Microchip-FPGA Embedded Systems Solutions - * @brief Coreplex definitions - * - */ -#ifndef MSS_COREPLEX_H -#define MSS_COREPLEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * U5 COREPLEX DEFINITIONS - */ -#define U5CP_CLINT_BASE (0x02000000) -#define U5CP_CACHE_CTRL_PORT_BASE (0x02010000) -#define CACHE_CTRL_NUM_BANKS_OFFSET (0x000) -#define CACHE_CTRL_NUM_WAYS_OFFSET (0x001) -#define CACHE_CTRL_NUM_SETS_OFFSET (0x002) -#define CACHE_CTRL_BLKSIZE_OFFSET (0x003) -#define CACHE_CTRL_WAYENB_OFFSET (0x008) -#define CACHE_CTRL_ERR_INJ_OFFSET (0x040) -#define CACHE_CTRL_ADDR_META_DATA_ERR_OFFSET (0x100) -#define CACHE_CTRL_NUM_META_DATA_ERRS_OFFSET (0x108) -#define CACHE_CTRL_ADDR_DATA_ERR_OFFSET (0x140) -#define CACHE_CTRL_NUM_DATA_ERRS_OFFSET (0x148) -#define CACHE_CTRL_ADDR_UNCORRECTABLE_DATA_OFFSET (0x160) -#define CACHE_CTRL_NUM_UNCORRECTABLE_DATA_ERRS_OFFSET (0x168) -#define CACHE_CTRL_FLUSH64_OFFSET (0x200) -#define CACHE_CTRL_FLUSH32_OFFSET (0x240) -#define CACHE_CTRL_MASTER0_WAY_OFFSET (0x800) - -#define CACHE_CTRL_NUM_BANKS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_BANKS_OFFSET) -#define CACHE_CTRL_NUM_WAYS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_WAYS_OFFSET) -#define CACHE_CTRL_NUM_SETS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_SETS_OFFSET) -#define CACHE_CTRL_BLKSIZE_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_BLKSIZE_OFFSET) -#define CACHE_CTRL_WAYENB_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_WAYENB_OFFSET) -#define CACHE_CTRL_ERR_INJ_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ERR_INJ_OFFSET) -#define CACHE_CTRL_ADDR_META_DATA_ERR_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ADDR_META_DATA_ERR_OFFSET) -#define CACHE_CTRL_NUM_META_DATA_ERRS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_META_DATA_ERRS_OFFSET) -#define CACHE_CTRL_ADDR_DATA_ERR_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ADDR_DATA_ERR_OFFSET) -#define CACHE_CTRL_NUM_DATA_ERRS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_DATA_ERRS_OFFSET) -#define CACHE_CTRL_ADDR_UNCORRECTABLE_DATA_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ADDR_UNCORRECTABLE_DATA_OFFSET) -#define CACHE_CTRL_NUM_UNCORRECTABLE_DATA_ERRS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_UNCORRECTABLE_DATA_ERRS_OFFSET) -#define CACHE_CTRL_FLUSH64_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_FLUSH64_OFFSET) -#define CACHE_CTRL_FLUSH32_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_FLUSH32_OFFSET) -#define CACHE_CTRL_MASTER0_WAY_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_MASTER0_WAY_OFFSET) - -#define U5CP_MSIP_BASE (U5CP_CLINT_BASE) -#define U5CP_MSIP_H0 (U5CP_MSIP_BASE + 0x00) -#define U5CP_MSIP_H1 (U5CP_MSIP_BASE + 0x04) -#define U5CP_MSIP_H2 (U5CP_MSIP_BASE + 0x08) -#define U5CP_MSIP_H3 (U5CP_MSIP_BASE + 0x0C) -#define U5CP_MSIP_H4 (U5CP_MSIP_BASE + 0x10) - -#define U5CP_MTIMECMP_BASE (U5CP_CLINT_BASE + 0x4000) -#define U5CP_MTIMECMP_H0 (U5CP_MTIMECMP_BASE + 0x00) -#define U5CP_MTIMECMP_H1 (U5CP_MTIMECMP_BASE + 0x04) -#define U5CP_MTIMECMP_H2 (U5CP_MTIMECMP_BASE + 0x08) -#define U5CP_MTIMECMP_H3 (U5CP_MTIMECMP_BASE + 0x0C) -#define U5CP_MTIMECMP_H4 (U5CP_MTIMECMP_BASE + 0x10) - -#define U5CP_MTIME_BASE (U5CP_CLINT_BASE + 0xBFF8) -#define U5CP_MTIME_H0 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H1 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H2 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H3 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H4 (U5CP_MTIME_BASE + 0x00) - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_COREPLEX_H */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_hal.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_hal.h index 87bd7ae..90cfbea 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_hal.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_hal.h @@ -27,13 +27,13 @@ typedef long ssize_t; #endif #endif -#include "mss_assert.h" -#include "mpfs_hal/nwc/mss_ddr_defs.h" -#include "mpfs_hal/nwc/mss_ddr_SGMII_regs.h" -#include "mpfs_hal/nwc/mss_io_config.h" -#include "mpfs_hal/nwc/mss_pll.h" -#include "mpfs_hal/nwc/mss_scb_nwc_regs.h" -#include "mpfs_hal/nwc/mss_scb_nwc_regs.h" +#include "common/mss_assert.h" +#include "common/nwc/mss_ddr_defs.h" +#include "common/nwc/mss_ddr_SGMII_regs.h" +#include "common/nwc/mss_io_config.h" +#include "common/nwc/mss_pll.h" +#include "common/nwc/mss_scb_nwc_regs.h" +#include "common/nwc/mss_scb_nwc_regs.h" /* * mss_sw_config.h may be edited as required and should be located outside the * mpfs_hal folder @@ -44,31 +44,28 @@ typedef long ssize_t; * mss_sw_config.h. This allows defines in hw_platform.h be overload from * mss_sw_config.h if necessary. * */ -#include "atomic.h" -#include "bits.h" -#include "encoding.h" +#include "common/atomic.h" +#include "common/bits.h" +#include "common/encoding.h" #include "soc_config/hw_platform.h" -#include "mpfs_hal/nwc/mss_ddr.h" -#include "mss_clint.h" -#include "mss_coreplex.h" -#include "mss_h2f.h" -#include "mss_hart_ints.h" -#include "mss_ints.h" -#include "mss_mpu.h" -#include "mss_peripheral_base_add.h" -#include "mss_plic.h" -#include "mss_prci.h" -#include "mss_seg.h" -#include "mss_sysreg.h" -#include "mss_util.h" -#include "mtrap.h" -#include "mss_l2_cache.h" -#include "mss_axiswitch.h" -#include "nwc/mss_cfm.h" -#include "nwc/mss_ddr.h" -#include "nwc/mss_sgmii.h" -#include "system_startup.h" -#include "nwc/mss_ddr_debug.h" +#include "common/nwc/mss_ddr.h" +#include "common/mss_clint.h" +#include "common/mss_h2f.h" +#include "common/mss_hart_ints.h" +#include "common/mss_mpu.h" +#include "common/mss_pmp.h" +#include "common/mss_plic.h" +#include "common/mss_seg.h" +#include "common/mss_sysreg.h" +#include "common/mss_util.h" +#include "common/mss_mtrap.h" +#include "common/mss_l2_cache.h" +#include "common/mss_axiswitch.h" +#include "common/nwc/mss_cfm.h" +#include "common/nwc/mss_ddr.h" +#include "common/nwc/mss_sgmii.h" +#include "startup_gcc/system_startup.h" +#include "common/nwc/mss_ddr_debug.h" #ifdef SIMULATION_TEST_FEEDBACK #include "nwc/simulation.h" #endif @@ -77,9 +74,6 @@ typedef long ssize_t; extern "C" { #endif -uint32_t SysTick_Config(void); -void disable_systick(void); - #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_ints.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_ints.h deleted file mode 100644 index 92a4394..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_ints.h +++ /dev/null @@ -1,180 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ - -/******************************************************************************* - * - * @file mss_ints.h - * @author Microchip-FPGA Embedded Systems Solutions - * @brief MPFS interrupt prototypes - * - * Interrupt function prototypes - * - */ - -#ifndef MSS_INTS_H -#define MSS_INTS_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void handle_m_ext_interrupt(void); -void Software_h0_IRQHandler(void); -void Software_h1_IRQHandler(void); -void Software_h2_IRQHandler(void); -void Software_h3_IRQHandler(void); -void Software_h4_IRQHandler(void); -void SysTick_Handler_h0_IRQHandler(void); -void SysTick_Handler_h1_IRQHandler(void); -void SysTick_Handler_h2_IRQHandler(void); -void SysTick_Handler_h3_IRQHandler(void); -void SysTick_Handler_h4_IRQHandler(void); - -/* - * - * Local interrupt stubs - * - */ -void maintenance_e51_local_IRQHandler_0(void); -void usoc_smb_interrupt_e51_local_IRQHandler_1(void); -void usoc_vc_interrupt_e51_local_IRQHandler_2(void); -void g5c_message_e51_local_IRQHandler_3(void); -void g5c_devrst_e51_local_IRQHandler_4(void); -void wdog4_tout_e51_local_IRQHandler_5(void); -void wdog3_tout_e51_local_IRQHandler_6(void); -void wdog2_tout_e51_local_IRQHandler_7(void); -void wdog1_tout_e51_local_IRQHandler_8(void); -void wdog0_tout_e51_local_IRQHandler_9(void); -void wdog0_mvrp_e51_local_IRQHandler_10(void); -void mmuart0_e51_local_IRQHandler_11(void); -void envm_e51_local_IRQHandler_12(void); -void ecc_correct_e51_local_IRQHandler_13(void); -void ecc_error_e51_local_IRQHandler_14(void); -void scb_interrupt_e51_local_IRQHandler_15(void); -void fabric_f2h_32_e51_local_IRQHandler_16(void); -void fabric_f2h_33_e51_local_IRQHandler_17(void); -void fabric_f2h_34_e51_local_IRQHandler_18(void); -void fabric_f2h_35_e51_local_IRQHandler_19(void); -void fabric_f2h_36_e51_local_IRQHandler_20(void); -void fabric_f2h_37_e51_local_IRQHandler_21(void); -void fabric_f2h_38_e51_local_IRQHandler_22(void); -void fabric_f2h_39_e51_local_IRQHandler_23(void); -void fabric_f2h_40_e51_local_IRQHandler_24(void); -void fabric_f2h_41_e51_local_IRQHandler_25(void); -void fabric_f2h_42_e51_local_IRQHandler_26(void); -void fabric_f2h_43_e51_local_IRQHandler_27(void); -void fabric_f2h_44_e51_local_IRQHandler_28(void); -void fabric_f2h_45_e51_local_IRQHandler_29(void); -void fabric_f2h_46_e51_local_IRQHandler_30(void); -void fabric_f2h_47_e51_local_IRQHandler_31(void); -void fabric_f2h_48_e51_local_IRQHandler_32(void); -void fabric_f2h_49_e51_local_IRQHandler_33(void); -void fabric_f2h_50_e51_local_IRQHandler_34(void); -void fabric_f2h_51_e51_local_IRQHandler_35(void); -void fabric_f2h_52_e51_local_IRQHandler_36(void); -void fabric_f2h_53_e51_local_IRQHandler_37(void); -void fabric_f2h_54_e51_local_IRQHandler_38(void); -void fabric_f2h_55_e51_local_IRQHandler_39(void); -void fabric_f2h_56_e51_local_IRQHandler_40(void); -void fabric_f2h_57_e51_local_IRQHandler_41(void); -void fabric_f2h_58_e51_local_IRQHandler_42(void); -void fabric_f2h_59_e51_local_IRQHandler_43(void); -void fabric_f2h_60_e51_local_IRQHandler_44(void); -void fabric_f2h_61_e51_local_IRQHandler_45(void); -void fabric_f2h_62_e51_local_IRQHandler_46(void); -void fabric_f2h_63_e51_local_IRQHandler_47(void); - -/* - * U54 - */ -void spare_u54_local_IRQHandler_0(void); -void spare_u54_local_IRQHandler_1(void); -void spare_u54_local_IRQHandler_2(void); - -void mac_mmsl_u54_1_local_IRQHandler_3(void); -void mac_emac_u54_1_local_IRQHandler_4(void); -void mac_queue3_u54_1_local_IRQHandler_5(void); -void mac_queue2_u54_1_local_IRQHandler_6(void); -void mac_queue1_u54_1_local_IRQHandler_7(void); -void mac_int_u54_1_local_IRQHandler_8(void); - -void mac_mmsl_u54_2_local_IRQHandler_3(void); -void mac_emac_u54_2_local_IRQHandler_4(void); -void mac_queue3_u54_2_local_IRQHandler_5(void); -void mac_queue2_u54_2_local_IRQHandler_6(void); -void mac_queue1_u54_2_local_IRQHandler_7(void); -void mac_int_u54_2_local_IRQHandler_8(void); - -void mac_mmsl_u54_3_local_IRQHandler_3(void); -void mac_emac_u54_3_local_IRQHandler_4(void); -void mac_queue3_u54_3_local_IRQHandler_5(void); -void mac_queue2_u54_3_local_IRQHandler_6(void); -void mac_queue1_u54_3_local_IRQHandler_7(void); -void mac_int_u54_3_local_IRQHandler_8(void); - -void mac_mmsl_u54_4_local_IRQHandler_3(void); -void mac_emac_u54_4_local_IRQHandler_4(void); -void mac_queue3_u54_4_local_IRQHandler_5(void); -void mac_queue2_u54_4_local_IRQHandler_6(void); -void mac_queue1_u54_4_local_IRQHandler_7(void); -void mac_int_u54_4_local_IRQHandler_8(void); - -void wdog_tout_u54_h1_local_IRQHandler_9(void); -void wdog_tout_u54_h2_local_IRQHandler_9(void); -void wdog_tout_u54_h3_local_IRQHandler_9(void); -void wdog_tout_u54_h4_local_IRQHandler_9(void); -void mvrp_u54_local_IRQHandler_10(void); -void mmuart_u54_h1_local_IRQHandler_11(void); -void mmuart_u54_h2_local_IRQHandler_11(void); -void mmuart_u54_h3_local_IRQHandler_11(void); -void mmuart_u54_h4_local_IRQHandler_11(void); -void spare_u54_local_IRQHandler_12(void); -void spare_u54_local_IRQHandler_13(void); -void spare_u54_local_IRQHandler_14(void); -void spare_u54_local_IRQHandler_15(void); -void fabric_f2h_0_u54_local_IRQHandler_16(void); -void fabric_f2h_1_u54_local_IRQHandler_17(void); -void fabric_f2h_2_u54_local_IRQHandler_18(void); -void fabric_f2h_3_u54_local_IRQHandler_19(void); -void fabric_f2h_4_u54_local_IRQHandler_20(void); -void fabric_f2h_5_u54_local_IRQHandler_21(void); -void fabric_f2h_6_u54_local_IRQHandler_22(void); -void fabric_f2h_7_u54_local_IRQHandler_23(void); -void fabric_f2h_8_u54_local_IRQHandler_24(void); -void fabric_f2h_9_u54_local_IRQHandler_25(void); -void fabric_f2h_10_u54_local_IRQHandler_26(void); -void fabric_f2h_11_u54_local_IRQHandler_27(void); -void fabric_f2h_12_u54_local_IRQHandler_28(void); -void fabric_f2h_13_u54_local_IRQHandler_29(void); -void fabric_f2h_14_u54_local_IRQHandler_30(void); -void fabric_f2h_15_u54_local_IRQHandler_31(void); -void fabric_f2h_16_u54_local_IRQHandler_32(void); -void fabric_f2h_17_u54_local_IRQHandler_33(void); -void fabric_f2h_18_u54_local_IRQHandler_34(void); -void fabric_f2h_19_u54_local_IRQHandler_35(void); -void fabric_f2h_20_u54_local_IRQHandler_36(void); -void fabric_f2h_21_u54_local_IRQHandler_37(void); -void fabric_f2h_22_u54_local_IRQHandler_38(void); -void fabric_f2h_23_u54_local_IRQHandler_39(void); -void fabric_f2h_24_u54_local_IRQHandler_40(void); -void fabric_f2h_25_u54_local_IRQHandler_41(void); -void fabric_f2h_26_u54_local_IRQHandler_42(void); -void fabric_f2h_27_u54_local_IRQHandler_43(void); -void fabric_f2h_28_u54_local_IRQHandler_44(void); -void fabric_f2h_29_u54_local_IRQHandler_45(void); -void fabric_f2h_30_u54_local_IRQHandler_46(void); -void fabric_f2h_31_u54_local_IRQHandler_47(void); - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_INTS_H */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_peripheral_base_add.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_peripheral_base_add.h deleted file mode 100644 index 402da44..0000000 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_peripheral_base_add.h +++ /dev/null @@ -1,108 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ - -/******************************************************************************* - * - * @file mss_peripheral_base_add.h - * @author Microchip-FPGA Embedded Systems Solutions - * MSSIO bank numbers - * - */ - -#ifndef MSS_ADDRESS_MAP_H -#define MSS_ADDRESS_MAP_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL -#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL -#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL -#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL -#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL - -#define ERROR_DEVICE 0x18000000UL /* hifive unleashed only */ - -/* APB slots */ -/* - * By default, all the APB peripherals are connected to AXI-Slave 5 using the AXI to AHB and AHB to APB - * bridges. This means that the multiple CPUS and Fabric interfaces arbitrate - * for access to the APB slaves resulting in a variable access latency depended on system activity. This may - * cause system issues in particular in AMP mode with two separate operating systems running on different CPU’s - * A second AHB/APB bus system is connected to the AXI slave 6 port using system addresses 0x28000000-0x2FFFFFFF. - * Each of the APB peripherals can be configured at device start up to be connected the main APB bus - * (0x20000000-0x203FFFFF) or to the AMP APB bus (0x28000000-0x283FFFFF). This allows two independent access systems - * from the CPUS to the peripherals. Devices marked as DUAL SLOT in the defines below may be mapped to the second APB - * bus structure. - * - */ -#define MSS_BASE_ADD_MMUART0 0x20000000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG0 0x20001000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_SYSREG_PRIV 0x20002000UL -#define MSS_BASE_ADD_SYSREG_SCB 0x20003000UL -#define MSS_BASE_ADD_AXISW_CFG 0x20004000UL -#define MSS_BASE_ADD_MPUCFG 0x20005000UL -#define MSS_BASE_ADD_FMETER 0x20006000UL -#define MSS_BASE_ADD_FI_CFG 0x20007000UL -#define MSS_BASE_ADD_MMC_CFG 0x20008000UL -#define MSS_BASE_ADD_DRC_CFG 0x20080000UL -#define MSS_BASE_ADD_MMUART1 0x20100000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG1 0x20101000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MMUART2 0x20102000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG2 0x20103000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MMUART3 0x20104000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG3 0x20105000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MMUART4 0x20106000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG4 0x20107000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_SPI0 0x20108000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_SPI1 0x20109000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_I2C0 0x2010A000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_I2C1 0x2010B000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_AN0 0x2010C000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_AN1 0x2010D000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MAC0_CFG 0x20110000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MAC1_CFG 0x20112000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_GPIO0 0x20120000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_GPIO1 0x20121000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_GPIO2 0x20122000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MSRTC 0x20124000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MSTIMER 0x20125000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_H2FINT 0x20126000UL /* DUAL SLOT */ - -#define MSS_BASE_ADD_NVM_CFG 0x20200000UL -#define MSS_BASE_ADD_USB_CFG 0x20201000UL -#define MSS_BASE_ADD_NVM_DATA 0x20220000UL -#define MSS_BASE_ADD_QSPI_XIP 0x21000000UL -#define MSS_BASE_ADD_ATHENA 0x22000000UL -#define MSS_BASE_ADD_TRACE_AXIC 0x23000000UL -#define MSS_BASE_ADD_TRACE_SMB 0x23010000UL -#define MSS_BASE_ADD_TRACE_VC 0x23020000UL - -#define MSS_BASE_ADD_IOSCB_DATA 0x30000000UL -#define MSS_BASE_ADD_IOSCB_CFG 0x37080000UL -#define MSS_BASE_ADD_FIC3_FAB 0x40000000UL - -#define MSS_BASE_ADD_FIC0 0x60000000UL -#define MSS_BASE_ADD_DRC_CACHE 0x80000000UL -#define MSS_BASE_ADD_DRC_NC 0xC0000000UL -#define MSS_BASE_ADD_DRC_NC_WCB 0xD0000000UL -#define MSS_BASE_ADD_FIC1 0xE0000000UL - -#define MSS_BASE_ADD_DRC_CACHE_AXI_L2 0x1000000000UL -#define MSS_BASE_ADD_DRC_NC_AXI_NC 0x1400000000UL -#define MSS_BASE_ADD_DRC_NC_WCB_AXI_NC 0x1800000000UL -#define MSS_BASE_ADD_FIC0_AXI_F0 0x2000000000UL -#define MSS_BASE_ADD_FIC1_AXI_F1 0x3000000000UL - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_ADDRESS_MAP_H */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/entry.S b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/mss_entry.S similarity index 60% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/entry.S rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/mss_entry.S index 9140f45..9e049de 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/entry.S +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/mss_entry.S @@ -13,9 +13,11 @@ * @brief entry functions. * */ -#include "bits.h" -#include "encoding.h" -#include "mtrap.h" + +#include "../common/bits.h" +#include "../common/encoding.h" +#include "../common/mss_mtrap.h" +#include "system_startup_defs.h" #include "mpfs_hal_config/mss_sw_config.h" .option norvc @@ -25,6 +27,13 @@ reset_vector: _start: + /* + * clear the Return Address Stack + */ + call .clear_ras + li a1, 0x3 + csrw 0x7c0, a1 + /* Setup trap handler */ la a4, trap_vector csrw mtvec, a4 # initalise machine trap vector address @@ -49,6 +58,14 @@ _start: csrw mscratch, zero csrw mcause, zero csrw mepc, zero + /* + * clear PMP enables + */ + csrw pmpcfg0, zero + csrw pmpcfg2, zero + /* + * clear regs + */ li x1, 0 li x2, 0 li x3, 0 @@ -183,6 +200,20 @@ _start: call .clear_dtim call .clear_l2lim .skip_mem_clear: + /* + * Clear bus error unit accrued register on start-up + * This is cleared by the first hart only + */ + la a4,0x01700020UL + sb x0, 0(a4) + la a4,0x01701020UL + sb x0, 0(a4) + la a4,0x01702020UL + sb x0, 0(a4) + la a4,0x01703020UL + sb x0, 0(a4) + la a4,0x01704020UL + sb x0, 0(a4) # now core MPFS_HAL_FIRST_HART jumps to main_first_hart .main_hart: j main_first_hart @@ -202,7 +233,17 @@ _start: # enabled- otherwise stays in wfi. # Other interrupts appera to bring out of wfi,even if # not enabled. - li a1, HLS_DATA_IN_WFI + + # + # Wait here until main hart is up and running + # + li a3, HLS_MAIN_HART_STARTED + la a1, (__stack_top_h0$ - HLS_DEBUG_AREA_SIZE) +.wait_main_hart: + LOAD a2, 0(a1) + bne a3, a2, .wait_main_hart + # Flag we are here to the main hart + li a1, HLS_OTHER_HART_IN_WFI STORE a1, 0(tp) /* flush the instruction cache */ fence.i @@ -223,7 +264,7 @@ _start: csrw mie, zero csrw mip, zero # set marker as to where we are - li a1, HLS_DATA_PASSED_WFI + li a1, HLS_OTHER_HART_PASSED_WFI STORE a1, 0(tp) j main_other_hart .LoopForeverOther: @@ -235,6 +276,7 @@ _start: /******************************************************************************/ /******************************interrupt handeling below here******************/ /******************************************************************************/ + trap_vector: # The mscratch register is an XLEN-bit read/write register dedicated for use by machine mode. # Typically, it is used to hold a pointer to a machine-mode hart-local context space and swapped @@ -337,10 +379,186 @@ restore_regs: fence.i ret + /*********************************************************************************** + * + * The following init_memory() symbol overrides the weak symbol in the HAL and does + * a safe copy of RW data and clears zero-init memory + * + */ + // zero_section helper function: + // a0 = exec_start_addr + // a1 = exec_end_addr + // + .globl zero_section + .type zero_section, @function +zero_section: + beq a0, a1, .zero_section_done + sd zero, (a0) + addi a0, a0, 8 + j zero_section +.zero_section_done: + ret + + // zero_section helper function: + // a0 = exec_start_addr + // a1 = exec_end_addr + // a2 = start count + // + .globl count_section + .type count_section, @function +count_section: + beq a0, a1, .count_section_done + sd a2, (a0) + addi a0, a0, 8 + addi a2, a2, 8 + j count_section +.count_section_done: + ret + + // copy_section helper function: + // a0 = load_addr + // a1 = exec_start_addr + // a2 = exec_end_addr + .globl copy_section + .type copy_section, @function +copy_section: + beq a1, a0, .copy_section_done // if load_addr == exec_start_addr, goto copy_section_done +.check_if_copy_section_done: + beq a1, a2, .copy_section_done // if offset != length, goto keep_copying +.keep_copying: + ld a3, 0(a0) // val = *load_addr + sd a3, 0(a1) // *exec_start_addr = val; + addi a0, a0, 8 // load_addr = load_addr + 8 + addi a1, a1, 8 // exec_start_addr = exec_start_addr + 8 + j .check_if_copy_section_done +.copy_section_done: + ret + + + +/*********************************************************************************** + * + * memfill() - fills memory, alternate to lib function when not available + */ + // config_copy helper function: + // a0 = dest + // a1 = value to fill + // a2 = length + .globl memfill + .type memfill, @function +memfill: + mv t1,a0 + mv t2,a1 + beqz a2,2f +1: + sb t2,0(t1) + addi a2,a2,-1 + addi t1,t1,1 + bnez a2,1b +2: + ret + +/*********************************************************************************** + * + * The following config_copy() symbol overrides the weak symbol in the HAL and does + * a safe copy of HW config data + */ + // config_copy helper function: + // a0 = dest + // a1 = src + // a2 = length + .globl config_copy + .type config_copy, @function +config_copy: + mv t1,a0 + beqz a2,2f +1: + lb t2,0(a1) + sb t2,0(t1) + addi a2,a2,-1 + addi t1,t1,1 + addi a1,a1,1 + bnez a2,1b +2: + ret + +/*********************************************************************************** + * + * config_32_copy () Copies a word at a time, used when copying to contigous registers + */ + // config_copy helper function: + // a0 = dest + // a1 = src + // a2 = length + .globl config_32_copy + .type config_32_copy, @function +config_32_copy: + mv t1,a0 + beqz a2,2f +1: + lw t2,0(a1) + sw t2,0(t1) + addi a2,a2,-4 + addi t1,t1,4 + addi a1,a1,4 + bnez a2,1b +2: + ret + + /*********************************************************************************** + * + * config_64_copy - copying using 64 bit loads, addresses must be on 64 bit boundary + */ + // config_copy helper function: + // a0 = dest + // a1 = src + // a2 = length + .globl config_64_copy + .type config_64_copy, @function +config_64_copy: + mv t1,a0 + beqz a2,2f +1: + ld t2,0(a1) + sd t2,0(t1) + addi a2,a2,-8 + addi t1,t1,8 + addi a1,a1,8 + bnez a2,1b +2: + ret + +/*********************************************************************************** + * + * The following copy_switch_code() symbol overrides the weak symbol in the HAL and does + * a safe copy of HW config data + */ + .globl copy_switch_code + .type copy_switch_code, @function +copy_switch_code: + la a5, __sc_start // a5 = __sc_start + la a4, __sc_load // a4 = __sc_load + beq a5,a4,.copy_switch_code_done // if a5 == a4, goto copy_switch_code_done + la a3, __sc_end // a3 = __sc_end + beq a5,a3,.copy_switch_code_done // if a5 == a3, goto copy_switch_code_done +.copy_switch_code_loop: + lw a2,0(a4) // a2 = *a4 + sw a2,0(a5) // *a5 = a2 + addi a5,a5,4 // a5+=4 + addi a4,a4,4 // a4+=4 + + bltu a5,a3,.copy_switch_code_loop // if a5 < a3, goto copy_switch_code_loop +.copy_switch_code_done: + ret /******************************************************************************* * */ +#define START__OF_LIM 0x08000000 +#define END__OF_LIM 0x08200000 +#define START__OF_DTM 0x01000000 +#define END__OF_DTM 0x01002000 + .clear_l2lim: // Clear the LIM @@ -371,3 +589,60 @@ restore_regs: blt a4, a5, 1b .done_clear: ret + +/* + * record_ecc_error_counts on reset + * These are non-zero in the coreplex. + * Can be checked later on to see if values have changed + * a0 = mECCDataFailCount save address + a1 = mECCDataCorrectionCount save address + a2 = mECCDirFixCount save address + */ +.record_ecc_error_counts: + # Store initial ECC errors + #define mECCDataFailCount 0x02010168U + la a5, mECCDataFailCount + mv a4, a0// eg. Use stat of DTIM in not used for anything else 0x01000100 + lw t2,0(a5) + sw t2,0(a4) + #define mECCDataCorrectionCount 0x02010148U + la a5, mECCDataCorrectionCount + mv a4, a1// eg. Use stat of DTIM in not used for anything else 0x01000110 + lw t2,0(a5) + sw t2,0(a4) + #define mECCDirFixCount 0x02010108u + la a5, mECCDirFixCount + mv a4, a2// eg. Use stat of DTIM in not used for anything else 0x01000120 + lw t2,0(a5) + sw t2,0(a4) + ret + +/* + * clear_ras , clear_ras_2_deep + * Two deep function calls. + * Used to clear the interal processor Return Address Stack + * This is belt and braces, may not be required + */ +.clear_ras: + mv a5, x1 + nop + call .clear_ras_2_deep + nop + nop + nop + nop + nop + nop + mv x1, a5 + ret + +.clear_ras_2_deep: + nop + nop + nop + nop + nop + nop + ret + + diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_mutex.S b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/mss_mutex.S similarity index 100% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_mutex.S rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/mss_mutex.S diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/newlib_stubs.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/newlib_stubs.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c index 267a8c9..e2ea215 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/newlib_stubs.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c @@ -18,7 +18,7 @@ #include #include #include -#include "mss_hal.h" +#include "../mss_hal.h" /*============================================================================== * Redirection of standard output to a SmartFusion2 MSS UART. @@ -47,7 +47,7 @@ * MICROCHIP_STDIO_BAUD_RATE #define. */ #ifdef MICROCHIP_STDIO_THRU_UART -#include "drivers/mss_uart/mss_uart.h" +#include "drivers/mss_mmuart/mss_uart.h" #ifndef MICROCHIP_STDIO_BAUD_RATE #define MICROCHIP_STDIO_BAUD_RATE MSS_UART_115200_BAUD diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/system_startup.c b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.c similarity index 88% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/system_startup.c rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.c index d496d16..343fded 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/system_startup.c +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.c @@ -29,9 +29,10 @@ */ #include #include -#include "mss_hal.h" +#include "../mss_hal.h" #ifdef MPFS_HAL_HW_CONFIG -#include "nwc/mss_nwc_init.h" +#include "../common/nwc/mss_nwc_init.h" +#include "system_startup_defs.h" #endif @@ -58,6 +59,8 @@ __attribute__((weak)) int main_first_hart(void) if(hartid == MPFS_HAL_FIRST_HART) { uint8_t hard_idx; + ptrdiff_t stack_top; + /* * We only use code within the conditional compile * #ifdef MPFS_HAL_HW_CONFIG @@ -91,13 +94,15 @@ __attribute__((weak)) int main_first_hart(void) * Copies text section if relocation required */ (void)copy_section(&__text_load, &__text_start, &__text_end); - #ifdef MPFS_HAL_HW_CONFIG /* * Start the other harts. They are put in wfi in entry.S * When debugging, harts are released from reset separately, * so we need to make sure hart is in wfi before we try and release. */ + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h0$); + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); + hls->in_wfi_indicator = HLS_MAIN_HART_STARTED; WFI_SM sm_check_thread = INIT_THREAD_PR; hard_idx = MPFS_HAL_FIRST_HART + 1U; while( hard_idx <= MPFS_HAL_LAST_HART) @@ -108,16 +113,29 @@ __attribute__((weak)) int main_first_hart(void) { default: case INIT_THREAD_PR: - hls = (HLS_DATA*)((uint8_t *)&__stack_bottom_h1$ - + (((uint8_t *)&__stack_top_h1$ - - (uint8_t *)&__stack_bottom_h1$) * hard_idx) - - (uint8_t *)(HLS_DEBUG_AREA_SIZE)); + + switch (hard_idx) + { + case 1: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h1$); + break; + case 2: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h2$); + break; + case 3: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h3$); + break; + case 4: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h4$); + break; + } + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); sm_check_thread = CHECK_WFI; wait_count = 0U; break; case CHECK_WFI: - if( hls->in_wfi_indicator == HLS_DATA_IN_WFI ) + if( hls->in_wfi_indicator == HLS_OTHER_HART_IN_WFI ) { /* Separate state- to add a little delay */ sm_check_thread = SEND_WFI; @@ -131,7 +149,7 @@ __attribute__((weak)) int main_first_hart(void) break; case CHECK_WAKE: - if( hls->in_wfi_indicator == HLS_DATA_PASSED_WFI ) + if( hls->in_wfi_indicator == HLS_OTHER_HART_PASSED_WFI ) { sm_check_thread = INIT_THREAD_PR; hard_idx++; @@ -142,7 +160,7 @@ __attribute__((weak)) int main_first_hart(void) wait_count++; if(wait_count > 0x10U) { - if( hls->in_wfi_indicator == HLS_DATA_IN_WFI ) + if( hls->in_wfi_indicator == HLS_OTHER_HART_IN_WFI ) { raise_soft_interrupt(hard_idx); wait_count = 0UL; @@ -152,6 +170,9 @@ __attribute__((weak)) int main_first_hart(void) break; } } + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h0$); + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); + hls->in_wfi_indicator = HLS_MAIN_HART_FIN_INIT; #endif /* MPFS_HAL_HW_CONFIG */ (void)main_other_hart(); @@ -359,66 +380,6 @@ __attribute__((weak)) void u54_4(void) park_hart(); } - /*============================================================================== - * Copy hardware configuration to registers. - * This function should be used in place of memcpy() to cover the use case - * where C library code has not yet been copied from its LMA to VMA. For - * example copying before the copy_section of the .text section has taken - * place. - */ - char * config_copy(void *dest, const void * src, size_t len) - { - char *csrc = (char *)src; - char *cdest = (char *)dest; - - for(uint32_t inc = 0; inc < len; inc++) - { - cdest[inc] = csrc[inc]; - } - - return(csrc); - } - - -/** - * copy_section - * @param p_load - * @param p_vma - * @param p_vma_end - */ -void copy_section -( - uint64_t * p_load, - uint64_t * p_vma, - uint64_t * p_vma_end) -{ - if ( p_vma != p_load) - { - while(p_vma < p_vma_end) - { - *p_vma = *p_load; - ++p_load; - ++p_vma; - } - } -} - -/** - * zero_section - * @param start - * @param end - */ -static void zero_section(uint64_t * start, uint64_t * end) -{ - uint64_t * p_zero = start; - - while(p_zero < end) - { - *p_zero = 0UL; - ++p_zero; - } -} - /*----------------------------------------------------------------------------- * _start() function called invoked * This function is called on power up and warm reset. @@ -431,6 +392,11 @@ static void zero_section(uint64_t * start, uint64_t * end) copy_section(&__sdata_load, &__sdata_start, &__sdata_end); copy_section(&__data_load, &__data_start, &__data_end); + + /* filling the lim as a test with identifiable content */ +#if 0 //todo: used during testing, remove + count_section(&__stack_top_h4$, &__l2lim_end, &__stack_top_h4$); +#endif copy_section(&__l2_scratchpad_load, &__l2_scratchpad_start, &__l2_scratchpad_end); zero_section(&__sbss_start, &__sbss_end); zero_section(&__bss_start, &__bss_end); @@ -456,6 +422,9 @@ __attribute__((weak)) uint8_t init_bus_error_unit(void) BEU->regs[hard_idx].ENABLE = (uint64_t)BEU_ENABLE; BEU->regs[hard_idx].PLIC_INT = (uint64_t)BEU_PLIC_INT; BEU->regs[hard_idx].LOCAL_INT = (uint64_t)BEU_LOCAL_INT; + BEU->regs[hard_idx].CAUSE = 0ULL; + BEU->regs[hard_idx].ACCRUED = 0ULL; + BEU->regs[hard_idx].VALUE = 0ULL; } #endif return (0U); diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/system_startup.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.h similarity index 67% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/system_startup.h rename to examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.h index 6c90e51..8691dc0 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/system_startup.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup.h @@ -37,8 +37,16 @@ typedef struct HLS_DATA_ /*------------------------------------------------------------------------------ * Symbols from the linker script used to locate the text, data and bss sections. */ +extern unsigned long __stack_top_h0$; +extern unsigned long __stack_bottom_h0$; extern unsigned long __stack_top_h1$; extern unsigned long __stack_bottom_h1$; +extern unsigned long __stack_top_h2$; +extern unsigned long __stack_bottom_h2$; +extern unsigned long __stack_top_h3$; +extern unsigned long __stack_bottom_h3$; +extern unsigned long __stack_top_h4$; +extern unsigned long __stack_bottom_h4$; extern unsigned long __data_load; extern unsigned long __data_start; @@ -58,6 +66,23 @@ extern unsigned long __text_load; extern unsigned long __text_start; extern unsigned long __text_end; +extern unsigned long __l2lim_end; + +extern unsigned long __e51itim_start; +extern unsigned long __e51itim_end; + +extern unsigned long __u54_1_itim_start; +extern unsigned long __u54_1_itim_end; + +extern unsigned long __u54_2_itim_start; +extern unsigned long __u54_2_itim_end; + +extern unsigned long __u54_3_itim_start; +extern unsigned long __u54_3_itim_end; + +extern unsigned long __u54_4_itim_start; +extern unsigned long __u54_4_itim_end; + /* * Function Declarations */ @@ -72,15 +97,31 @@ void init_memory( void); uint8_t init_mem_protection_unit(void); uint8_t init_pmp(uint8_t hart_id); uint8_t init_bus_error_unit( void); +char * memfill(void *dest, const void * src, size_t len); char * config_copy(void *dest, const void * src, size_t len); +char * config_32_copy(void *dest, const void * src, size_t len); +char * config_64_copy(void *dest, const void * src, size_t len); + void copy_section ( uint64_t * p_load, uint64_t * p_vma, uint64_t * p_vma_end ); +void zero_section +( + uint64_t *__sbss_start, + uint64_t * __sbss_end +); void load_virtual_rom(void); +void count_section +( + uint64_t * start_address, + uint64_t * end_address, + uint64_t * start_value +); + #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h new file mode 100644 index 0000000..9ad2051 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * +*/ + +/****************************************************************************** + * @file system_startup_defs.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Defines for the system_startup_defs.c + */ + +#ifndef SYSTEM_STARTUP_DEFS_H +#define SYSTEM_STARTUP_DESF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Markers used to indicate startup status of hart + */ +#define HLS_MAIN_HART_STARTED 0x12344321U +#define HLS_MAIN_HART_FIN_INIT 0x55555555U +#define HLS_OTHER_HART_IN_WFI 0x12345678U +#define HLS_OTHER_HART_PASSED_WFI 0x87654321U + +/*------------------------------------------------------------------------------ + * Define the size of the HLS used + * In our HAL, we are using Hart Local storage for debug data storage only + * as well as flags for wfi instruction management. + * The TLS will take memory from top of the stack if allocated + * + */ +#if !defined (HLS_DEBUG_AREA_SIZE) +#define HLS_DEBUG_AREA_SIZE 64 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STARTUP_H */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld index 7613092..870f719 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld @@ -131,11 +131,11 @@ HEAP_SIZE = 0k; /* needs to be calculated for your appli * These are the stack sizes that will be allocated to each hart before starting * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). */ -STACK_SIZE_E51_APPLICATION = 1k; -STACK_SIZE_U54_1_APPLICATION = 1k; -STACK_SIZE_U54_2_APPLICATION = 1k; -STACK_SIZE_U54_3_APPLICATION = 1k; -STACK_SIZE_U54_4_APPLICATION = 1k; +STACK_SIZE_E51_APPLICATION = 8k; +STACK_SIZE_U54_1_APPLICATION = 8k; +STACK_SIZE_U54_2_APPLICATION = 8k; +STACK_SIZE_U54_3_APPLICATION = 8k; +STACK_SIZE_U54_4_APPLICATION = 8k; /* reset address 0xC0000000 */ SECTION_START_ADDRESS = 0x80000000; @@ -166,6 +166,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -184,6 +185,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } > DDR_CACHED @@ -226,22 +231,11 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } > DDR_CACHED - - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > DDR_CACHED - + /* data section */ .data : ALIGN(0x10) { @@ -321,5 +315,13 @@ SECTIONS PROVIDE(__stack_top_h4$ = .); } > DDR_CACHED + + /* must be on 4k boundary- corresponds to page size */ + .free_lim : ALIGN(0x1000) + { + /* place __start_of_free_lim$ after last allocation of l2_lim */ + . = ALIGN(0x10); + PROVIDE(__start_of_free_lim$ = .); + } > DDR_CACHED } diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-dtim.ld b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-dtim.ld index 9429d04..b3ba45f 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-dtim.ld +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-dtim.ld @@ -95,7 +95,7 @@ See mpfs-lim.ld example linker script when runing from LIM. MEMORY { - eNVM (rx) : ORIGIN = 0x20230000, LENGTH = 56k + eNVM (rx) : ORIGIN = 0x20220000, LENGTH = 64k ram_LIM (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k ram (rwx) : ORIGIN = 0x01000000, LENGTH = 8k scratchpad(rwx): ORIGIN = 0x0A000000, LENGTH = 512k @@ -154,6 +154,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -172,6 +173,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } > ram @@ -214,22 +219,11 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } > ram - - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > ram - + /* data section */ .data : ALIGN(0x10) { diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld index ee898eb..6a84f8f 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-envm.ld @@ -100,7 +100,7 @@ MEMORY /* eNVM can be made into 128K section or split as required */ /* In this example, our reset vector is set to point to the */ /* start of SEC2 at 0x20220000. */ - eNVM_SEC_2_0_1_3 (rx) : ORIGIN = 0x20220000, LENGTH = 120k + eNVM_SEC_2_0_1_3 (rx) : ORIGIN = 0x20220000, LENGTH = 128k ram_LIM (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k ram_dtm (rwx) : ORIGIN = 0x01000000, LENGTH = 7k /* DTIM */ scratchpad(rwx): ORIGIN = 0x0A000000, LENGTH = 512k @@ -165,6 +165,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -183,6 +184,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } > eNVM_SEC_2_0_1_3 @@ -244,22 +249,11 @@ SECTIONS /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } > ram_LIM AT > eNVM_SEC_2_0_1_3 - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > ram_LIM - /* data section */ .data : ALIGN(0x10) { @@ -340,6 +334,9 @@ SECTIONS . += STACK_SIZE_U54_4_APPLICATION; PROVIDE(__app_stack_top_h4 = .); PROVIDE(__stack_top_h4$ = .); + /* place __start_of_free_lim$ after last allocation of l2_lim */ + . = ALIGN(0x10); + PROVIDE(__start_of_free_lim$ = .); } > ram_LIM } diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld index 0e96f29..39fbc58 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld @@ -117,7 +117,17 @@ HEAP_SIZE = 8k; /* needs to be calculated for your appli /* TLS hart 1 */ /* etc */ /* note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ -STACK_SIZE_PER_HART = 1k; + +/* + * Stack size for each hart's application. + * These are the stack sizes that will be allocated to each hart before starting + * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). + */ +STACK_SIZE_E51_APPLICATION = 8k; +STACK_SIZE_U54_1_APPLICATION = 8k; +STACK_SIZE_U54_2_APPLICATION = 8k; +STACK_SIZE_U54_3_APPLICATION = 8k; +STACK_SIZE_U54_4_APPLICATION = 8k; SECTIONS @@ -131,6 +141,7 @@ SECTIONS *mss_h2f.o (.text .text* .rodata .rodata* .srodata*) *mss_l2_cache.o (.text .text* .rodata .rodata* .srodata*) *mss_mpu.o (.text .text* .rodata .rodata* .srodata*) + *mss_pmp.o (.text .text* .rodata .rodata* .srodata*) *mss_mutex.o (.text .text* .rodata .rodata* .srodata*) *mss_stubs.o (.text .text* .rodata .rodata* .srodata*) *mss_util.o (.text .text* .rodata .rodata* .srodata*) @@ -164,6 +175,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -182,6 +194,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } >scratchpad AT> l2_lim @@ -204,22 +220,11 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } >scratchpad AT> l2_lim - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > scratchpad - /* data section */ .data : ALIGN(0x10) { @@ -270,23 +275,33 @@ SECTIONS .stack : ALIGN(0x1000) { PROVIDE(__stack_bottom_h0$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h0 = .); + . += STACK_SIZE_E51_APPLICATION; + PROVIDE(__app_stack_top_h0 = .); PROVIDE(__stack_top_h0$ = .); PROVIDE(__stack_bottom_h1$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h1$ = .); + . += STACK_SIZE_U54_1_APPLICATION; + PROVIDE(__app_stack_top_h1 = .); PROVIDE(__stack_top_h1$ = .); PROVIDE(__stack_bottom_h2$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h2 = .); + . += STACK_SIZE_U54_2_APPLICATION; + PROVIDE(__app_stack_top_h2 = .); PROVIDE(__stack_top_h2$ = .); PROVIDE(__stack_bottom_h3$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h3 = .); + . += STACK_SIZE_U54_3_APPLICATION; + PROVIDE(__app_stack_top_h3 = .); PROVIDE(__stack_top_h3$ = .); PROVIDE(__stack_bottom_h4$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h4 = .); + . += STACK_SIZE_U54_4_APPLICATION; + PROVIDE(__app_stack_top_h4 = .); PROVIDE(__stack_top_h4$ = .); } > l2_lim @@ -307,8 +322,10 @@ SECTIONS *(.ram_coderodata*) . = ALIGN (4); __sc_end = .; + /* place __start_of_free_lim$ after last allocation of l2_lim */ + PROVIDE(__start_of_free_lim$ = .); } >switch_code AT> l2_lim /* On the MPFS for startup code use, >switch_code AT>eNVM */ - + } diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld index 8693161..7f9918a 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/linker/mpfs-lim.ld @@ -95,18 +95,17 @@ See mpfs-lim.ld example linker script when runing from LIM. MEMORY { - /* eNVM can be made into 128K section or split as required */ - /* In this example, our reset vector is set to point to the */ - /* start of SEC0 at 0x20222000. The initial 8K is reserved for data - /* storage in this example */ - eNVM_SEC2 (rx) : ORIGIN = 0x20220000, LENGTH = 8k - eNVM_SEC0_1_3 (rx) : ORIGIN = 0x20222000, LENGTH = 120k - /* LIM - we place code here in this example */ - ram (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k - ram_DTIM (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - scratchpad(rwx): ORIGIN = 0x0A000000, LENGTH = 512k - /* This 1k of DTIM is used to run code when switching the eNVM clock */ - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k + envm (rx) : ORIGIN = 0x20220000, LENGTH = 128k + dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k + switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k + e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k + u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k + u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k + u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k + u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k + l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k + l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k + ddr (rwx) : ORIGIN = 0x80000000, LENGTH = 1024m } HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ @@ -123,24 +122,44 @@ HEAP_SIZE = 8k; /* needs to be calculated for your appli /* TLS hart 1 */ /* etc */ /* note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ -/* STACK_SIZE_PER_HART = 1k; */ +/* STACK_SIZE_PER_HART = 8k; */ /* * Stack size for each hart's application. * These are the stack sizes that will be allocated to each hart before starting * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). */ -STACK_SIZE_E51_APPLICATION = 1k; -STACK_SIZE_U54_1_APPLICATION = 1k; -STACK_SIZE_U54_2_APPLICATION = 1k; -STACK_SIZE_U54_3_APPLICATION = 1k; -STACK_SIZE_U54_4_APPLICATION = 1k; +STACK_SIZE_E51_APPLICATION = 8k; +STACK_SIZE_U54_1_APPLICATION = 8k; +STACK_SIZE_U54_2_APPLICATION = 8k; +STACK_SIZE_U54_3_APPLICATION = 8k; +STACK_SIZE_U54_4_APPLICATION = 8k; SECTIONS { + PROVIDE(__envm_start = ORIGIN(envm)); + PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); + PROVIDE(__l2lim_start = ORIGIN(l2lim)); + PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); + PROVIDE(__ddr_start = ORIGIN(ddr)); + PROVIDE(__ddr_end = ORIGIN(ddr) + LENGTH(ddr)); + PROVIDE(__dtim_start = ORIGIN(dtim)); + PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); + PROVIDE(__e51itim_start = ORIGIN(e51_itim)); + PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); + PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); + PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); + PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); + PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); + PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); + PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); + PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); + PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); + PROVIDE(__l2lim_start = ORIGIN(l2lim)); + PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); -/* text: test code section */ - . = 0x08000000; + /* text: text code section */ + . = __l2lim_start; .text : ALIGN(0x10) { __text_load = LOADADDR(.text); @@ -161,6 +180,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -179,12 +199,18 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; - } > ram + . = ALIGN(0x10); + } > l2lim .l2_scratchpad : ALIGN(0x10) { + . = ALIGN (0x10); __l2_scratchpad_load = LOADADDR(.l2_scratchpad); __l2_scratchpad_start = .; __l2_scratchpad_vma_start = .; @@ -192,7 +218,7 @@ SECTIONS . = ALIGN(0x10); __l2_scratchpad_end = .; __l2_scratchpad_vma_end = .; - } >scratchpad AT> ram + } >l2zerodevice AT> l2lim /* * The .ram_code section will contain the code That is run from RAM. @@ -211,7 +237,7 @@ SECTIONS *(.ram_coderodata*) . = ALIGN (4); __sc_end = .; - } >switch_code AT> ram /* On the MPFS for startup code use, >switch_code AT>eNVM */ + } >switch_code AT> l2lim /* On the MPFS for startup code use, >switch_code AT>eNVM */ /* short/global data section */ .sdata : ALIGN(0x10) @@ -221,21 +247,10 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; - } > ram - - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > ram + } > l2lim /* data section */ .data : ALIGN(0x10) @@ -247,7 +262,7 @@ SECTIONS *(.data .data.* .gnu.linkonce.d.*) . = ALIGN(0x10); __data_end = .; - } > ram + } > l2lim /* sbss section */ .sbss : ALIGN(0x10) @@ -257,7 +272,7 @@ SECTIONS *(.scommon) . = ALIGN(0x10); __sbss_end = .; - } > ram + } > l2lim /* sbss section */ .bss : ALIGN(0x10) @@ -268,7 +283,7 @@ SECTIONS *(COMMON) . = ALIGN(0x10); __bss_end = .; - } > ram + } > l2lim /* End of uninitialized data segment */ _end = .; @@ -280,7 +295,7 @@ SECTIONS __heap_end = .; . = ALIGN(0x10); _heap_end = __heap_end; - } > ram + } > l2lim /* must be on 4k boundary- corresponds to page size */ .stack : ALIGN(0x1000) @@ -314,7 +329,11 @@ SECTIONS . += STACK_SIZE_U54_4_APPLICATION; PROVIDE(__app_stack_top_h4 = .); PROVIDE(__stack_top_h4$ = .); - - } > ram + /* place __start_of_free_lim$ after last allocation of l2_lim */ + . = ALIGN(0x10); + PROVIDE(__start_of_free_lim$ = .); + } > l2lim + + } diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h index cf7e2fb..4e794bc 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h +++ b/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h @@ -117,8 +117,8 @@ /* * If not using item, comment out line below */ -//#define SGMII_SUPPORT -//#define DDR_SUPPORT +#define SGMII_SUPPORT +#define DDR_SUPPORT #define MSSIO_SUPPORT //#define SIMULATION_TEST_FEEDBACK //#define E51_ENTER_SLEEP_STATE diff --git a/examples/mss-rtc/mpfs-rtc-time/.cproject b/examples/mss-rtc/mpfs-rtc-time/.cproject index 63cb625..7b5c42f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/.cproject +++ b/examples/mss-rtc/mpfs-rtc-time/.cproject @@ -99,13 +99,15 @@ @@ -121,13 +123,15 @@ @@ -319,13 +323,15 @@ @@ -345,13 +351,15 @@ diff --git a/examples/mss-rtc/mpfs-rtc-time/mpfs-rtc-time hw all-harts debug.launch b/examples/mss-rtc/mpfs-rtc-time/mpfs-rtc-time hw all-harts debug.launch index bbe1114..bff0329 100644 --- a/examples/mss-rtc/mpfs-rtc-time/mpfs-rtc-time hw all-harts debug.launch +++ b/examples/mss-rtc/mpfs-rtc-time/mpfs-rtc-time hw all-harts debug.launch @@ -10,7 +10,7 @@ - + @@ -33,7 +33,7 @@ - + diff --git a/examples/mss-rtc/mpfs-rtc-time/src/application/hart0/e51.c b/examples/mss-rtc/mpfs-rtc-time/src/application/hart0/e51.c index fb28270..f0baeed 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/application/hart0/e51.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/application/hart0/e51.c @@ -47,8 +47,7 @@ void e51(void) /* All clocks ON */ SYSREG->SUBBLK_CLOCK_CR = 0xffffffff; - SYSREG->SOFT_RESET_CR &= ~((1u << 0u) | (1u << 4u) | (1u << 5u) | - (1u << 19u) | (1u << 23u) | (1u << 28u) | (1u << 18u)) ; + SYSREG->SOFT_RESET_CR &= ~((1u << 5u) | (1u << 18u)) ; /* RTC and MMUART0 */ MSS_UART_init(&g_mss_uart0_lo, MSS_UART_115200_BAUD, @@ -62,7 +61,7 @@ void e51(void) MSS_UART_polled_tx_string(&g_mss_uart0_lo, g_greeting_msg); SYSREG->RTC_CLOCK_CR &= ~BIT_SET; - SYSREG->RTC_CLOCK_CR = LIBERO_SETTING_MSS_RTC_TOGGLE_CLK / 100000UL; + SYSREG->RTC_CLOCK_CR = LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK / LIBERO_SETTING_MSS_RTC_TOGGLE_CLK; SYSREG->RTC_CLOCK_CR |= BIT_SET; /* Initialize RTC. */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_ddr_pll.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_ddr_pll.h deleted file mode 100644 index 2f5c741..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_ddr_pll.h +++ /dev/null @@ -1,198 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_ddr_pll.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_ddr_pll.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_DDR_PLL_H_ -#define HW_CLK_DDR_PLL_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DDR_SOFT_RESET) -/*This is a compulsory register for all SCB slaves and must be at the same -offset in all slaves to facilitate global soft reset of all SCB registers with -a single broadcast write from the SCB master. */ -#define LIBERO_SETTING_DDR_SOFT_RESET 0x00000000UL - /* NV_MAP [0:1] RST */ - /* V_MAP [1:1] RST */ - /* PERIPH [8:1] RST */ - /* BLOCKID [16:16] ID */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_CTRL) -/*PLL control register */ -#define LIBERO_SETTING_DDR_PLL_CTRL 0x0100003FUL - /* REG_POWERDOWN_B [0:1] RW value= 0x1 */ - /* REG_RFDIV_EN [1:1] RW value= 0x1 */ - /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ - /* REG_DIVQ1_EN [3:1] RW value= 0x1 */ - /* REG_DIVQ2_EN [4:1] RW value= 0x1 */ - /* REG_DIVQ3_EN [5:1] RW value= 0x1 */ - /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ - /* RESETONLOCK [7:1] RW value= 0x0 */ - /* BYPCK_SEL [8:4] RW value= 0x0 */ - /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ - /* RESERVE10 [13:3] RSVD */ - /* REG_BYPASSPRE [16:4] RW value= 0x0 */ - /* REG_BYPASSPOST [20:4] RW value= 0x0 */ - /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ - /* LOCK [25:1] RO */ - /* LOCK_INT_EN [26:1] RW value= 0x0 */ - /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ - /* LOCK_INT [28:1] SW1C */ - /* UNLOCK_INT [29:1] SW1C */ - /* RESERVE11 [30:1] RSVD */ - /* LOCK_B [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_REF_FB) -/*PLL reference and feedback registers */ -#define LIBERO_SETTING_DDR_PLL_REF_FB 0x00000500UL - /* FSE_B [0:1] RW value= 0x0 */ - /* FBCK_SEL [1:2] RW value= 0x0 */ - /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ - /* RESERVE12 [4:4] RSVD */ - /* RFDIV [8:6] RW value= 0x5 */ - /* RESERVE13 [14:2] RSVD */ - /* RESERVE14 [16:12] RSVD */ - /* RESERVE15 [28:4] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_FRACN) -/*PLL fractional register */ -#define LIBERO_SETTING_DDR_PLL_FRACN 0x00000000UL - /* FRACN_EN [0:1] RW value= 0x0 */ - /* FRACN_DAC_EN [1:1] RW value= 0x0 */ - /* RESERVE16 [2:6] RSVD */ - /* RESERVE17 [8:24] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_DIV_0_1) -/*PLL 0/1 division registers */ -#define LIBERO_SETTING_DDR_PLL_DIV_0_1 0x02000100UL - /* VCO0PH_SEL [0:3] RO */ - /* DIV0_START [3:3] RW value= 0x0 */ - /* RESERVE18 [6:2] RSVD */ - /* POST0DIV [8:7] RW value= 0x1 */ - /* RESERVE19 [15:1] RSVD */ - /* VCO1PH_SEL [16:3] RO */ - /* DIV1_START [19:3] RW value= 0x0 */ - /* RESERVE20 [22:2] RSVD */ - /* POST1DIV [24:7] RW value= 0x2 */ - /* RESERVE21 [31:1] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_DIV_2_3) -/*PLL 2/3 division registers */ -#define LIBERO_SETTING_DDR_PLL_DIV_2_3 0x01000100UL - /* VCO2PH_SEL [0:3] RO */ - /* DIV2_START [3:3] RW value= 0x0 */ - /* RESERVE22 [6:2] RSVD */ - /* POST2DIV [8:7] RW value= 0x1 */ - /* RESERVE23 [15:1] RSVD */ - /* VCO3PH_SEL [16:3] RO */ - /* DIV3_START [19:3] RW value= 0x0 */ - /* RESERVE24 [22:2] RSVD */ - /* POST3DIV [24:7] RW value= 0x1 */ - /* CKPOST3_SEL [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_CTRL2) -/*PLL control register */ -#define LIBERO_SETTING_DDR_PLL_CTRL2 0x00001020UL - /* BWI [0:2] RW value= 0x0 */ - /* BWP [2:2] RW value= 0x0 */ - /* IREF_EN [4:1] RW value= 0x0 */ - /* IREF_TOGGLE [5:1] RW value= 0x1 */ - /* RESERVE25 [6:3] RSVD */ - /* LOCKCNT [9:4] RW value= 0x8 */ - /* RESERVE26 [13:4] RSVD */ - /* ATEST_EN [17:1] RW value= 0x0 */ - /* ATEST_SEL [18:3] RW value= 0x0 */ - /* RESERVE27 [21:11] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_CAL) -/*PLL calibration register */ -#define LIBERO_SETTING_DDR_PLL_CAL 0x00000D06UL - /* DSKEWCALCNT [0:3] RW value= 0x6 */ - /* DSKEWCAL_EN [3:1] RW value= 0x0 */ - /* DSKEWCALBYP [4:1] RW value= 0x0 */ - /* RESERVE28 [5:3] RSVD */ - /* DSKEWCALIN [8:7] RW value= 0xd */ - /* RESERVE29 [15:1] RSVD */ - /* DSKEWCALOUT [16:7] RO */ - /* RESERVE30 [23:9] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_PLL_PHADJ) -/*PLL phase registers */ -#define LIBERO_SETTING_DDR_PLL_PHADJ 0x00005003UL - /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ - /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ - /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ - /* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */ - /* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */ - /* REG_OUT3_PHSINIT [11:3] RW value= 0x2 */ - /* REG_LOADPHS_B [14:1] RW value= 0x1 */ - /* RESERVE31 [15:17] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_0) -/*SSCG registers 0 */ -#define LIBERO_SETTING_DDR_SSCG_REG_0 0x00000000UL - /* DIVVAL [0:6] RW value= 0x0 */ - /* FRACIN [6:24] RW value= 0x0 */ - /* RESERVE00 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_1) -/*SSCG registers 1 */ -#define LIBERO_SETTING_DDR_SSCG_REG_1 0x00000000UL - /* DOWNSPREAD [0:1] RW value= 0x0 */ - /* SSMD [1:5] RW value= 0x0 */ - /* FRACMOD [6:24] RO */ - /* RESERVE01 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_2) -/*SSCG registers 2 */ -#define LIBERO_SETTING_DDR_SSCG_REG_2 0x00000080UL - /* INTIN [0:12] RW value= 0x80 */ - /* INTMOD [12:12] RO */ - /* RESERVE02 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DDR_SSCG_REG_3) -/*SSCG registers 3 */ -#define LIBERO_SETTING_DDR_SSCG_REG_3 0x00000001UL - /* SSE_B [0:1] RW value= 0x1 */ - /* SEL_EXTWAVE [1:2] RW value= 0x0 */ - /* EXT_MAXADDR [3:8] RW value= 0x0 */ - /* TBLADDR [11:8] RO */ - /* RANDOM_FILTER [19:1] RW value= 0x0 */ - /* RANDOM_SEL [20:2] RW value= 0x0 */ - /* RESERVE03 [22:1] RSVD */ - /* RESERVE04 [23:9] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_DDR_PLL_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_mss_cfm.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_mss_cfm.h deleted file mode 100644 index 6fde0cf..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_mss_cfm.h +++ /dev/null @@ -1,115 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_mss_cfm.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_mss_cfm.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_MSS_CFM_H_ -#define HW_CLK_MSS_CFM_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_BCLKMUX) -/*Input mux selections */ -#define LIBERO_SETTING_MSS_BCLKMUX 0x00000208UL - /* BCLK0_SEL [0:5] RW value= 0x8 */ - /* BCLK1_SEL [5:5] RW value= 0x10 */ - /* BCLK2_SEL [10:5] RW value= 0x0 */ - /* BCLK3_SEL [15:5] RW value= 0x0 */ - /* BCLK4_SEL [20:5] RW value= 0x0 */ - /* BCLK5_SEL [25:5] RW value= 0x0 */ - /* RESERVED [30:2] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_CKMUX) -/*Input mux selections */ -#define LIBERO_SETTING_MSS_PLL_CKMUX 0x00000155UL - /* CLK_IN_MAC_TSU_SEL [0:2] RW value= 0x1 */ - /* PLL0_RFCLK0_SEL [2:2] RW value= 0x1 */ - /* PLL0_RFCLK1_SEL [4:2] RW value= 0x1 */ - /* PLL1_RFCLK0_SEL [6:2] RW value= 0x1 */ - /* PLL1_RFCLK1_SEL [8:2] RW value= 0x1 */ - /* PLL1_FDR_SEL [10:5] RW value= 0x0 */ - /* RESERVED [15:17] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_MSSCLKMUX) -/*MSS Clock mux selections */ -#define LIBERO_SETTING_MSS_MSSCLKMUX 0x00000003UL - /* MSSCLK_MUX_SEL [0:2] RW value= 0x3 */ - /* MSSCLK_MUX_MD [2:2] RW value= 0x0 */ - /* CLK_STANDBY_SEL [4:1] RW value= 0x0 */ - /* RESERVED [5:27] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_SPARE0) -/*spare logic */ -#define LIBERO_SETTING_MSS_SPARE0 0x00000000UL - /* SPARE0 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_FMETER_ADDR) -/*Frequency_meter_address_selections */ -#define LIBERO_SETTING_MSS_FMETER_ADDR 0x00000000UL - /* ADDR10 [0:2] RSVD */ - /* ADDR [2:4] RW value= 0x0 */ - /* RESERVE18 [6:26] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_FMETER_DATAW) -/*Frequency_meter_data_write */ -#define LIBERO_SETTING_MSS_FMETER_DATAW 0x00000000UL - /* DATA [0:24] RW value= 0x0 */ - /* STROBE [24:1] W1P */ - /* RESERVE19 [25:7] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_FMETER_DATAR) -/*Frequency_meter_data_read */ -#define LIBERO_SETTING_MSS_FMETER_DATAR 0x00000000UL - /* DATA [0:24] RO */ - /* RESERVE20 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_IMIRROR_TRIM) -/*Imirror TRIM Bits */ -#define LIBERO_SETTING_MSS_IMIRROR_TRIM 0x00000000UL - /* BG_CODE [0:3] RW value= 0x0 */ - /* CC_CODE [3:8] RW value= 0x0 */ - /* RESERVE21 [11:21] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_TEST_CTRL) -/*Test MUX Controls */ -#define LIBERO_SETTING_MSS_TEST_CTRL 0x00000000UL - /* OSC_ENABLE [0:4] RW value= 0x0 */ - /* ATEST_EN [4:1] RW value= 0x0 */ - /* ATEST_SEL [5:5] RW value= 0x0 */ - /* DTEST_EN [10:1] RW value= 0x0 */ - /* DTEST_SEL [11:5] RW value= 0x0 */ - /* RESERVE22 [16:16] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_MSS_CFM_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_mss_pll.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_mss_pll.h deleted file mode 100644 index fb6a379..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_mss_pll.h +++ /dev/null @@ -1,188 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_mss_pll.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_mss_pll.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_MSS_PLL_H_ -#define HW_CLK_MSS_PLL_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_PLL_CTRL) -/*PLL control register */ -#define LIBERO_SETTING_MSS_PLL_CTRL 0x01000007UL - /* REG_POWERDOWN_B [0:1] RW value= 0x1 */ - /* REG_RFDIV_EN [1:1] RW value= 0x1 */ - /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ - /* REG_DIVQ1_EN [3:1] RW value= 0x0 */ - /* REG_DIVQ2_EN [4:1] RW value= 0x0 */ - /* REG_DIVQ3_EN [5:1] RW value= 0x0 */ - /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ - /* RESETONLOCK [7:1] RW value= 0x0 */ - /* BYPCK_SEL [8:4] RW value= 0x0 */ - /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ - /* RESERVE10 [13:3] RSVD */ - /* REG_BYPASSPRE [16:4] RW value= 0x0 */ - /* REG_BYPASSPOST [20:4] RW value= 0x0 */ - /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ - /* LOCK [25:1] RO */ - /* LOCK_INT_EN [26:1] RW value= 0x0 */ - /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ - /* LOCK_INT [28:1] SW1C */ - /* UNLOCK_INT [29:1] SW1C */ - /* RESERVE11 [30:1] RSVD */ - /* LOCK_B [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_REF_FB) -/*PLL reference and feedback registers */ -#define LIBERO_SETTING_MSS_PLL_REF_FB 0x00000500UL - /* FSE_B [0:1] RW value= 0x0 */ - /* FBCK_SEL [1:2] RW value= 0x0 */ - /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ - /* RESERVE12 [4:4] RSVD */ - /* RFDIV [8:6] RW value= 0x5 */ - /* RESERVE13 [14:2] RSVD */ - /* RESERVE14 [16:12] RSVD */ - /* RESERVE15 [28:4] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_FRACN) -/*PLL fractional register */ -#define LIBERO_SETTING_MSS_PLL_FRACN 0x00000000UL - /* FRACN_EN [0:1] RW value= 0x0 */ - /* FRACN_DAC_EN [1:1] RW value= 0x0 */ - /* RESERVE16 [2:6] RSVD */ - /* RESERVE17 [8:24] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_DIV_0_1) -/*PLL 0/1 division registers */ -#define LIBERO_SETTING_MSS_PLL_DIV_0_1 0x01000100UL - /* VCO0PH_SEL [0:3] RO */ - /* DIV0_START [3:3] RW value= 0x0 */ - /* RESERVE18 [6:2] RSVD */ - /* POST0DIV [8:7] RW value= 0x1 */ - /* RESERVE19 [15:1] RSVD */ - /* VCO1PH_SEL [16:3] RO */ - /* DIV1_START [19:3] RW value= 0x0 */ - /* RESERVE20 [22:2] RSVD */ - /* POST1DIV [24:7] RW value= 0x1 */ - /* RESERVE21 [31:1] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_DIV_2_3) -/*PLL 2/3 division registers */ -#define LIBERO_SETTING_MSS_PLL_DIV_2_3 0x01000100UL - /* VCO2PH_SEL [0:3] RO */ - /* DIV2_START [3:3] RW value= 0x0 */ - /* RESERVE22 [6:2] RSVD */ - /* POST2DIV [8:7] RW value= 0x1 */ - /* RESERVE23 [15:1] RSVD */ - /* VCO3PH_SEL [16:3] RO */ - /* DIV3_START [19:3] RW value= 0x0 */ - /* RESERVE24 [22:2] RSVD */ - /* POST3DIV [24:7] RW value= 0x1 */ - /* CKPOST3_SEL [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_CTRL2) -/*PLL control register */ -#define LIBERO_SETTING_MSS_PLL_CTRL2 0x00001020UL - /* BWI [0:2] RW value= 0x0 */ - /* BWP [2:2] RW value= 0x0 */ - /* IREF_EN [4:1] RW value= 0x0 */ - /* IREF_TOGGLE [5:1] RW value= 0x1 */ - /* RESERVE25 [6:3] RSVD */ - /* LOCKCNT [9:4] RW value= 0x8 */ - /* RESERVE26 [13:4] RSVD */ - /* ATEST_EN [17:1] RW value= 0x0 */ - /* ATEST_SEL [18:3] RW value= 0x0 */ - /* RESERVE27 [21:11] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_CAL) -/*PLL calibration register */ -#define LIBERO_SETTING_MSS_PLL_CAL 0x00000D06UL - /* DSKEWCALCNT [0:3] RW value= 0x6 */ - /* DSKEWCAL_EN [3:1] RW value= 0x0 */ - /* DSKEWCALBYP [4:1] RW value= 0x0 */ - /* RESERVE28 [5:3] RSVD */ - /* DSKEWCALIN [8:7] RW value= 0xd */ - /* RESERVE29 [15:1] RSVD */ - /* DSKEWCALOUT [16:7] RO */ - /* RESERVE30 [23:9] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_PLL_PHADJ) -/*PLL phase registers */ -#define LIBERO_SETTING_MSS_PLL_PHADJ 0x00004003UL - /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ - /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ - /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ - /* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */ - /* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */ - /* REG_OUT3_PHSINIT [11:3] RW value= 0x8 */ - /* REG_LOADPHS_B [14:1] RW value= 0x0 */ - /* RESERVE31 [15:17] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_0) -/*SSCG registers 0 */ -#define LIBERO_SETTING_MSS_SSCG_REG_0 0x00000000UL - /* DIVVAL [0:6] RW value= 0x0 */ - /* FRACIN [6:24] RW value= 0x0 */ - /* RESERVE00 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_1) -/*SSCG registers 1 */ -#define LIBERO_SETTING_MSS_SSCG_REG_1 0x00000000UL - /* DOWNSPREAD [0:1] RW value= 0x0 */ - /* SSMD [1:5] RW value= 0x0 */ - /* FRACMOD [6:24] RO */ - /* RESERVE01 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_2) -/*SSCG registers 2 */ -#define LIBERO_SETTING_MSS_SSCG_REG_2 0x00000060UL - /* INTIN [0:12] RW value= 0x60 */ - /* INTMOD [12:12] RO */ - /* RESERVE02 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_MSS_SSCG_REG_3) -/*SSCG registers 3 */ -#define LIBERO_SETTING_MSS_SSCG_REG_3 0x00000001UL - /* SSE_B [0:1] RW value= 0x1 */ - /* SEL_EXTWAVE [1:2] RW value= 0x0 */ - /* EXT_MAXADDR [3:8] RW value= 0x0 */ - /* TBLADDR [11:8] RO */ - /* RANDOM_FILTER [19:1] RW value= 0x0 */ - /* RANDOM_SEL [20:2] RW value= 0x0 */ - /* RESERVE03 [22:1] RSVD */ - /* RESERVE04 [23:9] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_MSS_PLL_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_cfm.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_cfm.h deleted file mode 100644 index aab31e7..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_cfm.h +++ /dev/null @@ -1,85 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_sgmii_cfm.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_sgmii_cfm.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_SGMII_CFM_H_ -#define HW_CLK_SGMII_CFM_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SGMII_REFCLKMUX) -/*Input mux selections */ -#define LIBERO_SETTING_SGMII_REFCLKMUX 0x00000005UL - /* PLL0_RFCLK0_SEL [0:2] RW value= 0x1 */ - /* PLL0_RFCLK1_SEL [2:2] RW value= 0x1 */ - /* RESERVED [4:28] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SGMII_CLKMUX) -/*sgmii clk mux */ -#define LIBERO_SETTING_SGMII_SGMII_CLKMUX 0x00000005UL - /* SGMII_CLKMUX [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SPARE0) -/*spare logic */ -#define LIBERO_SETTING_SGMII_SPARE0 0x00000000UL - /* RESERVED [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_CLK_XCVR) -/*Clock_Receiver */ -#define LIBERO_SETTING_SGMII_CLK_XCVR 0x00002C30UL - /* EN_UDRIVE_P [0:1] RW value= 0x0 */ - /* EN_INS_HYST_P [1:1] RW value= 0x0 */ - /* EN_TERM_P [2:2] RW value= 0x0 */ - /* EN_RXMODE_P [4:2] RW value= 0x3 */ - /* EN_UDRIVE_N [6:1] RW value= 0x0 */ - /* EN_INS_HYST_N [7:1] RW value= 0x0 */ - /* EN_TERM_N [8:2] RW value= 0x0 */ - /* EN_RXMODE_N [10:2] RW value= 0x3 */ - /* CLKBUF_EN_PULLUP [12:1] RW value= 0x0 */ - /* EN_RDIFF [13:1] RW value= 0x1 */ - /* RESERVED [14:18] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_TEST_CTRL) -/*Test MUX Controls */ -#define LIBERO_SETTING_SGMII_TEST_CTRL 0x00000000UL - /* OSC_ENABLE [0:4] RW value= 0x0 */ - /* ATEST_EN [4:1] RW value= 0x0 */ - /* ATEST_SEL [5:5] RW value= 0x0 */ - /* DTEST_EN [10:1] RW value= 0x0 */ - /* DTEST_SEL [11:5] RW value= 0x0 */ - /* RESERVE22 [16:16] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_SGMII_CFM_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_pll.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_pll.h deleted file mode 100644 index d518916..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sgmii_pll.h +++ /dev/null @@ -1,198 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_sgmii_pll.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_sgmii_pll.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_SGMII_PLL_H_ -#define HW_CLK_SGMII_PLL_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SGMII_SOFT_RESET) -/*This is a compulsory register for all SCB slaves and must be at the same -offset in all slaves to facilitate global soft reset of all SCB registers with -a single broadcast write from the SCB master. */ -#define LIBERO_SETTING_SGMII_SOFT_RESET 0x00000000UL - /* NV_MAP [0:1] RST */ - /* V_MAP [1:1] RST */ - /* PERIPH [8:1] RST */ - /* BLOCKID [16:16] ID */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL) -/*PLL control register */ -#define LIBERO_SETTING_SGMII_PLL_CTRL 0x0100003EUL - /* REG_POWERDOWN_B [0:1] RW value= 0x0 */ - /* REG_RFDIV_EN [1:1] RW value= 0x1 */ - /* REG_DIVQ0_EN [2:1] RW value= 0x1 */ - /* REG_DIVQ1_EN [3:1] RW value= 0x1 */ - /* REG_DIVQ2_EN [4:1] RW value= 0x1 */ - /* REG_DIVQ3_EN [5:1] RW value= 0x1 */ - /* REG_RFCLK_SEL [6:1] RW value= 0x0 */ - /* RESETONLOCK [7:1] RW value= 0x0 */ - /* BYPCK_SEL [8:4] RW value= 0x0 */ - /* REG_BYPASS_GO_B [12:1] RW value= 0x0 */ - /* RESERVE10 [13:3] RSVD */ - /* REG_BYPASSPRE [16:4] RW value= 0x0 */ - /* REG_BYPASSPOST [20:4] RW value= 0x0 */ - /* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */ - /* LOCK [25:1] RO */ - /* LOCK_INT_EN [26:1] RW value= 0x0 */ - /* UNLOCK_INT_EN [27:1] RW value= 0x0 */ - /* LOCK_INT [28:1] SW1C */ - /* UNLOCK_INT [29:1] SW1C */ - /* RESERVE11 [30:1] RSVD */ - /* LOCK_B [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_REF_FB) -/*PLL reference and feedback registers */ -#define LIBERO_SETTING_SGMII_PLL_REF_FB 0x00000100UL - /* FSE_B [0:1] RW value= 0x0 */ - /* FBCK_SEL [1:2] RW value= 0x0 */ - /* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */ - /* RESERVE12 [4:4] RSVD */ - /* RFDIV [8:6] RW value= 0x1 */ - /* RESERVE13 [14:2] RSVD */ - /* RESERVE14 [16:12] RSVD */ - /* RESERVE15 [28:4] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_FRACN) -/*PLL fractional register */ -#define LIBERO_SETTING_SGMII_PLL_FRACN 0x00000000UL - /* FRACN_EN [0:1] RW value= 0x0 */ - /* FRACN_DAC_EN [1:1] RW value= 0x0 */ - /* RESERVE16 [2:6] RSVD */ - /* RESERVE17 [8:24] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_0_1) -/*PLL 0/1 division registers */ -#define LIBERO_SETTING_SGMII_PLL_DIV_0_1 0x01000100UL - /* VCO0PH_SEL [0:3] RO */ - /* DIV0_START [3:3] RW value= 0x0 */ - /* RESERVE18 [6:2] RSVD */ - /* POST0DIV [8:7] RW value= 0x1 */ - /* RESERVE19 [15:1] RSVD */ - /* VCO1PH_SEL [16:3] RO */ - /* DIV1_START [19:3] RW value= 0x0 */ - /* RESERVE20 [22:2] RSVD */ - /* POST1DIV [24:7] RW value= 0x1 */ - /* RESERVE21 [31:1] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_2_3) -/*PLL 2/3 division registers */ -#define LIBERO_SETTING_SGMII_PLL_DIV_2_3 0x01000100UL - /* VCO2PH_SEL [0:3] RO */ - /* DIV2_START [3:3] RW value= 0x0 */ - /* RESERVE22 [6:2] RSVD */ - /* POST2DIV [8:7] RW value= 0x1 */ - /* RESERVE23 [15:1] RSVD */ - /* VCO3PH_SEL [16:3] RO */ - /* DIV3_START [19:3] RW value= 0x0 */ - /* RESERVE24 [22:2] RSVD */ - /* POST3DIV [24:7] RW value= 0x1 */ - /* CKPOST3_SEL [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL2) -/*PLL control register */ -#define LIBERO_SETTING_SGMII_PLL_CTRL2 0x00001020UL - /* BWI [0:2] RW value= 0x0 */ - /* BWP [2:2] RW value= 0x0 */ - /* IREF_EN [4:1] RW value= 0x0 */ - /* IREF_TOGGLE [5:1] RW value= 0x1 */ - /* RESERVE25 [6:3] RSVD */ - /* LOCKCNT [9:4] RW value= 0x8 */ - /* RESERVE26 [13:4] RSVD */ - /* ATEST_EN [17:1] RW value= 0x0 */ - /* ATEST_SEL [18:3] RW value= 0x0 */ - /* RESERVE27 [21:11] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_CAL) -/*PLL calibration register */ -#define LIBERO_SETTING_SGMII_PLL_CAL 0x00000D06UL - /* DSKEWCALCNT [0:3] RW value= 0x6 */ - /* DSKEWCAL_EN [3:1] RW value= 0x0 */ - /* DSKEWCALBYP [4:1] RW value= 0x0 */ - /* RESERVE28 [5:3] RSVD */ - /* DSKEWCALIN [8:7] RW value= 0xd */ - /* RESERVE29 [15:1] RSVD */ - /* DSKEWCALOUT [16:7] RO */ - /* RESERVE30 [23:9] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_PLL_PHADJ) -/*PLL phase registers */ -#define LIBERO_SETTING_SGMII_PLL_PHADJ 0x00007443UL - /* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */ - /* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */ - /* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */ - /* REG_OUT1_PHSINIT [5:3] RW value= 0x2 */ - /* REG_OUT2_PHSINIT [8:3] RW value= 0x4 */ - /* REG_OUT3_PHSINIT [11:3] RW value= 0x6 */ - /* REG_LOADPHS_B [14:1] RW value= 0x1 */ - /* RESERVE31 [15:17] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_0) -/*SSCG registers 0 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_0 0x00000000UL - /* DIVVAL [0:6] RW value= 0x0 */ - /* FRACIN [6:24] RW value= 0x0 */ - /* RESERVE00 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_1) -/*SSCG registers 1 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_1 0x00000000UL - /* DOWNSPREAD [0:1] RW value= 0x0 */ - /* SSMD [1:5] RW value= 0x0 */ - /* FRACMOD [6:24] RO */ - /* RESERVE01 [30:2] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_2) -/*SSCG registers 2 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_2 0x00000019UL - /* INTIN [0:12] RW value= 0x19 */ - /* INTMOD [12:12] RO */ - /* RESERVE02 [24:8] RSVD */ -#endif -#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_3) -/*SSCG registers 3 */ -#define LIBERO_SETTING_SGMII_SSCG_REG_3 0x00000001UL - /* SSE_B [0:1] RW value= 0x1 */ - /* SEL_EXTWAVE [1:2] RW value= 0x0 */ - /* EXT_MAXADDR [3:8] RW value= 0x0 */ - /* TBLADDR [11:8] RO */ - /* RANDOM_FILTER [19:1] RW value= 0x0 */ - /* RANDOM_SEL [20:2] RW value= 0x0 */ - /* RESERVE03 [22:1] RSVD */ - /* RESERVE04 [23:9] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_SGMII_PLL_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sysreg.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sysreg.h deleted file mode 100644 index 0923b4b..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_clk_sysreg.h +++ /dev/null @@ -1,67 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_clk_sysreg.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_clk_sysreg.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CLK_SYSREG_H_ -#define HW_CLK_SYSREG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR) -/*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */ -#define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR 0x00000024UL - /* DIVIDER_CPU [0:2] RW value= 0x0 */ - /* DIVIDER_AXI [2:2] RW value= 0x1 */ - /* DIVIDER_APB_AHB [4:2] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_MSS_RTC_CLOCK_CR) -/*RTC clock divider */ -#define LIBERO_SETTING_MSS_RTC_CLOCK_CR 0x00000064UL - /* PERIOD [0:12] RW value= 0x64 */ -#endif -#if !defined (LIBERO_SETTING_MSS_ENVM_CR) -/*ENVM AHB Controller setup - - Clock period = (Value+1) * (1000/AHBFREQMHZ) -e.g. 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz */ -#define LIBERO_SETTING_MSS_ENVM_CR 0x40050006UL - /* CLOCK_PERIOD [0:6] RW value= 0x6 */ - /* CLOCK_CONTINUOUS [8:1] RW value= 0x0 */ - /* CLOCK_SUPPRESS [9:1] RW value= 0x0 */ - /* READAHEAD [16:1] RW value= 0x1 */ - /* SLOWREAD [17:1] RW value= 0x0 */ - /* INTERRUPT_ENABLE [18:1] RW value= 0x1 */ - /* TIMER [24:8] RW value= 0x40 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CLK_SYSREG_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_mss_clks.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_mss_clks.h deleted file mode 100644 index 72f1274..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/clocks/hw_mss_clks.h +++ /dev/null @@ -1,73 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mss_clks.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mss_clks.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MSS_CLKS_H_ -#define HW_MSS_CLKS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK) -/*Ref Clock rate in MHz */ -#define LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK 100000000 - /* MSS_EXT_SGMII_REF_CLK [0:32] RW value= 100000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK) -/*CPU Clock rate in MHz */ -#define LIBERO_SETTING_MSS_COREPLEX_CPU_CLK 600000000 - /* MSS_COREPLEX_CPU_CLK [0:32] RW value= 600000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_SYSTEM_CLK) -/*System Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_SYSTEM_CLK 600000000 - /* MSS_SYSTEM_CLK [0:32] RW value= 600000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_RTC_TOGGLE_CLK) -/*RTC toggle Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_RTC_TOGGLE_CLK 1000000 - /* MSS_RTC_TOGGLE_CLK [0:32] RW value= 1000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_AXI_CLK) -/*AXI Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_AXI_CLK 300000000 - /* MSS_AXI_CLK [0:32] RW value= 300000000 */ -#endif -#if !defined (LIBERO_SETTING_MSS_APB_AHB_CLK) -/*AXI Clock rate in MHz static power. */ -#define LIBERO_SETTING_MSS_APB_AHB_CLK 150000000 - /* MSS_APB_AHB_CLK [0:32] RW value= 150000000 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MSS_CLKS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_io_bank.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_io_bank.h deleted file mode 100644 index 6e59d98..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_io_bank.h +++ /dev/null @@ -1,142 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_io_bank.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_io_bank.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_IO_BANK_H_ -#define HW_DDR_IO_BANK_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DPC_BITS) -/*DPC Bits Register */ -#define LIBERO_SETTING_DPC_BITS 0x0004C422UL - /* DPC_VS [0:4] RW value= 0x2 */ - /* DPC_VRGEN_H [4:6] RW value= 0x2 */ - /* DPC_VRGEN_EN_H [10:1] RW value= 0x1 */ - /* DPC_MOVE_EN_H [11:1] RW value= 0x0 */ - /* DPC_VRGEN_V [12:6] RW value= 0xC */ - /* DPC_VRGEN_EN_V [18:1] RW value= 0x1 */ - /* DPC_MOVE_EN_V [19:1] RW value= 0x0 */ - /* RESERVE01 [20:12] RSVD */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_DQ) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_DQ 0x00000006UL - /* RPC_ODT_DQ [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_DQS) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006UL - /* RPC_ODT_DQS [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_ADDCMD) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000004UL - /* RPC_ODT_ADDCMD [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_CLK) -/*Need to be set by software in all modes but OFF mode. Decoding options should -follow ODT_STR table, depends on drive STR setting */ -#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002UL - /* RPC_ODT_CLK [0:32] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQ) -/*0x2000 73A8 (rpc10_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_DQ 0x00000005UL - /* RPC_ODT_STATIC_DQ [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQS) -/*0x2000 73AC (rpc11_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_DQS 0x00000005UL - /* RPC_ODT_STATIC_DQS [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD) -/*0x2000 739C (rpc7_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD 0x00000007UL - /* RPC_ODT_STATIC_ADDCMD [0:32] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKP) -/*0x2000 73A4 (rpc9_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_CLKP 0x00000007UL - /* RPC_ODT_STATIC_CLKP [0:32] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKN) -/*0x2000 73A0 (rpc8_ODT) */ -#define LIBERO_SETTING_RPC_ODT_STATIC_CLKN 0x00000007UL - /* RPC_ODT_STATIC_CLKN [0:32] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_ADDCMD) -/*0x2000 757C (rpc95) */ -#define LIBERO_SETTING_RPC_IBUFMD_ADDCMD 0x00000003UL - /* RPC_IBUFMD_ADDCMD [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_CLK) -/*0x2000 7580 (rpc96) */ -#define LIBERO_SETTING_RPC_IBUFMD_CLK 0x00000004UL - /* RPC_IBUFMD_CLK [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQ) -/*0x2000 7584 (rpc97) */ -#define LIBERO_SETTING_RPC_IBUFMD_DQ 0x00000003UL - /* RPC_IBUFMD_DQ [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQS) -/*0x2000 7588 (rpc98) */ -#define LIBERO_SETTING_RPC_IBUFMD_DQS 0x00000004UL - /* RPC_IBUFMD_DQS [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_RPC_SPARE0_DQ) -/*bits 15:14 connect to pc_ibufmx DQ/DQS/DM bits 13:12 connect to pc_ibufmx -CA/CK Check at ioa pc bit */ -#define LIBERO_SETTING_RPC_SPARE0_DQ 0x00008000UL - /* RPC_SPARE0_DQ [0:32] RW value= 0x8000 */ -#endif -#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10) -/*0x2000 7428 OVRT10 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000000UL - /* RPC_EN_ADDCMD1_OVRT10 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11) -/*0x2000 742C OVRT11 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000120UL - /* RPC_EN_ADDCMD2_OVRT11 [0:32] RW value= 0x120 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_IO_BANK_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_mode.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_mode.h deleted file mode 100644 index 8d191a2..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_mode.h +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_mode.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_mode.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_MODE_H_ -#define HW_DDR_MODE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DDRPHY_MODE) -/*DDRPHY MODE (binary)- 000 ddr3, 001 ddr33L, 010 ddr4, 011 LPDDR3, 100 LPDDR4, -111 OFF_MODE */ -#define LIBERO_SETTING_DDRPHY_MODE 0x00014B04UL - /* DDRMODE [0:3] RW value= 0x4 */ - /* ECC [3:1] RW value= 0x0 */ - /* CRC [4:1] RW value= 0x0 */ - /* BUS_WIDTH [5:3] RW value= 0x0 */ - /* DMI_DBI [8:1] RW value= 0x1 */ - /* DQ_DRIVE [9:2] RW value= 0x1 */ - /* DQS_DRIVE [11:2] RW value= 0x1 */ - /* ADD_CMD_DRIVE [13:2] RW value= 0x2 */ - /* CLOCK_OUT_DRIVE [15:2] RW value= 0x2 */ - /* DQ_TERMINATION [17:2] RW value= 0x0 */ - /* DQS_TERMINATION [19:2] RW value= 0x0 */ - /* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */ - /* PRESET_ODT_CLK [23:2] RW value= 0x0 */ - /* POWER_DOWN [25:1] RW value= 0x0 */ - /* RANK [26:1] RW value= 0x0 */ - /* RESERVED [27:5] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DATA_LANES_USED) -/*number of lanes used for data- does not include ECC, infer from mode register -*/ -#define LIBERO_SETTING_DATA_LANES_USED 0x00000002UL - /* DATA_LANES [0:3] RW value= 0x2 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_MODE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_off_mode.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_off_mode.h deleted file mode 100644 index 3ae39cb..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_off_mode.h +++ /dev/null @@ -1,75 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_off_mode.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_off_mode.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_OFF_MODE_H_ -#define HW_DDR_OFF_MODE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_DDRPHY_MODE_OFF) -/*DDRPHY MODE Register, ddr off */ -#define LIBERO_SETTING_DDRPHY_MODE_OFF 0x00000000UL - /* DDRMODE [0:3] RW value= 0x0 */ - /* ECC [3:1] RW value= 0x0 */ - /* CRC [4:1] RW value= 0x0 */ - /* BUS_WIDTH [5:3] RW value= 0x0 */ - /* DMI_DBI [8:1] RW value= 0x0 */ - /* DQ_DRIVE [9:2] RW value= 0x0 */ - /* DQS_DRIVE [11:2] RW value= 0x0 */ - /* ADD_CMD_DRIVE [13:2] RW value= 0x0 */ - /* CLOCK_OUT_DRIVE [15:2] RW value= 0x0 */ - /* DQ_TERMINATION [17:2] RW value= 0x0 */ - /* DQS_TERMINATION [19:2] RW value= 0x0 */ - /* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */ - /* PRESET_ODT_CLK [23:2] RW value= 0x0 */ - /* POWER_DOWN [25:1] RW value= 0x0 */ - /* RANK [26:1] RW value= 0x0 */ - /* RESERVED [27:5] RSVD */ -#endif -#if !defined (LIBERO_SETTING_DPC_BITS_OFF_MODE) -/*DPC Bits Register off mode */ -#define LIBERO_SETTING_DPC_BITS_OFF_MODE 0x00000000UL - /* DPC_VS [0:4] RW value= 0x0 */ - /* DPC_VRGEN_H [4:6] RW value= 0x0 */ - /* DPC_VRGEN_EN_H [10:1] RW value= 0x0 */ - /* DPC_MOVE_EN_H [11:1] RW value= 0x0 */ - /* DPC_VRGEN_V [12:6] RW value= 0x0 */ - /* DPC_VRGEN_EN_V [18:1] RW value= 0x0 */ - /* DPC_MOVE_EN_V [19:1] RW value= 0x0 */ - /* RESERVE01 [20:12] RSVD */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_OFF_MODE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_options.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_options.h deleted file mode 100644 index 197b954..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_options.h +++ /dev/null @@ -1,79 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_options.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_options.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_OPTIONS_H_ -#define HW_DDR_OPTIONS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING) -/*Tip config: Referenced receivers in the CA bus are turned on for CA training. -These burn static power.(0x01 => turn off ; 0x00 => no action ) */ -#define LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING 0x00000001UL - /* CA_BUS_RX_OFF_POST_TRAINING [0:1] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN) -/*Tip config: 1 => 1 rank, 3 => 2 ranks */ -#define LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN 0x00000001UL - /* USER_INPUT_PHY_RANKS_TO_TRAIN [0:2] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_TRAINING_SKIP_SETTING) -/*Tip config: Pick what trainings we want performed by the TIP, default is 0x1F -*/ -#define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000002UL - /* SKIP_BCLKSCLK_TIP_TRAINING [0:1] RW value= 0x0 */ - /* SKIP_ADDCMD_TIP_TRAINING [1:1] RW value= 0x1 */ - /* SKIP_WRLVL_TIP_TRAINING [2:1] RW value= 0x0 */ - /* SKIP_RDGATE_TIP_TRAINING [3:1] RW value= 0x0 */ - /* SKIP_DQ_DQS_OPT_TIP_TRAINING [4:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_TIP_CFG_PARAMS) -/*Tip config: default: 0x2,0x4,0x0,0x1F,0x1F */ -#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02AUL - /* ADDCMD_OFFSET [0:3] RW value= 0x2 */ - /* BCKLSCLK_OFFSET [3:3] RW value= 0x5 */ - /* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */ - /* READ_GATE_MIN_READS [13:8] RW value= 0x7F */ - /* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET) -/*in simulation we need to set this to 2, for hardware it will be dependent on -the trace lengths */ -#define LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET 0x00000002UL - /* TIP_CONFIG_PARAMS_BCLK_VCOPHS [0:32] RW value= 0x02 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_OPTIONS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_segs.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_segs.h deleted file mode 100644 index 1fd6308..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddr_segs.h +++ /dev/null @@ -1,155 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddr_segs.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddr_segs.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDR_SEGS_H_ -#define HW_DDR_SEGS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SEG0_0) -/*Cached access at 0x00_8000_0000 (-0x80+0x00) */ -#define LIBERO_SETTING_SEG0_0 0x00007F80UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7F80 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_1) -/*Cached access at 0x10_0000_000 */ -#define LIBERO_SETTING_SEG0_1 0x00007000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7000 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_2) -/*not used */ -#define LIBERO_SETTING_SEG0_2 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_3) -/*not used */ -#define LIBERO_SETTING_SEG0_3 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_4) -/*not used */ -#define LIBERO_SETTING_SEG0_4 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_5) -/*not used */ -#define LIBERO_SETTING_SEG0_5 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:6] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_6) -/*not used */ -#define LIBERO_SETTING_SEG0_6 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG0_7) -/*not used */ -#define LIBERO_SETTING_SEG0_7 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_0) -/*not used */ -#define LIBERO_SETTING_SEG1_0 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_1) -/*not used */ -#define LIBERO_SETTING_SEG1_1 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_2) -/*Non-Cached access at 0x00_c000_0000 */ -#define LIBERO_SETTING_SEG1_2 0x00007F40UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7F40 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_3) -/*Non-Cached access at 0x14_0000_0000 */ -#define LIBERO_SETTING_SEG1_3 0x00006C00UL - /* ADDRESS_OFFSET [0:15] RW value= 0x6C00 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_4) -/*Non-Cached WCB access at 0x00_d000_0000 */ -#define LIBERO_SETTING_SEG1_4 0x00007F30UL - /* ADDRESS_OFFSET [0:15] RW value= 0x7F30 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_5) -/*Non-Cached WCB 0x18_0000_0000 */ -#define LIBERO_SETTING_SEG1_5 0x00006800UL - /* ADDRESS_OFFSET [0:15] RW value= 0x6800 */ - /* RESERVED [15:6] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_6) -/*Trace - Trace not in use here so can be left as 0 */ -#define LIBERO_SETTING_SEG1_6 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SEG1_7) -/*not used */ -#define LIBERO_SETTING_SEG1_7 0x00000000UL - /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ - /* RESERVED [15:16] RW value= 0x0 */ - /* LOCKED [31:1] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDR_SEGS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddrc.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddrc.h deleted file mode 100644 index 38f0e2a..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/ddr/hw_ddrc.h +++ /dev/null @@ -1,1888 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_ddrc.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_ddrc.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_DDRC_H_ -#define HW_DDRC_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP 0x00000000UL - /* CFG_MANUAL_ADDRESS_MAP [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CHIPADDR_MAP) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_CHIPADDR_MAP 0x0000001DUL - /* CFG_CHIPADDR_MAP [0:32] RW value= 0x00001D */ -#endif -#if !defined (LIBERO_SETTING_CFG_CIDADDR_MAP) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_CIDADDR_MAP 0x00000000UL - /* CFG_CIDADDR_MAP [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW 0x00000004UL - /* CFG_MB_AUTOPCH_COL_BIT_POS_LOW [0:32] RW value= 0x00000004 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH 0x0000000AUL - /* CFG_MB_AUTOPCH_COL_BIT_POS_HIGH [0:32] RW value= 0x0000000A */ -#endif -#if !defined (LIBERO_SETTING_CFG_BANKADDR_MAP_0) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_BANKADDR_MAP_0 0x0000C2CAUL - /* CFG_BANKADDR_MAP_0 [0:32] RW value= 0x00C2CA */ -#endif -#if !defined (LIBERO_SETTING_CFG_BANKADDR_MAP_1) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_BANKADDR_MAP_1 0x00000000UL - /* CFG_BANKADDR_MAP_1 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_0) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_0 0x9140F38DUL - /* CFG_ROWADDR_MAP_0 [0:32] RW value= 0x9140F38D */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_1) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_1 0x75955134UL - /* CFG_ROWADDR_MAP_1 [0:32] RW value= 0x75955134 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_2) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_2 0x71B69961UL - /* CFG_ROWADDR_MAP_2 [0:32] RW value= 0x71B69961 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ROWADDR_MAP_3) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_ROWADDR_MAP_3 0x00000000UL - /* CFG_ROWADDR_MAP_3 [0:32] RW value= 0x000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_0) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_COLADDR_MAP_0 0x440C2040UL - /* CFG_COLADDR_MAP_0 [0:32] RW value= 0x440C2040 */ -#endif -#if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_1) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_COLADDR_MAP_1 0x02481C61UL - /* CFG_COLADDR_MAP_1 [0:32] RW value= 0x02481C61 */ -#endif -#if !defined (LIBERO_SETTING_CFG_COLADDR_MAP_2) -/*IP Blk = ADDR_MAP Access=RW */ -#define LIBERO_SETTING_CFG_COLADDR_MAP_2 0x00000000UL - /* CFG_COLADDR_MAP_2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VRCG_ENABLE) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_VRCG_ENABLE 0x00000140UL - /* CFG_VRCG_ENABLE [0:32] RW value= 0x00000140 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VRCG_DISABLE) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_VRCG_DISABLE 0x000000A0UL - /* CFG_VRCG_DISABLE [0:32] RW value= 0x000000A0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_LATENCY_SET) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_LATENCY_SET 0x00000000UL - /* CFG_WRITE_LATENCY_SET [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_THERMAL_OFFSET) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_THERMAL_OFFSET 0x00000000UL - /* CFG_THERMAL_OFFSET [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_SOC_ODT) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_SOC_ODT 0x00000006UL - /* CFG_SOC_ODT [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODTE_CK) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_ODTE_CK 0x00000000UL - /* CFG_ODTE_CK [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODTE_CS) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_ODTE_CS 0x00000000UL - /* CFG_ODTE_CS [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODTD_CA) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_ODTD_CA 0x00000000UL - /* CFG_ODTD_CA [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LPDDR4_FSP_OP) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_LPDDR4_FSP_OP 0x00000001UL - /* CFG_LPDDR4_FSP_OP [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX 0x00000001UL - /* CFG_GENERATE_REFRESH_ON_SRX [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DBI_CL) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_DBI_CL 0x00000016UL - /* CFG_DBI_CL [0:32] RW value= 0x00000016 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NON_DBI_CL) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_CFG_NON_DBI_CL 0x00000016UL - /* CFG_NON_DBI_CL [0:32] RW value= 0x00000016 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0) -/*IP Blk = MC_BASE3 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0 0x00000000UL - /* INIT_FORCE_WRITE_DATA_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_CRC) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_CRC 0x00000000UL - /* CFG_WRITE_CRC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MPR_READ_FORMAT) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_MPR_READ_FORMAT 0x00000000UL - /* CFG_MPR_READ_FORMAT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM 0x00000000UL - /* CFG_WR_CMD_LAT_CRC_DM [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE 0x00000000UL - /* CFG_FINE_GRAN_REF_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT 0x00000000UL - /* CFG_TEMP_SENSOR_READOUT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN 0x00000000UL - /* CFG_PER_DRAM_ADDR_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_GEARDOWN_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_GEARDOWN_MODE 0x00000000UL - /* CFG_GEARDOWN_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_PREAMBLE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WR_PREAMBLE 0x00000001UL - /* CFG_WR_PREAMBLE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_PREAMBLE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RD_PREAMBLE 0x00000000UL - /* CFG_RD_PREAMBLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE 0x00000000UL - /* CFG_RD_PREAMB_TRN_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_SR_ABORT) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_SR_ABORT 0x00000000UL - /* CFG_SR_ABORT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY 0x00000000UL - /* CFG_CS_TO_CMDADDR_LATENCY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_INT_VREF_MON) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_INT_VREF_MON 0x00000000UL - /* CFG_INT_VREF_MON [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE 0x00000000UL - /* CFG_TEMP_CTRL_REF_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE 0x00000000UL - /* CFG_TEMP_CTRL_REF_RANGE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE 0x00000000UL - /* CFG_MAX_PWR_DOWN_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_DBI) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_READ_DBI 0x00000000UL - /* CFG_READ_DBI [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_DBI) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_DBI 0x00000000UL - /* CFG_WRITE_DBI [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DATA_MASK) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_DATA_MASK 0x00000001UL - /* CFG_DATA_MASK [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR 0x00000000UL - /* CFG_CA_PARITY_PERSIST_ERR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTT_PARK) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RTT_PARK 0x00000000UL - /* CFG_RTT_PARK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_INBUF_4_PD) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_INBUF_4_PD 0x00000000UL - /* CFG_ODT_INBUF_4_PD [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS 0x00000000UL - /* CFG_CA_PARITY_ERR_STATUS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CRC_ERROR_CLEAR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CRC_ERROR_CLEAR 0x00000000UL - /* CFG_CRC_ERROR_CLEAR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_PARITY_LATENCY) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CA_PARITY_LATENCY 0x00000000UL - /* CFG_CA_PARITY_LATENCY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CCD_S) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CCD_S 0x00000005UL - /* CFG_CCD_S [0:32] RW value= 0x00000005 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CCD_L) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_CCD_L 0x00000006UL - /* CFG_CCD_L [0:32] RW value= 0x00000006 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE 0x00000000UL - /* CFG_VREFDQ_TRN_ENABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE 0x00000000UL - /* CFG_VREFDQ_TRN_RANGE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE 0x00000000UL - /* CFG_VREFDQ_TRN_VALUE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD_S) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RRD_S 0x00000004UL - /* CFG_RRD_S [0:32] RW value= 0x00000004 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD_L) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RRD_L 0x00000003UL - /* CFG_RRD_L [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_S) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_S 0x00000003UL - /* CFG_WTR_S [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_L) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_L 0x00000003UL - /* CFG_WTR_L [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_S_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_S_CRC_DM 0x00000003UL - /* CFG_WTR_S_CRC_DM [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR_L_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WTR_L_CRC_DM 0x00000003UL - /* CFG_WTR_L_CRC_DM [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_CRC_DM) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_WR_CRC_DM 0x00000006UL - /* CFG_WR_CRC_DM [0:32] RW value= 0x00000006 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC1 0x00000036UL - /* CFG_RFC1 [0:32] RW value= 0x00000036 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC2) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC2 0x00000036UL - /* CFG_RFC2 [0:32] RW value= 0x00000036 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC4) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC4 0x00000036UL - /* CFG_RFC4 [0:32] RW value= 0x00000036 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NIBBLE_DEVICES) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_NIBBLE_DEVICES 0x00000000UL - /* CFG_NIBBLE_DEVICES [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0 0x81881881UL - /* CFG_BIT_MAP_INDEX_CS0_0 [0:32] RW value= 0x81881881 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1 0x00008818UL - /* CFG_BIT_MAP_INDEX_CS0_1 [0:32] RW value= 0x00008818 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0 0xA92A92A9UL - /* CFG_BIT_MAP_INDEX_CS1_0 [0:32] RW value= 0xa92a92a9 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1 0x00002A92UL - /* CFG_BIT_MAP_INDEX_CS1_1 [0:32] RW value= 0x00002a92 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0 0xC28C28C2UL - /* CFG_BIT_MAP_INDEX_CS2_0 [0:32] RW value= 0xc28c28c2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1 0x00008C28UL - /* CFG_BIT_MAP_INDEX_CS2_1 [0:32] RW value= 0x00008c28 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0 0xEA2EA2EAUL - /* CFG_BIT_MAP_INDEX_CS3_0 [0:32] RW value= 0xea2ea2ea */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1 0x00002EA2UL - /* CFG_BIT_MAP_INDEX_CS3_1 [0:32] RW value= 0x00002ea2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0 0x03903903UL - /* CFG_BIT_MAP_INDEX_CS4_0 [0:32] RW value= 0x03903903 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1 0x00009039UL - /* CFG_BIT_MAP_INDEX_CS4_1 [0:32] RW value= 0x00009039 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0 0x2B32B32BUL - /* CFG_BIT_MAP_INDEX_CS5_0 [0:32] RW value= 0x2b32b32b */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1 0x000032B3UL - /* CFG_BIT_MAP_INDEX_CS5_1 [0:32] RW value= 0x000032b3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0 0x44944944UL - /* CFG_BIT_MAP_INDEX_CS6_0 [0:32] RW value= 0x44944944 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1 0x00009449UL - /* CFG_BIT_MAP_INDEX_CS6_1 [0:32] RW value= 0x00009449 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0 0x6C36C36CUL - /* CFG_BIT_MAP_INDEX_CS7_0 [0:32] RW value= 0x6c36c36c */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1 0x000036C3UL - /* CFG_BIT_MAP_INDEX_CS7_1 [0:32] RW value= 0x000036c3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0 0x85985985UL - /* CFG_BIT_MAP_INDEX_CS8_0 [0:32] RW value= 0x85985985 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1 0x00009859UL - /* CFG_BIT_MAP_INDEX_CS8_1 [0:32] RW value= 0x00009859 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0 0xAD3AD3ADUL - /* CFG_BIT_MAP_INDEX_CS9_0 [0:32] RW value= 0xad3ad3ad */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1 0x00003AD3UL - /* CFG_BIT_MAP_INDEX_CS9_1 [0:32] RW value= 0x00003ad3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0 0xC69C69C6UL - /* CFG_BIT_MAP_INDEX_CS10_0 [0:32] RW value= 0xc69c69c6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1 0x00009C69UL - /* CFG_BIT_MAP_INDEX_CS10_1 [0:32] RW value= 0x00009c69 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0 0xEE3EE3EEUL - /* CFG_BIT_MAP_INDEX_CS11_0 [0:32] RW value= 0xee3ee3ee */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1 0x00003EE3UL - /* CFG_BIT_MAP_INDEX_CS11_1 [0:32] RW value= 0x00003ee3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0 0x07A07A07UL - /* CFG_BIT_MAP_INDEX_CS12_0 [0:32] RW value= 0x07a07a07 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1 0x0000A07AUL - /* CFG_BIT_MAP_INDEX_CS12_1 [0:32] RW value= 0x0000a07a */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0 0x2F42F42FUL - /* CFG_BIT_MAP_INDEX_CS13_0 [0:32] RW value= 0x2f42f42f */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1 0x000042F4UL - /* CFG_BIT_MAP_INDEX_CS13_1 [0:32] RW value= 0x000042f4 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0 0x48A48A48UL - /* CFG_BIT_MAP_INDEX_CS14_0 [0:32] RW value= 0x48a48a48 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1 0x0000A48AUL - /* CFG_BIT_MAP_INDEX_CS14_1 [0:32] RW value= 0x0000a48a */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0 0x70470470UL - /* CFG_BIT_MAP_INDEX_CS15_0 [0:32] RW value= 0x70470470 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1 0x00004704UL - /* CFG_BIT_MAP_INDEX_CS15_1 [0:32] RW value= 0x00004704 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS 0x00000000UL - /* CFG_NUM_LOGICAL_RANKS_PER_3DS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC_DLR1) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC_DLR1 0x00000048UL - /* CFG_RFC_DLR1 [0:32] RW value= 0x00000048 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC_DLR2) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC_DLR2 0x0000002CUL - /* CFG_RFC_DLR2 [0:32] RW value= 0x0000002C */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC_DLR4) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RFC_DLR4 0x00000020UL - /* CFG_RFC_DLR4 [0:32] RW value= 0x00000020 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD_DLR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_RRD_DLR 0x00000004UL - /* CFG_RRD_DLR [0:32] RW value= 0x00000004 */ -#endif -#if !defined (LIBERO_SETTING_CFG_FAW_DLR) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_FAW_DLR 0x00000010UL - /* CFG_FAW_DLR [0:32] RW value= 0x00000010 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY) -/*IP Blk = MC_BASE1 Access=RW */ -#define LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY 0x00000000UL - /* CFG_ADVANCE_ACTIVATE_READY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CTRLR_SOFT_RESET_N) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CTRLR_SOFT_RESET_N 0x00000001UL - /* CTRLR_SOFT_RESET_N [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LOOKAHEAD_PCH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LOOKAHEAD_PCH 0x00000000UL - /* CFG_LOOKAHEAD_PCH [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LOOKAHEAD_ACT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LOOKAHEAD_ACT 0x00000000UL - /* CFG_LOOKAHEAD_ACT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_INIT_AUTOINIT_DISABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_AUTOINIT_DISABLE 0x00000000UL - /* INIT_AUTOINIT_DISABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_RESET) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_RESET 0x00000000UL - /* INIT_FORCE_RESET [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_GEARDOWN_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_GEARDOWN_EN 0x00000000UL - /* INIT_GEARDOWN_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DISABLE_CKE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_DISABLE_CKE 0x00000000UL - /* INIT_DISABLE_CKE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CS 0x00000000UL - /* INIT_CS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_PRECHARGE_ALL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_PRECHARGE_ALL 0x00000000UL - /* INIT_PRECHARGE_ALL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_REFRESH 0x00000000UL - /* INIT_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ZQ_CAL_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ZQ_CAL_REQ 0x00000000UL - /* INIT_ZQ_CAL_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BL 0x00000000UL - /* CFG_BL [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CTRLR_INIT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CTRLR_INIT 0x00000000UL - /* CTRLR_INIT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AUTO_REF_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AUTO_REF_EN 0x00000001UL - /* CFG_AUTO_REF_EN [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RAS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RAS 0x00000022UL - /* CFG_RAS [0:32] RW value= 0x22 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RCD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RCD 0x0000000FUL - /* CFG_RCD [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_RRD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RRD 0x00000008UL - /* CFG_RRD [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RP 0x00000011UL - /* CFG_RP [0:32] RW value= 0x11 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RC 0x00000033UL - /* CFG_RC [0:32] RW value= 0x33 */ -#endif -#if !defined (LIBERO_SETTING_CFG_FAW) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_FAW 0x00000020UL - /* CFG_FAW [0:32] RW value= 0x20 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RFC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RFC 0x00000130UL - /* CFG_RFC [0:32] RW value= 0x130 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RTP 0x00000008UL - /* CFG_RTP [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WR 0x00000010UL - /* CFG_WR [0:32] RW value= 0x10 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WTR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WTR 0x00000008UL - /* CFG_WTR [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PASR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PASR 0x00000000UL - /* CFG_PASR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XP 0x00000006UL - /* CFG_XP [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XSR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XSR 0x0000001FUL - /* CFG_XSR [0:32] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CFG_CL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CL 0x00000005UL - /* CFG_CL [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_WRITE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_WRITE 0x0000000FUL - /* CFG_READ_TO_WRITE [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_WRITE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_WRITE 0x0000000FUL - /* CFG_WRITE_TO_WRITE [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_READ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_READ 0x0000000FUL - /* CFG_READ_TO_READ [0:32] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_READ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_READ 0x0000001FUL - /* CFG_WRITE_TO_READ [0:32] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_WRITE_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_WRITE_ODT 0x00000001UL - /* CFG_READ_TO_WRITE_ODT [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT 0x00000000UL - /* CFG_WRITE_TO_WRITE_ODT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_READ_TO_READ_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_READ_TO_READ_ODT 0x00000001UL - /* CFG_READ_TO_READ_ODT [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WRITE_TO_READ_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WRITE_TO_READ_ODT 0x00000001UL - /* CFG_WRITE_TO_READ_ODT [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MIN_READ_IDLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MIN_READ_IDLE 0x00000001UL - /* CFG_MIN_READ_IDLE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRD 0x0000000CUL - /* CFG_MRD [0:32] RW value= 0xC */ -#endif -#if !defined (LIBERO_SETTING_CFG_BT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BT 0x00000000UL - /* CFG_BT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DS 0x00000006UL - /* CFG_DS [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_QOFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_QOFF 0x00000000UL - /* CFG_QOFF [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RTT 0x00000002UL - /* CFG_RTT [0:32] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DLL_DISABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DLL_DISABLE 0x00000000UL - /* CFG_DLL_DISABLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REF_PER) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_REF_PER 0x00000C34UL - /* CFG_REF_PER [0:32] RW value= 0xC34 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARTUP_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_STARTUP_DELAY 0x00027100UL - /* CFG_STARTUP_DELAY [0:32] RW value= 0x27100 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_COLBITS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEM_COLBITS 0x0000000AUL - /* CFG_MEM_COLBITS [0:32] RW value= 0xA */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_ROWBITS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEM_ROWBITS 0x00000010UL - /* CFG_MEM_ROWBITS [0:32] RW value= 0x10 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_BANKBITS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEM_BANKBITS 0x00000003UL - /* CFG_MEM_BANKBITS [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS0) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS0 0x00000000UL - /* CFG_ODT_RD_MAP_CS0 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS1 0x00000000UL - /* CFG_ODT_RD_MAP_CS1 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS2) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS2 0x00000000UL - /* CFG_ODT_RD_MAP_CS2 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS3) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS3 0x00000000UL - /* CFG_ODT_RD_MAP_CS3 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS4) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS4 0x00000000UL - /* CFG_ODT_RD_MAP_CS4 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS5) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS5 0x00000000UL - /* CFG_ODT_RD_MAP_CS5 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS6) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS6 0x00000000UL - /* CFG_ODT_RD_MAP_CS6 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_MAP_CS7) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_MAP_CS7 0x00000000UL - /* CFG_ODT_RD_MAP_CS7 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS0) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS0 0x00000000UL - /* CFG_ODT_WR_MAP_CS0 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS1 0x00000000UL - /* CFG_ODT_WR_MAP_CS1 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS2) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS2 0x00000000UL - /* CFG_ODT_WR_MAP_CS2 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS3) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS3 0x00000000UL - /* CFG_ODT_WR_MAP_CS3 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS4) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS4 0x00000000UL - /* CFG_ODT_WR_MAP_CS4 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS5) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS5 0x00000000UL - /* CFG_ODT_WR_MAP_CS5 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS6) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS6 0x00000000UL - /* CFG_ODT_WR_MAP_CS6 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_MAP_CS7) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_MAP_CS7 0x00000000UL - /* CFG_ODT_WR_MAP_CS7 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_TURN_ON) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_TURN_ON 0x00000000UL - /* CFG_ODT_RD_TURN_ON [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_TURN_ON) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_TURN_ON 0x00000000UL - /* CFG_ODT_WR_TURN_ON [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_RD_TURN_OFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_RD_TURN_OFF 0x00000000UL - /* CFG_ODT_RD_TURN_OFF [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_WR_TURN_OFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_WR_TURN_OFF 0x00000000UL - /* CFG_ODT_WR_TURN_OFF [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EMR3) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_EMR3 0x00000000UL - /* CFG_EMR3 [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TWO_T) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_TWO_T 0x00000000UL - /* CFG_TWO_T [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE 0x00000001UL - /* CFG_TWO_T_SEL_CYCLE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REGDIMM) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_REGDIMM 0x00000000UL - /* CFG_REGDIMM [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MOD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MOD 0x0000000CUL - /* CFG_MOD [0:32] RW value= 0xC */ -#endif -#if !defined (LIBERO_SETTING_CFG_XS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XS 0x00000005UL - /* CFG_XS [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XSDLL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XSDLL 0x00000200UL - /* CFG_XSDLL [0:32] RW value= 0x00000200 */ -#endif -#if !defined (LIBERO_SETTING_CFG_XPR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_XPR 0x00000005UL - /* CFG_XPR [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AL_MODE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AL_MODE 0x00000000UL - /* CFG_AL_MODE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CWL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CWL 0x00000005UL - /* CFG_CWL [0:32] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BL_MODE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BL_MODE 0x00000000UL - /* CFG_BL_MODE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TDQS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_TDQS 0x00000000UL - /* CFG_TDQS [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RTT_WR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RTT_WR 0x00000000UL - /* CFG_RTT_WR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LP_ASR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LP_ASR 0x00000000UL - /* CFG_LP_ASR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AUTO_SR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AUTO_SR 0x00000000UL - /* CFG_AUTO_SR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_SRT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_SRT 0x00000000UL - /* CFG_SRT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ADDR_MIRROR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ADDR_MIRROR 0x00000000UL - /* CFG_ADDR_MIRROR [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_TYPE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_TYPE 0x00000001UL - /* CFG_ZQ_CAL_TYPE [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_PER) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_PER 0x00027100UL - /* CFG_ZQ_CAL_PER [0:32] RW value= 0x27100 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN 0x00000000UL - /* CFG_AUTO_ZQ_CAL_EN [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEMORY_TYPE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MEMORY_TYPE 0x00000400UL - /* CFG_MEMORY_TYPE [0:32] RW value= 0x400 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ONLY_SRANK_CMDS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ONLY_SRANK_CMDS 0x00000000UL - /* CFG_ONLY_SRANK_CMDS [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NUM_RANKS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_NUM_RANKS 0x00000001UL - /* CFG_NUM_RANKS [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_QUAD_RANK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_QUAD_RANK 0x00000000UL - /* CFG_QUAD_RANK [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START 0x00000000UL - /* CFG_EARLY_RANK_TO_WR_START [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START 0x00000000UL - /* CFG_EARLY_RANK_TO_RD_START [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PASR_BANK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PASR_BANK 0x00000000UL - /* CFG_PASR_BANK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PASR_SEG) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PASR_SEG 0x00000000UL - /* CFG_PASR_SEG [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MRR_MODE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MRR_MODE 0x00000000UL - /* INIT_MRR_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_W_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_W_REQ 0x00000000UL - /* INIT_MR_W_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_ADDR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_ADDR 0x00000000UL - /* INIT_MR_ADDR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_WR_DATA) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_WR_DATA 0x00000000UL - /* INIT_MR_WR_DATA [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MR_WR_MASK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MR_WR_MASK 0x00000000UL - /* INIT_MR_WR_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_NOP) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_NOP 0x00000000UL - /* INIT_NOP [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_INIT_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_INIT_DURATION 0x00000640UL - /* CFG_INIT_DURATION [0:32] RW value= 0x640 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION 0x00000000UL - /* CFG_ZQINIT_CAL_DURATION [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION 0x00000000UL - /* CFG_ZQ_CAL_L_DURATION [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION 0x00000000UL - /* CFG_ZQ_CAL_S_DURATION [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION 0x00000028UL - /* CFG_ZQ_CAL_R_DURATION [0:32] RW value= 0x28 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRR) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRR 0x00000008UL - /* CFG_MRR [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRW) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRW 0x0000000AUL - /* CFG_MRW [0:32] RW value= 0xA */ -#endif -#if !defined (LIBERO_SETTING_CFG_ODT_POWERDOWN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ODT_POWERDOWN 0x00000000UL - /* CFG_ODT_POWERDOWN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WL 0x00000008UL - /* CFG_WL [0:32] RW value= 0x8 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RL 0x0000000EUL - /* CFG_RL [0:32] RW value= 0xE */ -#endif -#if !defined (LIBERO_SETTING_CFG_CAL_READ_PERIOD) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CAL_READ_PERIOD 0x00000000UL - /* CFG_CAL_READ_PERIOD [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_NUM_CAL_READS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_NUM_CAL_READS 0x00000001UL - /* CFG_NUM_CAL_READS [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_INIT_SELF_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_SELF_REFRESH 0x00000000UL - /* INIT_SELF_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_POWER_DOWN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_POWER_DOWN 0x00000000UL - /* INIT_POWER_DOWN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_WRITE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_WRITE 0x00000000UL - /* INIT_FORCE_WRITE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_FORCE_WRITE_CS) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_FORCE_WRITE_CS 0x00000000UL - /* INIT_FORCE_WRITE_CS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE 0x00000000UL - /* CFG_CTRLR_INIT_DISABLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_INIT_RDIMM_COMPLETE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_RDIMM_COMPLETE 0x00000000UL - /* INIT_RDIMM_COMPLETE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RDIMM_LAT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RDIMM_LAT 0x00000000UL - /* CFG_RDIMM_LAT [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT 0x00000001UL - /* CFG_RDIMM_BSIDE_INVERT [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_LRDIMM) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_LRDIMM 0x00000000UL - /* CFG_LRDIMM [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_MEMORY_RESET_MASK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_MEMORY_RESET_MASK 0x00000000UL - /* INIT_MEMORY_RESET_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE 0x00000000UL - /* CFG_RD_PREAMB_TOGGLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RD_POSTAMBLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RD_POSTAMBLE 0x00000000UL - /* CFG_RD_POSTAMBLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PU_CAL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PU_CAL 0x00000001UL - /* CFG_PU_CAL [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DQ_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DQ_ODT 0x00000002UL - /* CFG_DQ_ODT [0:32] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CA_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CA_ODT 0x00000004UL - /* CFG_CA_ODT [0:32] RW value= 0x4 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQLATCH_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQLATCH_DURATION 0x00000018UL - /* CFG_ZQLATCH_DURATION [0:32] RW value= 0x18 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_SELECT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_SELECT 0x00000000UL - /* INIT_CAL_SELECT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_R_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_R_REQ 0x00000000UL - /* INIT_CAL_L_R_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_B_SIZE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_B_SIZE 0x00000000UL - /* INIT_CAL_L_B_SIZE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_RWFIFO) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_RWFIFO 0x00000000UL - /* INIT_RWFIFO [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_RD_DQCAL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_RD_DQCAL 0x00000000UL - /* INIT_RD_DQCAL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_START_DQSOSC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_START_DQSOSC 0x00000000UL - /* INIT_START_DQSOSC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_STOP_DQSOSC) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_STOP_DQSOSC 0x00000000UL - /* INIT_STOP_DQSOSC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ZQ_CAL_START) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ZQ_CAL_START 0x00000000UL - /* INIT_ZQ_CAL_START [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_WR_POSTAMBLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_WR_POSTAMBLE 0x00000000UL - /* CFG_WR_POSTAMBLE [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_ADDR_0) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_ADDR_0 0x00000000UL - /* INIT_CAL_L_ADDR_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CAL_L_ADDR_1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_CAL_L_ADDR_1 0x00000000UL - /* INIT_CAL_L_ADDR_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLUPD_TRIG) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLUPD_TRIG 0x00000000UL - /* CFG_CTRLUPD_TRIG [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLUPD_START_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLUPD_START_DELAY 0x00000000UL - /* CFG_CTRLUPD_START_DELAY [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX 0x00000000UL - /* CFG_DFI_T_CTRLUPD_MAX [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_SEL) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_SEL 0x00000000UL - /* CFG_CTRLR_BUSY_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE 0x00000000UL - /* CFG_CTRLR_BUSY_VALUE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY 0x00000000UL - /* CFG_CTRLR_BUSY_TURN_OFF_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW 0x00000000UL - /* CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF 0x00000000UL - /* CFG_CTRLR_BUSY_RESTART_HOLDOFF [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY 0x00000000UL - /* CFG_PARITY_RDIMM_DELAY [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE 0x00000000UL - /* CFG_CTRLR_BUSY_ENABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ASYNC_ODT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ASYNC_ODT 0x00000000UL - /* CFG_ASYNC_ODT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ZQ_CAL_DURATION) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_ZQ_CAL_DURATION 0x00000320UL - /* CFG_ZQ_CAL_DURATION [0:32] RW value= 0x320 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MRRI) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MRRI 0x00000012UL - /* CFG_MRRI [0:32] RW value= 0x12 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ODT_FORCE_EN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ODT_FORCE_EN 0x00000000UL - /* INIT_ODT_FORCE_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_ODT_FORCE_RANK) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_ODT_FORCE_RANK 0x00000000UL - /* INIT_ODT_FORCE_RANK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY 0x00000000UL - /* CFG_PHYUPD_ACK_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1 0x00000000UL - /* CFG_MIRROR_X16_BG0_BG1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_PDA_MR_W_REQ) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_PDA_MR_W_REQ 0x00000000UL - /* INIT_PDA_MR_W_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT 0x00000000UL - /* INIT_PDA_NIBBLE_SELECT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH 0x00000000UL - /* CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CKSRE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CKSRE 0x00000008UL - /* CFG_CKSRE [0:32] RW value= 0x00000008 */ -#endif -#if !defined (LIBERO_SETTING_CFG_CKSRX) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_CKSRX 0x0000000BUL - /* CFG_CKSRX [0:32] RW value= 0x0000000b */ -#endif -#if !defined (LIBERO_SETTING_CFG_RCD_STAB) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_RCD_STAB 0x00000000UL - /* CFG_RCD_STAB [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY 0x00000000UL - /* CFG_DFI_T_CTRL_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE 0x00000000UL - /* CFG_DFI_T_DRAM_CLK_ENABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH 0x00000000UL - /* CFG_IDLE_TIME_TO_SELF_REFRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN 0x00000000UL - /* CFG_IDLE_TIME_TO_POWER_DOWN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF 0x00000000UL - /* CFG_BURST_RW_REFRESH_HOLDOFF [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_BG_INTERLEAVE) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_BG_INTERLEAVE 0x00000001UL - /* CFG_BG_INTERLEAVE [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING) -/*IP Blk = MC_BASE2 Access=RW */ -#define LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING 0x00000000UL - /* CFG_REFRESH_DURING_PHY_TRAINING [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0 0x00000000UL - /* CFG_STARVE_TIMEOUT_P0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1 0x00000000UL - /* CFG_STARVE_TIMEOUT_P1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2 0x00000000UL - /* CFG_STARVE_TIMEOUT_P2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3 0x00000000UL - /* CFG_STARVE_TIMEOUT_P3 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4 0x00000000UL - /* CFG_STARVE_TIMEOUT_P4 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5 0x00000000UL - /* CFG_STARVE_TIMEOUT_P5 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6 0x00000000UL - /* CFG_STARVE_TIMEOUT_P6 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7) -/*IP Blk = MPFE Access=RW */ -#define LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7 0x00000000UL - /* CFG_STARVE_TIMEOUT_P7 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REORDER_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_REORDER_EN 0x00000001UL - /* CFG_REORDER_EN [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REORDER_QUEUE_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_REORDER_QUEUE_EN 0x00000001UL - /* CFG_REORDER_QUEUE_EN [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN 0x00000000UL - /* CFG_INTRAPORT_REORDER_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MAINTAIN_COHERENCY) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_MAINTAIN_COHERENCY 0x00000001UL - /* CFG_MAINTAIN_COHERENCY [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_CFG_Q_AGE_LIMIT) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_Q_AGE_LIMIT 0x000000FFUL - /* CFG_Q_AGE_LIMIT [0:32] RW value= 0x000000FF */ -#endif -#if !defined (LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY 0x00000000UL - /* CFG_RO_CLOSED_PAGE_POLICY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_REORDER_RW_ONLY) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_REORDER_RW_ONLY 0x00000000UL - /* CFG_REORDER_RW_ONLY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RO_PRIORITY_EN) -/*IP Blk = REORDER Access=RW */ -#define LIBERO_SETTING_CFG_RO_PRIORITY_EN 0x00000000UL - /* CFG_RO_PRIORITY_EN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DM_EN) -/*IP Blk = RMW Access=RW */ -#define LIBERO_SETTING_CFG_DM_EN 0x00000001UL - /* CFG_DM_EN [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_RMW_EN) -/*IP Blk = RMW Access=RW */ -#define LIBERO_SETTING_CFG_RMW_EN 0x00000000UL - /* CFG_RMW_EN [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ECC_CORRECTION_EN) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_CFG_ECC_CORRECTION_EN 0x00000000UL - /* CFG_ECC_CORRECTION_EN [0:32] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ECC_BYPASS) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_CFG_ECC_BYPASS 0x00000000UL - /* CFG_ECC_BYPASS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN 0x00000000UL - /* INIT_WRITE_DATA_1B_ECC_ERROR_GEN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN 0x00000000UL - /* INIT_WRITE_DATA_2B_ECC_ERROR_GEN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH) -/*IP Blk = ECC Access=RW */ -#define LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH 0x00000000UL - /* CFG_ECC_1BIT_INT_THRESH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_READ_CAPTURE_ADDR) -/*IP Blk = READ_CAPT Access=RW */ -#define LIBERO_SETTING_INIT_READ_CAPTURE_ADDR 0x00000000UL - /* INIT_READ_CAPTURE_ADDR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ERROR_GROUP_SEL) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_ERROR_GROUP_SEL 0x00000000UL - /* CFG_ERROR_GROUP_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DATA_SEL) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_DATA_SEL 0x00000000UL - /* CFG_DATA_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MODE) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MODE 0x00000000UL - /* CFG_TRIG_MODE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_POST_TRIG_CYCS) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_POST_TRIG_CYCS 0x00000000UL - /* CFG_POST_TRIG_CYCS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MASK) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MASK 0x00000000UL - /* CFG_TRIG_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_EN_MASK) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_EN_MASK 0x00000000UL - /* CFG_EN_MASK [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_ADDR) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_ADDR 0x00000000UL - /* MTC_ACQ_ADDR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MT_ADDR_0) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MT_ADDR_0 0x00000000UL - /* CFG_TRIG_MT_ADDR_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_MT_ADDR_1) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_MT_ADDR_1 0x00000000UL - /* CFG_TRIG_MT_ADDR_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_0) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_0 0x00000000UL - /* CFG_TRIG_ERR_MASK_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_1) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_1 0x00000000UL - /* CFG_TRIG_ERR_MASK_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_2) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_2 0x00000000UL - /* CFG_TRIG_ERR_MASK_2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_3) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_3 0x00000000UL - /* CFG_TRIG_ERR_MASK_3 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_TRIG_ERR_MASK_4) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_TRIG_ERR_MASK_4 0x00000000UL - /* CFG_TRIG_ERR_MASK_4 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_0) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_WR_DATA_0 0x00000000UL - /* MTC_ACQ_WR_DATA_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_1) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_WR_DATA_1 0x00000000UL - /* MTC_ACQ_WR_DATA_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_MTC_ACQ_WR_DATA_2) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_MTC_ACQ_WR_DATA_2 0x00000000UL - /* MTC_ACQ_WR_DATA_2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_PRE_TRIG_CYCS) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_PRE_TRIG_CYCS 0x00000000UL - /* CFG_PRE_TRIG_CYCS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR) -/*IP Blk = MTA Access=RW */ -#define LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR 0x00000000UL - /* CFG_DATA_SEL_FIRST_ERROR [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DQ_WIDTH) -/*IP Blk = DYN_WIDTH_ADJ Access=RW */ -#define LIBERO_SETTING_CFG_DQ_WIDTH 0x00000001UL - /* CFG_DQ_WIDTH [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ACTIVE_DQ_SEL) -/*IP Blk = DYN_WIDTH_ADJ Access=RW */ -#define LIBERO_SETTING_CFG_ACTIVE_DQ_SEL 0x00000000UL - /* CFG_ACTIVE_DQ_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ) -/*IP Blk = CA_PAR_ERR Access=RW */ -#define LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ 0x00000000UL - /* INIT_CA_PARITY_ERROR_GEN_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD) -/*IP Blk = CA_PAR_ERR Access=RW */ -#define LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD 0x00000000UL - /* INIT_CA_PARITY_ERROR_GEN_CMD [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_RDDATA_EN) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_RDDATA_EN 0x00000015UL - /* CFG_DFI_T_RDDATA_EN [0:32] RW value= 0x15 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT 0x00000006UL - /* CFG_DFI_T_PHY_RDLAT [0:32] RW value= 0x6 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT 0x00000003UL - /* CFG_DFI_T_PHY_WRLAT [0:32] RW value= 0x3 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_PHYUPD_EN) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_PHYUPD_EN 0x00000001UL - /* CFG_DFI_PHYUPD_EN [0:32] RW value= 0x00000001 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_LP_DATA_REQ) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_LP_DATA_REQ 0x00000000UL - /* INIT_DFI_LP_DATA_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ 0x00000000UL - /* INIT_DFI_LP_CTRL_REQ [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_LP_WAKEUP) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_LP_WAKEUP 0x00000000UL - /* INIT_DFI_LP_WAKEUP [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE 0x00000000UL - /* INIT_DFI_DRAM_CLK_DISABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE 0x00000000UL - /* CFG_DFI_DATA_BYTE_DISABLE [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_LVL_SEL) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_LVL_SEL 0x00000000UL - /* CFG_DFI_LVL_SEL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_LVL_PERIODIC) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_LVL_PERIODIC 0x00000000UL - /* CFG_DFI_LVL_PERIODIC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_DFI_LVL_PATTERN) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_CFG_DFI_LVL_PATTERN 0x00000000UL - /* CFG_DFI_LVL_PATTERN [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_DFI_INIT_START) -/*IP Blk = DFI Access=RW */ -#define LIBERO_SETTING_PHY_DFI_INIT_START 0x00000001UL - /* PHY_DFI_INIT_START [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI1_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI1_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI2_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1 0x00000000UL - /* CFG_AXI_START_ADDRESS_AXI2_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0 0xFFFFFFFFUL - /* CFG_AXI_END_ADDRESS_AXI1_0 [0:32] RW value= 0xFFFFFFFF */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1 0x00000003UL - /* CFG_AXI_END_ADDRESS_AXI1_1 [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 0xFFFFFFFFUL - /* CFG_AXI_END_ADDRESS_AXI2_0 [0:32] RW value= 0xFFFFFFFF */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 0x00000003UL - /* CFG_AXI_END_ADDRESS_AXI2_1 [0:32] RW value= 0x00000003 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI1_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI1_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI2_0 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1 0x00000000UL - /* CFG_MEM_START_ADDRESS_AXI2_1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1 0x00000000UL - /* CFG_ENABLE_BUS_HOLD_AXI1 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2 0x00000000UL - /* CFG_ENABLE_BUS_HOLD_AXI2 [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_CFG_AXI_AUTO_PCH) -/*IP Blk = AXI_IF Access=RW */ -#define LIBERO_SETTING_CFG_AXI_AUTO_PCH 0x00000000UL - /* CFG_AXI_AUTO_PCH [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_RESET_CONTROL) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_RESET_CONTROL 0x00008001UL - /* PHY_RESET_CONTROL [0:32] RW value= 0x8001 */ -#endif -#if !defined (LIBERO_SETTING_PHY_PC_RANK) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_PC_RANK 0x00000001UL - /* PHY_PC_RANK [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_PHY_RANKS_TO_TRAIN) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_RANKS_TO_TRAIN 0x00000001UL - /* PHY_RANKS_TO_TRAIN [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_PHY_WRITE_REQUEST) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_WRITE_REQUEST 0x00000000UL - /* PHY_WRITE_REQUEST [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_READ_REQUEST) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_READ_REQUEST 0x00000000UL - /* PHY_READ_REQUEST [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY 0x00000000UL - /* PHY_WRITE_LEVEL_DELAY [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_GATE_TRAIN_DELAY) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_GATE_TRAIN_DELAY 0x0000003FUL - /* PHY_GATE_TRAIN_DELAY [0:32] RW value= 0x3F */ -#endif -#if !defined (LIBERO_SETTING_PHY_EYE_TRAIN_DELAY) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_EYE_TRAIN_DELAY 0x0000003FUL - /* PHY_EYE_TRAIN_DELAY [0:32] RW value= 0x3F */ -#endif -#if !defined (LIBERO_SETTING_PHY_EYE_PAT) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_EYE_PAT 0x00000000UL - /* PHY_EYE_PAT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_START_RECAL) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_START_RECAL 0x00000000UL - /* PHY_START_RECAL [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC 0x00000000UL - /* PHY_CLR_DFI_LVL_PERIODIC [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE 0x00000018UL - /* PHY_TRAIN_STEP_ENABLE [0:32] RW value= 0x18 */ -#endif -#if !defined (LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT 0x00000000UL - /* PHY_LPDDR_DQ_CAL_PAT [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_INDPNDT_TRAINING) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_INDPNDT_TRAINING 0x00000001UL - /* PHY_INDPNDT_TRAINING [0:32] RW value= 0x1 */ -#endif -#if !defined (LIBERO_SETTING_PHY_ENCODED_QUAD_CS) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_ENCODED_QUAD_CS 0x00000000UL - /* PHY_ENCODED_QUAD_CS [0:32] RW value= 0x00000000 */ -#endif -#if !defined (LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE) -/*IP Blk = csr_custom Access=RW */ -#define LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE 0x00000000UL - /* PHY_HALF_CLK_DLY_ENABLE [0:32] RW value= 0x00000000 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_DDRC_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/general/hw_gen_peripherals.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/general/hw_gen_peripherals.h deleted file mode 100644 index ccc37c1..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/general/hw_gen_peripherals.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_gen_peripherals.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_gen_peripherals.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_GEN_PERIPHERALS_H_ -#define HW_GEN_PERIPHERALS_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_GPIO_CR) -/*GPIO Blocks reset control- (soft_reset options chossen in Libero confgurator) -*/ -#define LIBERO_SETTING_GPIO_CR 0x000F0703UL - /* GPIO0_SOFT_RESET_SELECT [0:2] RW value= 0x3 */ - /* GPIO0_DEFAULT [4:2] RW value= 0x0 */ - /* GPIO1_SOFT_RESET_SELECT [8:3] RW value= 0x7 */ - /* GPIO1_DEFAULT [12:3] RW value= 0x0 */ - /* GPIO2_SOFT_RESET_SELECT [16:4] RW value= 0xF */ - /* GPIO2_DEFAULT [20:4] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_CR_INFO) -/*Information on how Crypto setup on this MPFS */ -#define LIBERO_SETTING_CRYPTO_CR_INFO 0x00000000UL - /* MSS_MODE [0:2] RO */ - /* RESERVED [2:1] RO */ - /* STREAM_ENABLE [3:1] RO */ - /* RESERVED1 [4:28] RO */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_GEN_PERIPHERALS_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/hw_platform.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/hw_platform.h deleted file mode 100644 index 60e645b..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/hw_platform.h +++ /dev/null @@ -1,79 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_platform.h - * @author Embedded Software - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_platform.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PLATFORM_H_ -#define HW_PLATFORM_H_ - -#include "memory_map/hw_memory.h" -#include "memory_map/hw_apb_split.h" -#include "memory_map/hw_cache.h" -#include "memory_map/hw_pmp_hart0.h" -#include "memory_map/hw_pmp_hart1.h" -#include "memory_map/hw_pmp_hart2.h" -#include "memory_map/hw_pmp_hart3.h" -#include "memory_map/hw_pmp_hart4.h" -#include "memory_map/hw_mpu_fic0.h" -#include "memory_map/hw_mpu_fic1.h" -#include "memory_map/hw_mpu_fic2.h" -#include "memory_map/hw_mpu_crypto.h" -#include "memory_map/hw_mpu_gem0.h" -#include "memory_map/hw_mpu_gem1.h" -#include "memory_map/hw_mpu_usb.h" -#include "memory_map/hw_mpu_mmc.h" -#include "memory_map/hw_mpu_scb.h" -#include "memory_map/hw_mpu_trace.h" -#include "io/hw_mssio_mux.h" -#include "io/hw_hsio_mux.h" -#include "sgmii/hw_sgmii_tip.h" -#include "ddr/hw_ddr_options.h" -#include "ddr/hw_ddr_io_bank.h" -#include "ddr/hw_ddr_mode.h" -#include "ddr/hw_ddr_off_mode.h" -#include "ddr/hw_ddr_segs.h" -#include "ddr/hw_ddrc.h" -#include "clocks/hw_mss_clks.h" -#include "clocks/hw_clk_sysreg.h" -#include "clocks/hw_clk_mss_pll.h" -#include "clocks/hw_clk_sgmii_pll.h" -#include "clocks/hw_clk_ddr_pll.h" -#include "clocks/hw_clk_mss_cfm.h" -#include "clocks/hw_clk_sgmii_cfm.h" -#include "general/hw_gen_peripherals.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* No content in this file, used for referencing header */ - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PLATFORM_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/io/hw_hsio_mux.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/io/hw_hsio_mux.h deleted file mode 100644 index e857172..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/io/hw_hsio_mux.h +++ /dev/null @@ -1,61 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_hsio_mux.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_hsio_mux.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_HSIO_MUX_H_ -#define HW_HSIO_MUX_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_TRIM_OPTIONS) -/*User trim options- set option to 1 to use */ -#define LIBERO_SETTING_TRIM_OPTIONS 0x00000000UL - /* TRIM_DDR_OPTION [0:1] */ - /* TRIM_SGMII_OPTION [1:1] */ -#endif -#if !defined (LIBERO_SETTING_DDR_IOC_REG0) -/*Manual trim values */ -#define LIBERO_SETTING_DDR_IOC_REG0 0x00000000UL - /* BANK_PCODE [0:6] RW value= 0x0 */ - /* BANK_NCODE [6:6] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SGMII_IOC_REG0) -/*Manual trim values */ -#define LIBERO_SETTING_SGMII_IOC_REG0 0x00000000UL - /* BANK_PCODE [0:6] RW value= 0x0 */ - /* BANK_NCODE [6:6] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_HSIO_MUX_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/io/hw_mssio_mux.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/io/hw_mssio_mux.h deleted file mode 100644 index 40d9c20..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/io/hw_mssio_mux.h +++ /dev/null @@ -1,313 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mssio_mux.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mssio_mux.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MSSIO_MUX_H_ -#define HW_MSSIO_MUX_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_IOMUX0_CR) -/*Selects whether the peripheral is connected to the Fabric or IOMUX structure. -*/ -#define LIBERO_SETTING_IOMUX0_CR 0x00000000UL - /* SPI0_FABRIC [0:1] RW value= 0x0 */ - /* SPI1_FABRIC [1:1] RW value= 0x0 */ - /* I2C0_FABRIC [2:1] RW value= 0x0 */ - /* I2C1_FABRIC [3:1] RW value= 0x0 */ - /* CAN0_FABRIC [4:1] RW value= 0x0 */ - /* CAN1_FABRIC [5:1] RW value= 0x0 */ - /* QSPI_FABRIC [6:1] RW value= 0x0 */ - /* MMUART0_FABRIC [7:1] RW value= 0x0 */ - /* MMUART1_FABRIC [8:1] RW value= 0x0 */ - /* MMUART2_FABRIC [9:1] RW value= 0x0 */ - /* MMUART3_FABRIC [10:1] RW value= 0x0 */ - /* MMUART4_FABRIC [11:1] RW value= 0x0 */ - /* MDIO0_FABRIC [12:1] RW value= 0x0 */ - /* MDIO1_FABRIC [13:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_IOMUX1_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX1_CR 0xFFFFFFFFUL - /* PAD0 [0:4] RW value= 0xF */ - /* PAD1 [4:4] RW value= 0xF */ - /* PAD2 [8:4] RW value= 0xF */ - /* PAD3 [12:4] RW value= 0xF */ - /* PAD4 [16:4] RW value= 0xF */ - /* PAD5 [20:4] RW value= 0xF */ - /* PAD6 [24:4] RW value= 0xF */ - /* PAD7 [28:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX2_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX2_CR 0x00FFFFFFUL - /* PAD8 [0:4] RW value= 0xF */ - /* PAD9 [4:4] RW value= 0xF */ - /* PAD10 [8:4] RW value= 0xF */ - /* PAD11 [12:4] RW value= 0xF */ - /* PAD12 [16:4] RW value= 0xF */ - /* PAD13 [20:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX3_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX3_CR 0x5555555FUL - /* PAD14 [0:4] RW value= 0xF */ - /* PAD15 [4:4] RW value= 0x5 */ - /* PAD16 [8:4] RW value= 0x5 */ - /* PAD17 [12:4] RW value= 0x5 */ - /* PAD18 [16:4] RW value= 0x5 */ - /* PAD19 [20:4] RW value= 0x5 */ - /* PAD20 [24:4] RW value= 0x5 */ - /* PAD21 [28:4] RW value= 0x5 */ -#endif -#if !defined (LIBERO_SETTING_IOMUX4_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX4_CR 0xFFFFF555UL - /* PAD22 [0:4] RW value= 0x5 */ - /* PAD23 [4:4] RW value= 0x5 */ - /* PAD24 [8:4] RW value= 0x5 */ - /* PAD25 [12:4] RW value= 0xF */ - /* PAD26 [16:4] RW value= 0xF */ - /* PAD27 [20:4] RW value= 0xF */ - /* PAD28 [24:4] RW value= 0xF */ - /* PAD29 [28:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX5_CR) -/*Configures the IO Mux structure for each IO pad. See the MSS MAS -specification for for description. */ -#define LIBERO_SETTING_IOMUX5_CR 0xFFFFFFFFUL - /* PAD30 [0:4] RW value= 0xF */ - /* PAD31 [4:4] RW value= 0xF */ - /* PAD32 [8:4] RW value= 0xF */ - /* PAD33 [12:4] RW value= 0xF */ - /* PAD34 [16:4] RW value= 0xF */ - /* PAD35 [20:4] RW value= 0xF */ - /* PAD36 [24:4] RW value= 0xF */ - /* PAD37 [28:4] RW value= 0xF */ -#endif -#if !defined (LIBERO_SETTING_IOMUX6_CR) -/*Sets whether the MMC/SD Voltage select lines are inverted on entry to the -IOMUX structure */ -#define LIBERO_SETTING_IOMUX6_CR 0x00000000UL - /* VLT_SEL [0:1] RW value= 0x0 */ - /* VLT_EN [1:1] RW value= 0x0 */ - /* VLT_CMD_DIR [2:1] RW value= 0x0 */ - /* VLT_DIR_0 [3:1] RW value= 0x0 */ - /* VLT_DIR_1_3 [4:1] RW value= 0x0 */ - /* SD_LED [5:1] RW value= 0x0 */ - /* SD_VOLT_0 [6:1] RW value= 0x0 */ - /* SD_VOLT_1 [7:1] RW value= 0x0 */ - /* SD_VOLT_2 [8:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_CFG_CR) -/*Configures the MSSIO block using SCB write */ -#define LIBERO_SETTING_MSSIO_BANK4_CFG_CR 0x00080907UL - /* BANK_PCODE [0:6] RW value= 0x7 */ - /* RESERVED0 [6:2] RW value= 0x00 */ - /* BANK_NCODE [8:6] RW value= 0x9 */ - /* RESERVED1 [14:2] RW value= 0x0 */ - /* VS [16:4] RW value= 0x8 */ - /* RESERVED2 [20:12] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR 0x08290829UL - /* IO_CFG_0 [0:16] RW value= 0x0829 */ - /* IO_CFG_1 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR 0x08290829UL - /* IO_CFG_2 [0:16] RW value= 0x0829 */ - /* IO_CFG_3 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR 0x08290829UL - /* IO_CFG_4 [0:16] RW value= 0x0829 */ - /* IO_CFG_5 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR 0x08290829UL - /* IO_CFG_6 [0:16] RW value= 0x0829 */ - /* IO_CFG_7 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR 0x08290829UL - /* IO_CFG_8 [0:16] RW value= 0x0829 */ - /* IO_CFG_9 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR 0x08290829UL - /* IO_CFG_10 [0:16] RW value= 0x0829 */ - /* IO_CFG_11 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR 0x08290829UL - /* IO_CFG_12 [0:16] RW value= 0x0829 */ - /* IO_CFG_13 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_CFG_CR) -/*Configures the MSSIO block using SCB write */ -#define LIBERO_SETTING_MSSIO_BANK2_CFG_CR 0x00080907UL - /* BANK_PCODE [0:6] RW value= 0x7 */ - /* RESERVED0 [6:2] RW value= 0x00 */ - /* BANK_NCODE [8:6] RW value= 0x9 */ - /* RESERVED1 [14:2] RW value= 0x0 */ - /* VS [16:4] RW value= 0x8 */ - /* RESERVED2 [20:12] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR 0x08290829UL - /* IO_CFG_0 [0:16] RW value= 0x0829 */ - /* IO_CFG_1 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR 0x08290829UL - /* IO_CFG_2 [0:16] RW value= 0x0829 */ - /* IO_CFG_3 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR 0x08290829UL - /* IO_CFG_4 [0:16] RW value= 0x0829 */ - /* IO_CFG_5 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR 0x08290829UL - /* IO_CFG_6 [0:16] RW value= 0x0829 */ - /* IO_CFG_7 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR 0x08290829UL - /* IO_CFG_8 [0:16] RW value= 0x0829 */ - /* IO_CFG_9 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR 0x08290829UL - /* IO_CFG_10 [0:16] RW value= 0x0829 */ - /* IO_CFG_11 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR 0x08290829UL - /* IO_CFG_12 [0:16] RW value= 0x0829 */ - /* IO_CFG_13 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR 0x08290829UL - /* IO_CFG_14 [0:16] RW value= 0x0829 */ - /* IO_CFG_15 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR 0x08290829UL - /* IO_CFG_16 [0:16] RW value= 0x0829 */ - /* IO_CFG_17 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR 0x08290829UL - /* IO_CFG_18 [0:16] RW value= 0x0829 */ - /* IO_CFG_19 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR 0x08290829UL - /* IO_CFG_20 [0:16] RW value= 0x0829 */ - /* IO_CFG_21 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR) -/*IO electrical configuration for MSSIO pad */ -#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR 0x08290829UL - /* IO_CFG_22 [0:16] RW value= 0x0829 */ - /* IO_CFG_23 [16:16] RW value= 0x0829 */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_VB2_CFG) -/*default dpc values for MSSIO bank 2 */ -#define LIBERO_SETTING_MSSIO_VB2_CFG 0x00000828UL - /* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */ - /* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */ - /* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */ - /* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */ - /* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */ - /* RESERVED [15:17] R */ -#endif -#if !defined (LIBERO_SETTING_MSSIO_VB4_CFG) -/*default dpc values for MSSIO bank 4 */ -#define LIBERO_SETTING_MSSIO_VB4_CFG 0x00000828UL - /* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */ - /* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */ - /* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */ - /* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */ - /* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */ - /* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */ - /* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */ - /* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */ - /* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */ - /* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */ - /* RESERVED [15:17] R */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MSSIO_MUX_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_apb_split.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_apb_split.h deleted file mode 100644 index e9e7187..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_apb_split.h +++ /dev/null @@ -1,74 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_apb_split.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_apb_split.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_APB_SPLIT_H_ -#define HW_APB_SPLIT_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_APBBUS_CR) -/*AMP Mode peripheral mapping register. When the register bit is '0' the -peripheral is mapped into the 0x2000000 address range using AXI bus 5 from the -Coreplex. When the register bit is '1' the peripheral is mapped into the -0x28000000 address range using AXI bus 6 from the Coreplex. */ -#define LIBERO_SETTING_APBBUS_CR 0x00000000UL - /* MMUART0 [0:1] RWC */ - /* MMUART1 [1:1] RWC */ - /* MMUART2 [2:1] RWC */ - /* MMUART3 [3:1] RWC */ - /* MMUART4 [4:1] RWC */ - /* WDOG0 [5:1] RWC */ - /* WDOG1 [6:1] RWC */ - /* WDOG2 [7:1] RWC */ - /* WDOG3 [8:1] RWC */ - /* WDOG4 [9:1] RWC */ - /* SPI0 [10:1] RWC */ - /* SPI1 [11:1] RWC */ - /* I2C0 [12:1] RWC */ - /* I2C1 [13:1] RWC */ - /* CAN0 [14:1] RWC */ - /* CAN1 [15:1] RWC */ - /* GEM0 [16:1] RWC */ - /* GEM1 [17:1] RWC */ - /* TIMER [18:1] RWC */ - /* GPIO0 [19:1] RWC */ - /* GPIO1 [20:1] RWC */ - /* GPIO2 [21:1] RWC */ - /* RTC [22:1] RWC */ - /* H2FINT [23:1] RWC */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_APB_SPLIT_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_cache.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_cache.h deleted file mode 100644 index edbbf47..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_cache.h +++ /dev/null @@ -1,149 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_cache.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_cache.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_CACHE_H_ -#define HW_CACHE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_WAY_ENABLE) -/*Way indexes less than or equal to this register value may be used by the -cache */ -#define LIBERO_SETTING_WAY_ENABLE 0x00000007UL - /* WAY_ENABLE [0:8] RW value= 0x7 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M0) -/*Way mask register master 0 (hart0) */ -#define LIBERO_SETTING_WAY_MASK_M0 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M1) -/*Way mask register master 1 (hart1) */ -#define LIBERO_SETTING_WAY_MASK_M1 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M2) -/*Way mask register master 2 (hart2) */ -#define LIBERO_SETTING_WAY_MASK_M2 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M3) -/*Way mask register master 3 (hart3) */ -#define LIBERO_SETTING_WAY_MASK_M3 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M4) -/*Way mask register master 4 (hart4) */ -#define LIBERO_SETTING_WAY_MASK_M4 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_CACHE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_memory.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_memory.h deleted file mode 100644 index ee347e6..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_memory.h +++ /dev/null @@ -1,98 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_memory.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_memory.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MEMORY_H_ -#define HW_MEMORY_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART0) -/*Reset vector hart0 */ -#define LIBERO_SETTING_RESET_VECTOR_HART0 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART0_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART1) -/*Reset vector hart1 */ -#define LIBERO_SETTING_RESET_VECTOR_HART1 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART1_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART2) -/*Reset vector hart2 */ -#define LIBERO_SETTING_RESET_VECTOR_HART2 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART2_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART3) -/*Reset vector hart3 */ -#define LIBERO_SETTING_RESET_VECTOR_HART3 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART3_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_RESET_VECTOR_HART4) -/*Reset vector hart4 */ -#define LIBERO_SETTING_RESET_VECTOR_HART4 0x20220000 -#define LIBERO_SETTING_RESET_VECTOR_HART4_SIZE 0x4 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_32_CACHE) -/*example instance of memory */ -#define LIBERO_SETTING_DDR_32_CACHE 0x80000000 -#define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_32_NON_CACHE) -/*example instance */ -#define LIBERO_SETTING_DDR_32_NON_CACHE 0xC0000000 -#define LIBERO_SETTING_DDR_32_NON_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_64_CACHE) -/*64 bit address */ -#define LIBERO_SETTING_DDR_64_CACHE 0x1000000000 -#define LIBERO_SETTING_DDR_64_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_64_NON_CACHE) -/*64 bit address */ -#define LIBERO_SETTING_DDR_64_NON_CACHE 0x1400000000 -#define LIBERO_SETTING_DDR_64_NON_CACHE_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_32_WCB) -/*example instance */ -#define LIBERO_SETTING_DDR_32_WCB 0xD0000000 -#define LIBERO_SETTING_DDR_32_WCB_SIZE 0x100000 /* Length of memory block*/ -#endif -#if !defined (LIBERO_SETTING_DDR_64_WCB) -/*64 bit address */ -#define LIBERO_SETTING_DDR_64_WCB 0x1800000000 -#define LIBERO_SETTING_DDR_64_WCB_SIZE 0x100000 /* Length of memory block*/ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MEMORY_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_crypto.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_crypto.h deleted file mode 100644 index 43d505e..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_crypto.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_crypto.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_crypto.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_CRYPTO_H_ -#define HW_MPU_CRYPTO_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_CRYPTO_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic0.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic0.h deleted file mode 100644 index 553581f..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic0.h +++ /dev/null @@ -1,155 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_fic0.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_fic0.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_FIC0_H_ -#define HW_MPU_FIC0_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP8) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP9) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP10) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP11) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP12) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP13) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP14) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP15) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC0_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_FIC0_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic1.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic1.h deleted file mode 100644 index 2cfac91..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic1.h +++ /dev/null @@ -1,155 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_fic1.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_fic1.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_FIC1_H_ -#define HW_MPU_FIC1_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP8) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP9) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP10) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP11) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP12) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP13) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP14) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP15) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC1_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_FIC1_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic2.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic2.h deleted file mode 100644 index 1a803c6..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_fic2.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_fic2.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_fic2.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_FIC2_H_ -#define HW_MPU_FIC2_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_FIC2_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_FIC2_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem0.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem0.h deleted file mode 100644 index 418aa95..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem0.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_gem0.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_gem0.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_GEM0_H_ -#define HW_MPU_GEM0_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_GEM0_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem1.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem1.h deleted file mode 100644 index 14fa46d..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_gem1.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_gem1.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_gem1.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_GEM1_H_ -#define HW_MPU_GEM1_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_GEM1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_GEM1_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_mmc.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_mmc.h deleted file mode 100644 index a36d15c..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_mmc.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_mmc.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_mmc.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_MMC_H_ -#define HW_MPU_MMC_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_MMC_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_MMC_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_scb.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_scb.h deleted file mode 100644 index 810182e..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_scb.h +++ /dev/null @@ -1,99 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_scb.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_scb.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_SCB_H_ -#define HW_MPU_SCB_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP4) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP5) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP6) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP7) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_SCB_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_SCB_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_trace.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_trace.h deleted file mode 100644 index 34309bb..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_trace.h +++ /dev/null @@ -1,57 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_trace.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_trace.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_TRACE_H_ -#define HW_MPU_TRACE_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_TRACE_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_TRACE_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_TRACE_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_usb.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_usb.h deleted file mode 100644 index 45e8cd2..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_mpu_usb.h +++ /dev/null @@ -1,71 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_mpu_usb.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_mpu_usb.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_MPU_USB_H_ -#define HW_MPU_USB_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP0) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP1) -/*mpu setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP2) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif -#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP3) -/*pmp setup register, 64 bits */ -#define LIBERO_SETTING_USB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL - /* PMP [0:38] RW value= 0xFFFFFFFFF */ - /* RESERVED [38:18] RW value= 0x0 */ - /* MODE [56:8] RW value= 0x1F */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_MPU_USB_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart0.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart0.h deleted file mode 100644 index b822a87..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart0.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart0.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart0.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART0_H_ -#define HW_PMP_HART0_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART0_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x00 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x00 */ - /* PMP3CFG [24:8] RW value= 0x00 */ - /* PMP4CFG [32:8] RW value= 0x00 */ - /* PMP5CFG [40:8] RW value= 0x00 */ - /* PMP6CFG [48:8] RW value= 0x00 */ - /* PMP7CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART0_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x00 */ - /* PMP9CFG [8:8] RW value= 0x00 */ - /* PMP10CFG [16:8] RW value= 0x00 */ - /* PMP11CFG [24:8] RW value= 0x00 */ - /* PMP12CFG [32:8] RW value= 0x00 */ - /* PMP13CFG [40:8] RW value= 0x00 */ - /* PMP14CFG [48:8] RW value= 0x00 */ - /* PMP15CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART0_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x00 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART0_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart1.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart1.h deleted file mode 100644 index 966b27d..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart1.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart1.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart1.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART1_H_ -#define HW_PMP_HART1_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART1_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x00 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x00 */ - /* PMP3CFG [24:8] RW value= 0x00 */ - /* PMP4CFG [32:8] RW value= 0x00 */ - /* PMP5CFG [40:8] RW value= 0x00 */ - /* PMP6CFG [48:8] RW value= 0x00 */ - /* PMP7CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART1_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x00 */ - /* PMP9CFG [8:8] RW value= 0x00 */ - /* PMP10CFG [16:8] RW value= 0x00 */ - /* PMP11CFG [24:8] RW value= 0x00 */ - /* PMP12CFG [32:8] RW value= 0x00 */ - /* PMP13CFG [40:8] RW value= 0x00 */ - /* PMP14CFG [48:8] RW value= 0x00 */ - /* PMP15CFG [56:8] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x00 */ -#endif -#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART1_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x00 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART1_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart2.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart2.h deleted file mode 100644 index 011e2e1..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart2.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart2.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart2.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART2_H_ -#define HW_PMP_HART2_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART2_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x0 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x0 */ - /* PMP3CFG [24:8] RW value= 0x0 */ - /* PMP4CFG [32:8] RW value= 0x0 */ - /* PMP5CFG [40:8] RW value= 0x0 */ - /* PMP6CFG [48:8] RW value= 0x0 */ - /* PMP7CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART2_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x0 */ - /* PMP9CFG [8:8] RW value= 0x0 */ - /* PMP10CFG [16:8] RW value= 0x0 */ - /* PMP11CFG [24:8] RW value= 0x0 */ - /* PMP12CFG [32:8] RW value= 0x0 */ - /* PMP13CFG [40:8] RW value= 0x0 */ - /* PMP14CFG [48:8] RW value= 0x0 */ - /* PMP15CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART2_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART2_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart3.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart3.h deleted file mode 100644 index 2cb3ae0..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart3.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart3.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart3.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART3_H_ -#define HW_PMP_HART3_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART3_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x0 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x0 */ - /* PMP3CFG [24:8] RW value= 0x0 */ - /* PMP4CFG [32:8] RW value= 0x0 */ - /* PMP5CFG [40:8] RW value= 0x0 */ - /* PMP6CFG [48:8] RW value= 0x0 */ - /* PMP7CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART3_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x0 */ - /* PMP9CFG [8:8] RW value= 0x0 */ - /* PMP10CFG [16:8] RW value= 0x0 */ - /* PMP11CFG [24:8] RW value= 0x0 */ - /* PMP12CFG [32:8] RW value= 0x0 */ - /* PMP13CFG [40:8] RW value= 0x0 */ - /* PMP14CFG [48:8] RW value= 0x0 */ - /* PMP15CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART3_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART3_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart4.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart4.h deleted file mode 100644 index d2ce0d0..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/memory_map/hw_pmp_hart4.h +++ /dev/null @@ -1,165 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_pmp_hart4.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_pmp_hart4.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_PMP_HART4_H_ -#define HW_PMP_HART4_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG0) -/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART4_CSR_PMPCFG0 0x0000000000000000ULL - /* PMP0CFG [0:8] RW value= 0x0 */ - /* PMP1CFG [8:8] RW value= 0x0 */ - /* PMP2CFG [16:8] RW value= 0x0 */ - /* PMP3CFG [24:8] RW value= 0x0 */ - /* PMP4CFG [32:8] RW value= 0x0 */ - /* PMP5CFG [40:8] RW value= 0x0 */ - /* PMP6CFG [48:8] RW value= 0x0 */ - /* PMP7CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG2) -/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 -execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */ -#define LIBERO_SETTING_HART4_CSR_PMPCFG2 0x0000000000000000ULL - /* PMP8CFG [0:8] RW value= 0x0 */ - /* PMP9CFG [8:8] RW value= 0x0 */ - /* PMP10CFG [16:8] RW value= 0x0 */ - /* PMP11CFG [24:8] RW value= 0x0 */ - /* PMP12CFG [32:8] RW value= 0x0 */ - /* PMP13CFG [40:8] RW value= 0x0 */ - /* PMP14CFG [48:8] RW value= 0x0 */ - /* PMP15CFG [56:8] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR0) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR0 0x0000000000000000ULL - /* CSR_PMPADDR0 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR1) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR1 0x0000000000000000ULL - /* CSR_PMPADDR1 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR2) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR2 0x0000000000000000ULL - /* CSR_PMPADDR2 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR3) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR3 0x0000000000000000ULL - /* CSR_PMPADDR3 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR4) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR4 0x0000000000000000ULL - /* CSR_PMPADDR4 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR5) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR5 0x0000000000000000ULL - /* CSR_PMPADDR5 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR6) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR6 0x0000000000000000ULL - /* CSR_PMPADDR6 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR7) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR7 0x0000000000000000ULL - /* CSR_PMPADDR7 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR8) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR8 0x0000000000000000ULL - /* CSR_PMPADDR8 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR9) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR9 0x0000000000000000ULL - /* CSR_PMPADDR9 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR10) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR10 0x0000000000000000ULL - /* CSR_PMPADDR10 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR11) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR11 0x0000000000000000ULL - /* CSR_PMPADDR11 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR12) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR12 0x0000000000000000ULL - /* CSR_PMPADDR12 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR13) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR13 0x0000000000000000ULL - /* CSR_PMPADDR13 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR14) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR14 0x0000000000000000ULL - /* CSR_PMPADDR14 [0:64] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR15) -/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte -in CSR_PMPCFGx */ -#define LIBERO_SETTING_HART4_CSR_PMPADDR15 0x0000000000000000ULL - /* CSR_PMPADDR15 [0:64] RW value= 0x0 */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_PMP_HART4_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/sgmii/hw_sgmii_tip.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/sgmii/hw_sgmii_tip.h deleted file mode 100644 index e11f33e..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_config/sgmii/hw_sgmii_tip.h +++ /dev/null @@ -1,197 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * @file hw_sgmii_tip.h - * @author Microchip-FPGA Embedded Systems Solutions - * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: PFSOC_MSS_C0 - * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:18:34 - * Format version of XML description: 0.3.8 - * PolarFire SoC Configuration Generator version: 0.4.1 - * - * Note 1: This file should not be edited. If you need to modify a parameter, - * without going through the Libero flow or editing the associated xml file, - * the following method is recommended: - * 1. edit the file platform//config//software//mpfs_hal//mss_sw_config.h - * 2. define the value you want to override there. (Note: There is a - * commented example in mss_sw_config.h) - * Note 2: The definition in mss_sw_config.h takes precedence, as - * mss_sw_config.h is included prior to the hw_sgmii_tip.h in the hal - * (see platform//mpfs_hal//mss_hal.h) - * - */ - -#ifndef HW_SGMII_TIP_H_ -#define HW_SGMII_TIP_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined (LIBERO_SETTING_SGMII_MODE) -/*SGMII mode control (SEU) */ -#define LIBERO_SETTING_SGMII_MODE 0x08C0E60CUL - /* REG_PLL_EN [0:1] RW value= 0x0 */ - /* REG_DLL_EN [1:1] RW value= 0x0 */ - /* REG_PVT_EN [2:1] RW value= 0x1 */ - /* REG_BC_VRGEN_EN [3:1] RW value= 0x1 */ - /* REG_TX0_EN [4:1] RW value= 0x0 */ - /* REG_RX0_EN [5:1] RW value= 0x0 */ - /* REG_TX1_EN [6:1] RW value= 0x0 */ - /* REG_RX1_EN [7:1] RW value= 0x0 */ - /* REG_DLL_LOCK_FLT [8:2] RW value= 0x2 */ - /* REG_DLL_ADJ_CODE [10:4] RW value= 0x9 */ - /* REG_CH0_CDR_RESET_B [14:1] RW value= 0x1 */ - /* REG_CH1_CDR_RESET_B [15:1] RW value= 0x1 */ - /* REG_BC_VRGEN [16:6] RW value= 0x00 */ - /* REG_CDR_MOVE_STEP [22:1] RW value= 0x1 */ - /* REG_REFCLK_EN_RDIFF [23:1] RW value= 0x1 */ - /* REG_BC_VS [24:4] RW value= 0x8 */ - /* REG_REFCLK_EN_UDRIVE_P [28:1] RW value= 0x0 */ - /* REG_REFCLK_EN_INS_HYST_P [29:1] RW value= 0x0 */ - /* REG_REFCLK_EN_UDRIVE_N [30:1] RW value= 0x0 */ - /* REG_REFCLK_EN_INS_HYST_N [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_PLL_CNTL) -/*PLL control register (SEU) */ -#define LIBERO_SETTING_PLL_CNTL 0x80140101UL - /* REG_PLL_POSTDIV [0:7] RW value= 0x01 */ - /* ARO_PLL0_LOCK [7:1] RO */ - /* REG_PLL_RFDIV [8:6] RW value= 0x01 */ - /* REG_PLL_REG_RFCLK_SEL [14:1] RW value= 0x0 */ - /* REG_PLL_LP_REQUIRES_LOCK [15:1] RW value= 0x0 */ - /* REG_PLL_INTIN [16:12] RW value= 0x014 */ - /* REG_PLL_BWI [28:2] RW value= 0x0 */ - /* REG_PLL_BWP [30:2] RW value= 0x2 */ -#endif -#if !defined (LIBERO_SETTING_CH0_CNTL) -/*Channel0 control register */ -#define LIBERO_SETTING_CH0_CNTL 0x00FC0000UL - /* REG_TX0_WPU_P [0:1] RW value= 0x0 */ - /* REG_TX0_WPD_P [1:1] RW value= 0x0 */ - /* REG_TX0_SLEW_P [2:2] RW value= 0x0 */ - /* REG_TX0_DRV_P [4:4] RW value= 0x0 */ - /* REG_TX0_ODT_P [8:4] RW value= 0x0 */ - /* REG_TX0_ODT_STATIC_P [12:3] RW value= 0x0 */ - /* REG_RX0_TIM_LONG [15:1] RW value= 0x0 */ - /* REG_RX0_WPU_P [16:1] RW value= 0x0 */ - /* REG_RX0_WPD_P [17:1] RW value= 0x0 */ - /* REG_RX0_IBUFMD_P [18:3] RW value= 0x7 */ - /* REG_RX0_EYEWIDTH_P [21:3] RW value= 0x7 */ - /* REG_RX0_ODT_P [24:4] RW value= 0x0 */ - /* REG_RX0_ODT_STATIC_P [28:3] RW value= 0x0 */ - /* REG_RX0_EN_FLAG_N [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_CH1_CNTL) -/*Channel1 control register */ -#define LIBERO_SETTING_CH1_CNTL 0x00FC0000UL - /* REG_TX1_WPU_P [0:1] RW value= 0x0 */ - /* REG_TX1_WPD_P [1:1] RW value= 0x0 */ - /* REG_TX1_SLEW_P [2:2] RW value= 0x0 */ - /* REG_TX1_DRV_P [4:4] RW value= 0x0 */ - /* REG_TX1_ODT_P [8:4] RW value= 0x0 */ - /* REG_TX1_ODT_STATIC_P [12:3] RW value= 0x0 */ - /* REG_RX1_TIM_LONG [15:1] RW value= 0x0 */ - /* REG_RX1_WPU_P [16:1] RW value= 0x0 */ - /* REG_RX1_WPD_P [17:1] RW value= 0x0 */ - /* REG_RX1_IBUFMD_P [18:3] RW value= 0x7 */ - /* REG_RX1_EYEWIDTH_P [21:3] RW value= 0x7 */ - /* REG_RX1_ODT_P [24:4] RW value= 0x0 */ - /* REG_RX1_ODT_STATIC_P [28:3] RW value= 0x0 */ - /* REG_RX1_EN_FLAG_N [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_RECAL_CNTL) -/*Recalibration control register */ -#define LIBERO_SETTING_RECAL_CNTL 0x000020C8UL - /* REG_RECAL_DIFF_RANGE [0:5] RW value= 0x8 */ - /* REG_RECAL_START_EN [5:1] RW value= 0x0 */ - /* REG_PVT_CALIB_START [6:1] RW value= 0x1 */ - /* REG_PVT_CALIB_LOCK [7:1] RW value= 0x1 */ - /* REG_RECAL_UPD [8:1] RW value= 0x0 */ - /* BC_VRGEN_DIRECTION [9:1] RW value= 0x0 */ - /* BC_VRGEN_LOAD [10:1] RW value= 0x0 */ - /* BC_VRGEN_MOVE [11:1] RW value= 0x0 */ - /* REG_PVT_REG_CALIB_CLKDIV [12:2] RW value= 0x2 */ - /* REG_PVT_REG_CALIB_DIFFR_VSEL [14:2] RW value= 0x0 */ - /* SRO_DLL_90_CODE [16:7] RO */ - /* SRO_DLL_LOCK [23:1] RO */ - /* SRO_DLL_ST_CODE [24:7] RO */ - /* SRO_RECAL_START [31:1] RO */ -#endif -#if !defined (LIBERO_SETTING_CLK_CNTL) -/*Clock input and routing control registers */ -#define LIBERO_SETTING_CLK_CNTL 0xF00050CCUL - /* REG_REFCLK_EN_TERM_P [0:2] RW value= 0x0 */ - /* REG_REFCLK_EN_RXMODE_P [2:2] RW value= 0x3 */ - /* REG_REFCLK_EN_TERM_N [4:2] RW value= 0x0 */ - /* REG_REFCLK_EN_RXMODE_N [6:2] RW value= 0x3 */ - /* REG_REFCLK_CLKBUF_EN_PULLUP [8:1] RW value= 0x0 */ - /* REG_CLKMUX_FCLK_SEL [9:3] RW value= 0x0 */ - /* REG_CLKMUX_PLL0_RFCLK0_SEL [12:2] RW value= 0x1 */ - /* REG_CLKMUX_PLL0_RFCLK1_SEL [14:2] RW value= 0x1 */ - /* REG_CLKMUX_SPARE0 [16:16] RW value= 0xf000 */ -#endif -#if !defined (LIBERO_SETTING_DYN_CNTL) -/*Dynamic control registers */ -#define LIBERO_SETTING_DYN_CNTL 0x00000400UL - /* REG_PLL_DYNEN [0:1] RW value= 0x0 */ - /* REG_DLL_DYNEN [1:1] RW value= 0x0 */ - /* REG_PVT_DYNEN [2:1] RW value= 0x0 */ - /* REG_BC_DYNEN [3:1] RW value= 0x0 */ - /* REG_CLKMUX_DYNEN [4:1] RW value= 0x0 */ - /* REG_LANE0_DYNEN [5:1] RW value= 0x0 */ - /* REG_LANE1_DYNEN [6:1] RW value= 0x0 */ - /* BC_VRGEN_OOR [7:1] RO */ - /* REG_PLL_SOFT_RESET_PERIPH [8:1] RW value= 0x0 */ - /* REG_DLL_SOFT_RESET_PERIPH [9:1] RW value= 0x0 */ - /* REG_PVT_SOFT_RESET_PERIPH [10:1] RW value= 0x1 */ - /* REG_BC_SOFT_RESET_PERIPH [11:1] RW value= 0x0 */ - /* REG_CLKMUX_SOFT_RESET_PERIPH [12:1] RW value= 0x0 */ - /* REG_LANE0_SOFT_RESET_PERIPH [13:1] RW value= 0x0 */ - /* REG_LANE1_SOFT_RESET_PERIPH [14:1] RW value= 0x0 */ - /* PVT_CALIB_STATUS [15:1] RO */ - /* ARO_PLL0_VCO0PH_SEL [16:3] RO */ - /* ARO_PLL0_VCO1PH_SEL [19:3] RO */ - /* ARO_PLL0_VCO2PH_SEL [22:3] RO */ - /* ARO_PLL0_VCO3PH_SEL [25:3] RO */ - /* ARO_REF_DIFFR [28:4] RO */ -#endif -#if !defined (LIBERO_SETTING_PVT_STAT) -/*PVT calibrator status registers */ -#define LIBERO_SETTING_PVT_STAT 0x00000000UL - /* ARO_REF_PCODE [0:6] RO */ - /* ARO_IOEN_BNK [6:1] RO */ - /* ARO_IOEN_BNK_B [7:1] RO */ - /* ARO_REF_NCODE [8:6] RO */ - /* ARO_CALIB_STATUS [14:1] RO */ - /* ARO_CALIB_STATUS_B [15:1] RO */ - /* ARO_PCODE [16:6] RO */ - /* ARO_CALIB_INTRPT [22:1] RO */ - /* PVT_CALIB_INTRPT [23:1] RO */ - /* ARO_NCODE [24:6] RO */ - /* PVT_CALIB_LOCK [30:1] RW value= 0x0 */ - /* PVT_CALIB_START [31:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_SPARE_CNTL) -/*Spare control register */ -#define LIBERO_SETTING_SPARE_CNTL 0xFF000000UL - /* REG_SPARE [0:32] RW value= 0xff000000 */ -#endif -#if !defined (LIBERO_SETTING_SPARE_STAT) -/*Spare status register */ -#define LIBERO_SETTING_SPARE_STAT 0x00000000UL - /* SRO_SPARE [0:32] RO */ -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* #ifdef HW_SGMII_TIP_H_ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_fpga_design/xml/PFSOC_MSS_C0_0..xml b/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_fpga_design/xml/PFSOC_MSS_C0_0..xml deleted file mode 100644 index 19226e4..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/custom-board/soc_fpga_design/xml/PFSOC_MSS_C0_0..xml +++ /dev/null @@ -1,3221 +0,0 @@ - - - 12.900.0.16-PFSOC_MSS:2.0.108 - PFSOC_MSS_C0 - MPFS250T_ES - FCVG484_Eval - 06-26-2020_16:18:34 - 0.3.8 - - - - - 0x20220000 - 0x20220000 - 0x20220000 - 0x20220000 - 0x20220000 - 0x80000000 - 0xC0000000 - 0x1000000000 - 0x1400000000 - 0xD0000000 - 0x1800000000 - - - - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 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- - 0x0 - - - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - - - - - 0x1 - 0x1 - 0x0 - - - 0x5 - - - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x3 - 0x0 - 0x0 - 0x0 - 0x3 - 0x0 - 0x1 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - - - - - - - 0x3 - 0x0 - 0x7 - 0x0 - 0xF - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - - - - - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/drivers_config/readme.txt b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/drivers_config/readme.txt new file mode 100644 index 0000000..d05a6a9 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/drivers_config/readme.txt @@ -0,0 +1,5 @@ +contains user configuration of the drivers. +drivers config should follow the following format: +platform/config/drivers//_sw_cfg.h +e.g +platform/config/drivers/ddr/ddr_sw_cfg.h \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h new file mode 100644 index 0000000..70ad981 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h @@ -0,0 +1,404 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/******************************************************************************* + * + * Platform definitions + * Version based on requirements of MPFS MSS + * + */ + /*========================================================================*//** + @mainpage Sample file detailing how mss_sw_config.h should be constructed for + the MPFS MSS + + @section intro_sec Introduction + The mss_sw_config.h is to be located in the project + ./src/platform/config/software/mpfs_hal directory. + This file must be hand crafted when using the MPFS MSS. + + + @section + +*//*==========================================================================*/ + + +#ifndef USER_CONFIG_MSS_USER_CONFIG_H_ +#define USER_CONFIG_MSS_USER_CONFIG_H_ + +/*------------------------------------------------------------------------------ + * MPFS_HAL_FIRST_HART and MPFS_HAL_LAST_HART defines used to specify which + * harts to actually start. + * Set MPFS_HAL_FIRST_HART to a value other than 0 if you do not want your code + * to start and execute code on the E51 hart. + * Set MPFS_HAL_LAST_HART to a value smaller than 4 if you do not wish to use + * all U54 harts. + * Harts that are not started will remain in an infinite WFI loop unless used + * through some other method + */ +#ifndef MPFS_HAL_FIRST_HART +#define MPFS_HAL_FIRST_HART 0 +#endif + +#ifndef MPFS_HAL_LAST_HART +#define MPFS_HAL_LAST_HART 4 +#endif + +/*------------------------------------------------------------------------------ + * Markers used to indicate startup status of hart + */ +#define HLS_DATA_IN_WFI 0x12345678U +#define HLS_DATA_PASSED_WFI 0x87654321U + +/*------------------------------------------------------------------------------ + * Define the size of the HLS used + * In our HAL, we are using Hart Local storage for debug data storage only + * as well as flags for wfi instruction management. + * The TLS will take memory from top of the stack if allocated + * + */ +#define HLS_DEBUG_AREA_SIZE 64 + +/* define the required tick rate in Milliseconds */ +/* if this program is running on one hart only, only that particular hart value + * will be used */ +#define HART0_TICK_RATE_MS 5UL +#define HART1_TICK_RATE_MS 5UL +#define HART2_TICK_RATE_MS 5UL +#define HART3_TICK_RATE_MS 5UL +#define HART4_TICK_RATE_MS 5UL + +#define H2F_BASE_ADDRESS 0x20126000 /* or 0x28126000 */ + +/* + * define how you want the Bus Error Unit configured + */ +#define BEU_ENABLE 0x0ULL +#define BEU_PLIC_INT 0x0ULL +#define BEU_LOCAL_INT 0x0ULL + +/* + * Clear memory on startup + * 0 => do not clear DTIM and L2 + * 1 => Clears memory + */ +#ifndef MPFS_HAL_CLEAR_MEMORY +#define MPFS_HAL_CLEAR_MEMORY 1 +#endif + +/* + * MPFS_HAL_HW_CONFIG + * Conditional compile switch is used to determine if MPFS HAL will perform the + * hardware configurations or not. + * Defined => This program acts as a First stage bootloader and performs + * hardware configurations. + * Not defined => This program assumes that the hardware configurations are + * already performed (Typically by a previous boot stage) + * + * List of items initialised when MPFS_HAL_HW_CONFIG is enabled + * - load virtual rom (see load_virtual_rom(void) in system_startup.c) + * - l2 cache config + * - Bus error unit config + * - MPU config + * - pmp config + * - I/O, clock and clock mux's, DDR and SGMII + * - will start other harts, see text describing MPFS_HAL_FIRST_HART, + * MPFS_HAL_LAST_HART above + */ +#ifndef MPFS_HAL_HW_CONFIG +#define MPFS_HAL_HW_CONFIG +#endif + +/* + * If not using item, comment out line below + */ +//#define SGMII_SUPPORT +//#define DDR_SUPPORT +#define MSSIO_SUPPORT +//#define SIMULATION_TEST_FEEDBACK +//#define E51_ENTER_SLEEP_STATE + +/* + * DDR software options + */ +#define DDR_FULL_32BIT_NC_CHECK_EN + +#define PATTERN_INCREMENTAL (0x01U << 0U) +#define PATTERN_WALKING_ONE (0x01U << 1U) +#define PATTERN_WALKING_ZERO (0x01U << 2U) +#define PATTERN_RANDOM (0x01U << 3U) +#define PATTERN_0xCCCCCCCC (0x01U << 4U) +#define PATTERN_0x55555555 (0x01U << 5U) +#define PATTERN_ZEROS (0x01U << 6U) +#define MAX_NO_PATTERNS 7U +/* number of test writes to perform */ +#define SW_CFG_NUM_READS_WRITES 0x20000U +/* + * what test patterns to write/read on start-up + * */ +#define SW_CONFIG_PATTERN (PATTERN_INCREMENTAL|\ + PATTERN_WALKING_ONE|\ + PATTERN_WALKING_ZERO|\ + PATTERN_RANDOM|\ + PATTERN_0xCCCCCCCC|\ + PATTERN_0x55555555) +/* Training types status offsets */ +#define BCLK_SCLK_BIT (0x1U<<0U) +#define ADDCMD_BIT (0x1U<<1U) +#define WRLVL_BIT (0x1U<<2U) +#define RDGATE_BIT (0x1U<<3U) +#define DQ_DQS_BIT (0x1U<<4U) +/* The first five bits represent the currently supported training in the TIP */ +/* This value will not change unless more training possibilities are added to + * the TIP */ +#define TRAINING_MASK (BCLK_SCLK_BIT|\ + ADDCMD_BIT|\ + WRLVL_BIT|\ + RDGATE_BIT|\ + DQ_DQS_BIT) +/* + * Debug DDR startup through a UART + * Comment out in normal operation. May be useful for debug purposes in bring-up + * of a new board design. + * See the weak function setup_ddr_debug_port(mss_uart_instance_t * uart) + * If you need to edit this function, make a copy of of the function without the + * weak declaration in your application code. + * */ +#define DEBUG_DDR_INIT +#define DEBUG_DDR_RD_RW_FAIL +//#define DEBUG_DDR_RD_RW_PASS +//#define DEBUG_DDR_CFG_DDR_SGMII_PHY +#define DEBUG_DDR_DDRCFG + + +/* + * During development we need to locally overwrite some values coming from + * Libero + * These are placed below here + */ +/* + * If using DDR4, enable DDR4__CODE_TAG_0_2 define + */ +//#define DDR4__CODE_TAG_0_2 + +/* + * You can over write any on the settings coming from Libero here + * + * e.g. Define how you want SEG registers configured, if you want to change from + * the default settings + */ + +#define LIBERO_SETTING_SEG0_0 (-(0x0080000000LL >> 24U)) +#define LIBERO_SETTING_SEG0_1 (-(0x1000000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_2 (-(0x00C0000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_3 (-(0x1400000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_4 (-(0x00D0000000LL >> 24U)) +#define LIBERO_SETTING_SEG1_5 (-(0x1800000000LL >> 24U)) + +/* comment out any of these defines if you do not want to sweep values + * SUPPORT_ADDR_CMD_OFFSET_SWEEP + * SUPPORT_BCLK_SCLK_SWEEP + * SUPPORT_DPC_SWEEP + * Alternatively, modify the sweep values. This helps when calibrating a new + * board design. Enabling DEBUG_DDR_INIT define above will display the + * calibration sweep. + */ +//#define SWEEP_ENABLED +#define SUPPORT_ADDR_CMD_OFFSET_SWEEP +#define SUPPORT_BCLK_SCLK_SWEEP +#define SUPPORT_DPC_SWEEP + +#define LIBERO_SETTING_MAX_ADDRESS_CMD_OFFSET 4UL +#define LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET 2UL +#define MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS ((LIBERO_SETTING_MAX_ADDRESS_CMD_OFFSET-LIBERO_SETTING_MIN_ADDRESS_CMD_OFFSET) +1U) + +#define LIBERO_SETTING_MAX_ADDRESS_BCLK_SCLK_OFFSET 5UL +#define LIBERO_SETTING_MIN_ADDRESS_BCLK_SCLK_OFFSET 5UL +#define MAX_NUMBER__BCLK_SCLK_OFFSET_SWEEPS ((LIBERO_SETTING_MAX_ADDRESS_BCLK_SCLK_OFFSET-LIBERO_SETTING_MIN_ADDRESS_BCLK_SCLK_OFFSET)+1U) + +#define LIBERO_SETTING_MAX_DPC_V_GEN 9UL +#define LIBERO_SETTING_MIN_DPC_V_GEN 9UL +#define MAX_NUMBER_DPC_V_GEN_SWEEPS ((LIBERO_SETTING_MAX_DPC_V_GEN-LIBERO_SETTING_MIN_DPC_V_GEN)+1U) + +#define LIBERO_SETTING_MAX_DPC_H_GEN 2UL +#define LIBERO_SETTING_MIN_DPC_H_GEN 2UL +#define MAX_NUMBER_DPC_H_GEN_SWEEPS ((LIBERO_SETTING_MAX_DPC_H_GEN-LIBERO_SETTING_MIN_DPC_H_GEN)+1U) + +#define LIBERO_SETTING_MAX_DPC_VS_GEN 2UL +#define LIBERO_SETTING_MIN_DPC_VS_GEN 2UL +#define MAX_NUMBER_DPC_VS_GEN_SWEEPS ((LIBERO_SETTING_MAX_DPC_VS_GEN-LIBERO_SETTING_MIN_DPC_VS_GEN)+1U) + +/* + * Define SW_CONFIG_LPDDR_WR_CALIB_FN if we want to use lpddr4 wr calib function + */ +//#define SW_CONFIG_LPDDR_WR_CALIB_FN +/* + * Temporally write Icicle/peripheral board differences here + */ +#define ICICLE_BOARD +#ifdef ICICLE_BOARD + +/* + * over-write value from Libero todo: remove once verified in Libero design + */ + +#define LIBERO_SETTING_MSSIO_BANK2_CFG_CR 0x00080907UL + /* BANK_PCODE [0:6] RW value= 0x7 */ + /* RESERVED0 [6:2] RW value= 0x00 */ + /* BANK_NCODE [8:6] RW value= 0x9 */ + /* RESERVED1 [14:2] RW value= 0x0 */ + /* VS [16:4] RW value= 0x8 */ + /* RESERVED2 [20:12] RW value= 0x0 */ +#define LIBERO_SETTING_MSSIO_BANK4_CFG_CR 0x00080907UL + /* BANK_PCODE [0:6] RW value= 0x7 */ + /* RESERVED0 [6:2] RW value= 0x00 */ + /* BANK_NCODE [8:6] RW value= 0x9 */ + /* RESERVED1 [14:2] RW value= 0x0 */ + /* VS [16:4] RW value= 0x8 */ + /* RESERVED2 [20:12] RW value= 0x0 */ + + +//#define LIBERO_SETTING_DPC_BITS 0x00049432UL +#define LIBERO_SETTING_DPC_BITS 0x00049432UL // Received from SVG 5/14/2020 +#define LIBERO_SETTING_DDRPHY_MODE 0x00014B24UL +#define LIBERO_SETTING_DATA_LANES_USED 0x00000004UL +#define LIBERO_SETTING_CFG_DQ_WIDTH 0x00000000UL + +#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02AUL // 0x07CFE02AUL//0x07CFE02AUL + /* ADDCMD_OFFSET [0:3] RW value= 0x2 5*/ + /* BCKLSCLK_OFFSET [3:3] RW value= 0x4 */ + /* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */ + /* READ_GATE_MIN_READS [13:8] RW value= 0x1F */ + /* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */ + +/* + * over write value from Libero + */ +#define LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT 0x00000003UL + +/* + * Temporarily over write values from Libero + */ +#define LIBERO_SETTING_RPC_ODT_ADDCMD 2 +#define LIBERO_SETTING_RPC_ODT_CLK 2 +#define LIBERO_SETTING_RPC_ODT_DQ 6 //6 +#define LIBERO_SETTING_RPC_ODT_DQS 6 //2 for peripheral board + +#else /* peripheral board */ +/* + * over-write value from Libero todo: remove once verifid in Libero design + */ +#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07C3E035UL //0x07C3E025UL + /* ADDCMD_OFFSET [0:3] RW value= 0x2 5*/ + /* BCKLSCLK_OFFSET [3:3] RW value= 0x4 */ + /* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */ + /* READ_GATE_MIN_READS [13:8] RW value= 0x1F */ + /* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */ + +/* + * over write value from Libero + */ +#define LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT 0x00000003UL + +/* + * Temporarily over write values from Libero + */ +#define LIBERO_SETTING_RPC_ODT_ADDCMD 2 +#define LIBERO_SETTING_RPC_ODT_CLK 2 +#define LIBERO_SETTING_RPC_ODT_DQ 6 +#define LIBERO_SETTING_RPC_ODT_DQS 2 + +#endif /* not ICICLE */ + +/* + * 0 implies all IP traing's used. This should be the default + * setting. + */ +#define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000000UL +/* + * 1 implies sw BCLK_SCK traing carried out before IP training. This should be + * the default + * setting. + */ +#define USE_SW_BCLK_SCK_TRAINING 0x00000001UL +#define SW_TRAING_BCLK_SCLK_OFFSET 0x00000006UL + +/* + * 0x6DU => setting vref_ca to 40% + * This (0x6DU) is the default setting. + * */ +#define DDR_MODE_REG_VREF_VALUE 0x6DU + +/* + * Will review address settings in Libero, tie in, sanity check with SEG + * settings + */ +#define LIBERO_SETTING_DDR_32_NON_CACHE 0xC0000000ULL + +/** + * \brief MPU configuration from Libero for FIC0 + * + */ +#define LIBERO_SETTING_FIC0_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for FIC1 0x1F00000FFFFFFFFF + * + */ +#define LIBERO_SETTING_FIC1_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for FIC2 + * + */ +#define LIBERO_SETTING_FIC2_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for ATHENA + * + */ +#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for GEM0 + * + */ +#define LIBERO_SETTING_GEM0_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for GEM1 + * + */ +#define LIBERO_SETTING_GEM1_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for MMC + * + */ +#define LIBERO_SETTING_MMC_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for SCB + * + */ +#define LIBERO_SETTING_SCB_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for USB + * + */ +#define LIBERO_SETTING_USB_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +/** + * \brief MPU configuration from Libero for TRACE + * + */ +#define LIBERO_SETTING_TRACE_MPU_CFG_PMP0 0x1F00000FFFFFFFFF + +#endif /* USER_CONFIG_MSS_USER_CONFIG_H_ */ + diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/readme.txt b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/readme.txt new file mode 100644 index 0000000..086c9f1 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/platform_config/mpfs_hal_config/readme.txt @@ -0,0 +1,2 @@ +contains user configuration of the platform +e.g. division of memory between harts etc. \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h index 181e2d1..5e28a5f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_ddr_pll.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_ddr_pll.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h index 9f58ec0..fd52530 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_cfm.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_mss_cfm.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h index 553f6d3..0066c57 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_mss_pll.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_mss_pll.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h index 802611b..205e76a 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_cfm.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_sgmii_cfm.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h index 390dcfb..939ab74 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sgmii_pll.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_sgmii_pll.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h index 15f5742..fcf24a2 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_clk_sysreg.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_clk_sysreg.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h index 064aeac..ef17cf3 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/clocks/hw_mss_clks.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mss_clks.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h index 3dacb22..40c6df9 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_io_bank.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_io_bank.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, @@ -120,17 +120,388 @@ CA/CK Check at ioa pc bit */ #define LIBERO_SETTING_RPC_SPARE0_DQ 0x00008000UL /* RPC_SPARE0_DQ [0:32] RW value= 0x8000 */ #endif +#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000F00UL + /* MSS_DDR_CK0 [0:1] RW value= 0x0 */ + /* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */ + /* MSS_DDR_A0 [2:1] RW value= 0x0 */ + /* MSS_DDR_A1 [3:1] RW value= 0x0 */ + /* MSS_DDR_A2 [4:1] RW value= 0x0 */ + /* MSS_DDR_A3 [5:1] RW value= 0x0 */ + /* MSS_DDR_A4 [6:1] RW value= 0x0 */ + /* MSS_DDR_A5 [7:1] RW value= 0x0 */ + /* MSS_DDR_A6 [8:1] RW value= 0x1 */ + /* MSS_DDR_A7 [9:1] RW value= 0x1 */ + /* MSS_DDR_A8 [10:1] RW value= 0x1 */ + /* MSS_DDR_A9 [11:1] RW value= 0x1 */ +#endif #if !defined (LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10) -/*0x2000 7428 OVRT10 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000000UL - /* RPC_EN_ADDCMD1_OVRT10 [0:32] RW value= 0x0 */ +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000FFFUL + /* MSS_DDR_CK1 [0:1] RW value= 0x1 */ + /* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */ + /* MSS_DDR_A10 [2:1] RW value= 0x1 */ + /* MSS_DDR_A11 [3:1] RW value= 0x1 */ + /* MSS_DDR_A12 [4:1] RW value= 0x1 */ + /* MSS_DDR_A13 [5:1] RW value= 0x1 */ + /* MSS_DDR_A14 [6:1] RW value= 0x1 */ + /* MSS_DDR_A15 [7:1] RW value= 0x1 */ + /* MSS_DDR_A16 [8:1] RW value= 0x1 */ + /* MSS_DDR3_WE_N [9:1] RW value= 0x1 */ + /* MSS_DDR_BA0 [10:1] RW value= 0x1 */ + /* MSS_DDR_BA1 [11:1] RW value= 0x1 */ #endif #if !defined (LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11) -/*0x2000 742C OVRT11 - physical configurations of LPDDR4, given the twindie -architecture */ -#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000120UL - /* RPC_EN_ADDCMD2_OVRT11 [0:32] RW value= 0x120 */ +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000FE6UL + /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */ + /* MSS_DDR_BG0 [1:1] RW value= 0x1 */ + /* MSS_DDR_BG1 [2:1] RW value= 0x1 */ + /* MSS_DDR_CS0 [3:1] RW value= 0x0 */ + /* MSS_DDR_CKE0 [4:1] RW value= 0x0 */ + /* MSS_DDR_ODT0 [5:1] RW value= 0x1 */ + /* MSS_DDR_CS1 [6:1] RW value= 0x1 */ + /* MSS_DDR_CKE1 [7:1] RW value= 0x1 */ + /* MSS_DDR_ODT1 [8:1] RW value= 0x1 */ + /* MSS_DDR_ACT_N [9:1] RW value= 0x1 */ + /* MSS_DDR_PARITY [10:1] RW value= 0x1 */ + /* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA0_OVRT12) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA0_OVRT12 0x00000000UL + /* MSS_DDR_DQ0 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ1 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ2 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ3 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ4 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ5 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ6 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ7 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM0 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA1_OVRT13) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA1_OVRT13 0x00000000UL + /* MSS_DDR_DQ8 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ9 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ10 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ11 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ12 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ13 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ14 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ15 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM1 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA2_OVRT14) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA2_OVRT14 0x00000000UL + /* MSS_DDR_DQ16 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ17 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ18 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ19 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ20 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ21 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ22 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ23 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM2 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_DATA3_OVRT15) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_DATA3_OVRT15 0x00000000UL + /* MSS_DDR_DQ24 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ25 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ26 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ27 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ28 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ29 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ30 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ31 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM3 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC_EN_ECC_OVRT16) +/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding +to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC_EN_ECC_OVRT16 0x0000007FUL + /* MSS_DDR_DQ32 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ33 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ34 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ35 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */ + /* MSS_DDR_DM4 [6:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC235_WPD_ADD_CMD0) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC235_WPD_ADD_CMD0 0x00000000UL + /* MSS_DDR_CK0 [0:1] RW value= 0x0 */ + /* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */ + /* MSS_DDR_A0 [2:1] RW value= 0x0 */ + /* MSS_DDR_A1 [3:1] RW value= 0x0 */ + /* MSS_DDR_A2 [4:1] RW value= 0x0 */ + /* MSS_DDR_A3 [5:1] RW value= 0x0 */ + /* MSS_DDR_A4 [6:1] RW value= 0x0 */ + /* MSS_DDR_A5 [7:1] RW value= 0x0 */ + /* MSS_DDR_A6 [8:1] RW value= 0x0 */ + /* MSS_DDR_A7 [9:1] RW value= 0x0 */ + /* MSS_DDR_A8 [10:1] RW value= 0x0 */ + /* MSS_DDR_A9 [11:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC236_WPD_ADD_CMD1) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC236_WPD_ADD_CMD1 0x00000000UL + /* MSS_DDR_CK1 [0:1] RW value= 0x0 */ + /* MSS_DDR_CK_N1 [1:1] RW value= 0x0 */ + /* MSS_DDR_A10 [2:1] RW value= 0x0 */ + /* MSS_DDR_A11 [3:1] RW value= 0x0 */ + /* MSS_DDR_A12 [4:1] RW value= 0x0 */ + /* MSS_DDR_A13 [5:1] RW value= 0x0 */ + /* MSS_DDR_A14 [6:1] RW value= 0x0 */ + /* MSS_DDR_A15 [7:1] RW value= 0x0 */ + /* MSS_DDR_A16 [8:1] RW value= 0x0 */ + /* MSS_DDR3_WE_N [9:1] RW value= 0x0 */ + /* MSS_DDR_BA0 [10:1] RW value= 0x0 */ + /* MSS_DDR_BA1 [11:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC237_WPD_ADD_CMD2) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. Note: For LPDDR4 need +to over-ride MSS_DDR_ODT0 and MSS_DDR_ODT1 and eanble PU i.e. (set OVR_EN ==1 , +wpu == 0 , wpd == 1 ) */ +#define LIBERO_SETTING_RPC237_WPD_ADD_CMD2 0x00000120UL + /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */ + /* MSS_DDR_BG0 [1:1] RW value= 0x0 */ + /* MSS_DDR_BG1 [2:1] RW value= 0x0 */ + /* MSS_DDR_CS0 [3:1] RW value= 0x0 */ + /* MSS_DDR_CKE0 [4:1] RW value= 0x0 */ + /* MSS_DDR_ODT0 [5:1] RW value= 0x1 */ + /* MSS_DDR_CS1 [6:1] RW value= 0x0 */ + /* MSS_DDR_CKE1 [7:1] RW value= 0x0 */ + /* MSS_DDR_ODT1 [8:1] RW value= 0x1 */ + /* MSS_DDR_ACT_N [9:1] RW value= 0x0 */ + /* MSS_DDR_PARITY [10:1] RW value= 0x0 */ + /* MSS_DDR_ALERT_N [11:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC238_WPD_DATA0) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC238_WPD_DATA0 0x00000000UL + /* MSS_DDR_DQ0 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ1 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ2 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ3 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ4 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ5 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ6 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ7 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM0 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC239_WPD_DATA1) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC239_WPD_DATA1 0x00000000UL + /* MSS_DDR_DQ8 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ9 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ10 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ11 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ12 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ13 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ14 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ15 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM1 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC240_WPD_DATA2) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC240_WPD_DATA2 0x00000000UL + /* MSS_DDR_DQ16 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ17 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ18 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ19 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ20 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ21 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ22 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ23 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM2 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC241_WPD_DATA3) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC241_WPD_DATA3 0x00000000UL + /* MSS_DDR_DQ24 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ25 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ26 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ27 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */ + /* MSS_DDR_DQ28 [6:1] RW value= 0x0 */ + /* MSS_DDR_DQ29 [7:1] RW value= 0x0 */ + /* MSS_DDR_DQ30 [8:1] RW value= 0x0 */ + /* MSS_DDR_DQ31 [9:1] RW value= 0x0 */ + /* MSS_DDR_DM3 [10:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC242_WPD_ECC) +/*Sets pull-downs when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC242_WPD_ECC 0x00000000UL + /* MSS_DDR_DQ32 [0:1] RW value= 0x0 */ + /* MSS_DDR_DQ33 [1:1] RW value= 0x0 */ + /* MSS_DDR_DQ34 [2:1] RW value= 0x0 */ + /* MSS_DDR_DQ35 [3:1] RW value= 0x0 */ + /* MSS_DDR_DQS_P4 [4:1] RW value= 0x0 */ + /* MSS_DDR_DQS_N4 [5:1] RW value= 0x0 */ + /* MSS_DDR_DM4 [6:1] RW value= 0x0 */ +#endif +#if !defined (LIBERO_SETTING_RPC243_WPU_ADD_CMD0) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC243_WPU_ADD_CMD0 0x00000FFFUL + /* MSS_DDR_CK0 [0:1] RW value= 0x1 */ + /* MSS_DDR_CK_N0 [1:1] RW value= 0x1 */ + /* MSS_DDR_A0 [2:1] RW value= 0x1 */ + /* MSS_DDR_A1 [3:1] RW value= 0x1 */ + /* MSS_DDR_A2 [4:1] RW value= 0x1 */ + /* MSS_DDR_A3 [5:1] RW value= 0x1 */ + /* MSS_DDR_A4 [6:1] RW value= 0x1 */ + /* MSS_DDR_A5 [7:1] RW value= 0x1 */ + /* MSS_DDR_A6 [8:1] RW value= 0x1 */ + /* MSS_DDR_A7 [9:1] RW value= 0x1 */ + /* MSS_DDR_A8 [10:1] RW value= 0x1 */ + /* MSS_DDR_A9 [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC244_WPU_ADD_CMD1) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC244_WPU_ADD_CMD1 0x00000FFFUL + /* MSS_DDR_CK1 [0:1] RW value= 0x1 */ + /* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */ + /* MSS_DDR_A10 [2:1] RW value= 0x1 */ + /* MSS_DDR_A11 [3:1] RW value= 0x1 */ + /* MSS_DDR_A12 [4:1] RW value= 0x1 */ + /* MSS_DDR_A13 [5:1] RW value= 0x1 */ + /* MSS_DDR_A14 [6:1] RW value= 0x1 */ + /* MSS_DDR_A15 [7:1] RW value= 0x1 */ + /* MSS_DDR_A16 [8:1] RW value= 0x1 */ + /* MSS_DDR3_WE_N [9:1] RW value= 0x1 */ + /* MSS_DDR_BA0 [10:1] RW value= 0x1 */ + /* MSS_DDR_BA1 [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC245_WPU_ADD_CMD2) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC245_WPU_ADD_CMD2 0x00000EDFUL + /* MSS_DDR_RAM_RST_N [0:1] RW value= 0x1 */ + /* MSS_DDR_BG0 [1:1] RW value= 0x1 */ + /* MSS_DDR_BG1 [2:1] RW value= 0x1 */ + /* MSS_DDR_CS0 [3:1] RW value= 0x1 */ + /* MSS_DDR_CKE0 [4:1] RW value= 0x1 */ + /* MSS_DDR_ODT0 [5:1] RW value= 0x0 */ + /* MSS_DDR_CS1 [6:1] RW value= 0x1 */ + /* MSS_DDR_CKE1 [7:1] RW value= 0x1 */ + /* MSS_DDR_ODT1 [8:1] RW value= 0x0 */ + /* MSS_DDR_ACT_N [9:1] RW value= 0x1 */ + /* MSS_DDR_PARITY [10:1] RW value= 0x1 */ + /* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC246_WPU_DATA0) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC246_WPU_DATA0 0x000007FFUL + /* MSS_DDR_DQ0 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ1 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ2 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ3 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P0 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N0 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ4 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ5 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ6 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ7 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM0 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC247_WPU_DATA1) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC247_WPU_DATA1 0x000007FFUL + /* MSS_DDR_DQ8 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ9 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ10 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ11 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P1 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N1 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ12 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ13 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ14 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ15 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM1 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC248_WPU_DATA2) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC248_WPU_DATA2 0x000007FFUL + /* MSS_DDR_DQ16 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ17 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ18 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ19 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P2 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N2 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ20 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ21 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ22 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ23 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM2 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC249_WPU_DATA3) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC249_WPU_DATA3 0x000007FFUL + /* MSS_DDR_DQ24 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ25 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ26 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ27 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P3 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N3 [5:1] RW value= 0x1 */ + /* MSS_DDR_DQ28 [6:1] RW value= 0x1 */ + /* MSS_DDR_DQ29 [7:1] RW value= 0x1 */ + /* MSS_DDR_DQ30 [8:1] RW value= 0x1 */ + /* MSS_DDR_DQ31 [9:1] RW value= 0x1 */ + /* MSS_DDR_DM3 [10:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_RPC250_WPU_ECC) +/*Sets pull-ups when override enabled. Each bit corresponding to an IO in +corresponding IOG lane, starting from p_pair0 to n_pair5. */ +#define LIBERO_SETTING_RPC250_WPU_ECC 0x0000007FUL + /* MSS_DDR_DQ32 [0:1] RW value= 0x1 */ + /* MSS_DDR_DQ33 [1:1] RW value= 0x1 */ + /* MSS_DDR_DQ34 [2:1] RW value= 0x1 */ + /* MSS_DDR_DQ35 [3:1] RW value= 0x1 */ + /* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */ + /* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */ + /* MSS_DDR_DM4 [6:1] RW value= 0x1 */ #endif #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h index e94e36e..ac54f96 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_mode.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_mode.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h index f5e283e..0bc2bd9 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_off_mode.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_off_mode.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h index 1f00de1..2face17 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_options.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_options.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h index 98e090e..023b475 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddr_segs.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddr_segs.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h index d62e5bd..47cae9c 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/ddr/hw_ddrc.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_ddrc.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h index 618b869..3e96472 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/general/hw_gen_peripherals.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_gen_peripherals.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/hw_platform.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/hw_platform.h index c289132..5673b0f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/hw_platform.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/hw_platform.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_platform.h * @author Embedded Software * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h index 9f945de..a5465bb 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_hsio_mux.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_hsio_mux.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h index 76137cc..fb58c93 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/io/hw_mssio_mux.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mssio_mux.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h index 196c916..f5f423a 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_apb_split.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_apb_split.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h index 0b12feb..172253b 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_cache.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_cache.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, @@ -35,109 +35,397 @@ extern "C" { #if !defined (LIBERO_SETTING_WAY_ENABLE) /*Way indexes less than or equal to this register value may be used by the -cache */ +cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave +8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is +128KB. */ #define LIBERO_SETTING_WAY_ENABLE 0x00000007UL /* WAY_ENABLE [0:8] RW value= 0x7 */ #endif -#if !defined (LIBERO_SETTING_WAY_MASK_M0) -/*Way mask register master 0 (hart0) */ -#define LIBERO_SETTING_WAY_MASK_M0 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M1) -/*Way mask register master 1 (hart1) */ -#define LIBERO_SETTING_WAY_MASK_M1 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M2) -/*Way mask register master 2 (hart2) */ -#define LIBERO_SETTING_WAY_MASK_M2 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M3) -/*Way mask register master 3 (hart3) */ -#define LIBERO_SETTING_WAY_MASK_M3 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ -#endif -#if !defined (LIBERO_SETTING_WAY_MASK_M4) -/*Way mask register master 4 (hart4) */ -#define LIBERO_SETTING_WAY_MASK_M4 0x00000000UL - /* WAY_MASK_0 [0:1] RW value= 0x0 */ - /* WAY_MASK_1 [1:1] RW value= 0x0 */ - /* WAY_MASK_2 [2:1] RW value= 0x0 */ - /* WAY_MASK_3 [3:1] RW value= 0x0 */ - /* WAY_MASK_4 [4:1] RW value= 0x0 */ - /* WAY_MASK_5 [5:1] RW value= 0x0 */ - /* WAY_MASK_6 [6:1] RW value= 0x0 */ - /* WAY_MASK_7 [7:1] RW value= 0x0 */ - /* WAY_MASK_8 [8:1] RW value= 0x0 */ - /* WAY_MASK_9 [9:1] RW value= 0x0 */ - /* WAY_MASK_10 [10:1] RW value= 0x0 */ - /* WAY_MASK_11 [11:1] RW value= 0x0 */ - /* WAY_MASK_12 [12:1] RW value= 0x0 */ - /* WAY_MASK_13 [13:1] RW value= 0x0 */ - /* WAY_MASK_14 [14:1] RW value= 0x0 */ - /* WAY_MASK_15 [15:1] RW value= 0x0 */ +#if !defined (LIBERO_SETTING_WAY_MASK_DMA) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_DMA 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_0) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_1) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_2) +/*Way mask registerAXI slave port 2. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_3) +/*Way mask register AXI slave port 3. Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_DCACHE) +/*Way mask register E51 data cache (hart0). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_ICACHE) +/*Way mask registerE52 instruction cache (hart0). Set field to zero to disable +way from this master. The available cache ways are 0 to number set in +WAY_ENABLE register. If using scratch pad memory, the ways you want reserved +for scrathpad are not available for selection, you must set to 0. e.g. If three +ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set +to zero for all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_DCACHE) +/*Way mask register data cache (hart1). Set field to zero to disable way from +this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_ICACHE) +/*Way mask register instruction cache (hart1). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_DCACHE) +/*Way mask register data cache (hart2). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_ICACHE) +/*Way mask register instruction cache (hart2). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_DCACHE) +/*Way mask register data cache (hart3). Set field to 1 to disable way from this +master.Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_ICACHE) +/*Way mask register instruction cache(hart3). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_DCACHE) +/*Way mask register data cache (hart4). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_ICACHE) +/*Way mask register instruction cache (hart4). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS) +/*Number of ways reserved for scratchpad. Note 1: This is not a register Note +2: each way is 128KB. Note 3: Embedded software expects cache ways allocated +for scratchpad start at way 0, and work up. */ +#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000000UL + /* NUM_OF_WAYS [0:8] RW value= 0x0 */ #endif #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h index 8b0c956..741f2a3 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_memory.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_memory.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h index 2d3681c..095205d 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_crypto.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_crypto.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h index 2e8559a..4baf682 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic0.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_fic0.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h index 0709c67..dd362dd 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic1.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_fic1.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h index 7d1cf33..fc881af 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_fic2.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_fic2.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h index 6f399a0..70da65f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem0.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_gem0.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h index 695c7f3..c2a1fcd 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_gem1.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_gem1.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h index 97998f9..c9fbf3a 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_mmc.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_mmc.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h index c199275..ebdbbc6 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_scb.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_scb.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h index 55465f9..322307a 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_trace.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_trace.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h index b147f46..850c32a 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_mpu_usb.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_mpu_usb.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h index 63a0fd1..c0f9a4f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart0.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart0.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h index ebaff07..bb89409 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart1.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart1.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h index 735afc1..efed373 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart2.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart2.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h index f74ba05..ac94a7b 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart3.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart3.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h index 14e5796..3c60ffd 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/memory_map/hw_pmp_hart4.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_pmp_hart4.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h index 1ca9d42..90cb36c 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_config/sgmii/hw_sgmii_tip.h @@ -1,16 +1,16 @@ /******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * @file hw_sgmii_tip.h * @author Microchip-FPGA Embedded Systems Solutions * - * Generated using Libero version: 12.900.0.16-PFSOC_MSS:2.0.108 - * Libero design name: ICICLE_MSS + * Generated using Libero version: 2.0 + * Libero design name: mss_pf_cache_rev1 * MPFS part number used in design: MPFS250T_ES - * Date generated by Libero: 06-26-2020_16:47:44 - * Format version of XML description: 0.3.8 + * Date generated by Libero: 10-14-2020_15:34:36 + * Format version of XML description: 0.4.2 * PolarFire SoC Configuration Generator version: 0.4.1 * * Note 1: This file should not be edited. If you need to modify a parameter, @@ -180,7 +180,7 @@ extern "C" { #if !defined (LIBERO_SETTING_SPARE_CNTL) /*Spare control register */ #define LIBERO_SETTING_SPARE_CNTL 0xFF000000UL - /* REG_SPARE [0:32] RW value= 0xff000000 */ + /* REG_SPARE [0:32] RW value= 0xFF000000 */ #endif #if !defined (LIBERO_SETTING_SPARE_STAT) /*Spare status register */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_fpga_design/xml/ICICLE_MSS_0.xml b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_fpga_design/xml/mss_pf_cache_rev1_mss_cfg_8_0_8.xml similarity index 82% rename from examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_fpga_design/xml/ICICLE_MSS_0.xml rename to examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_fpga_design/xml/mss_pf_cache_rev1_mss_cfg_8_0_8.xml index f4bef02..eaffea4 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_fpga_design/xml/ICICLE_MSS_0.xml +++ b/examples/mss-rtc/mpfs-rtc-time/src/boards/icicle-kit-es/soc_fpga_design/xml/mss_pf_cache_rev1_mss_cfg_8_0_8.xml @@ -1,11 +1,11 @@ - 12.900.0.16-PFSOC_MSS:2.0.108 - ICICLE_MSS + 2.0 + mss_pf_cache_rev1 MPFS250T_ES - FCVG484_Eval - 06-26-2020_16:47:44 - 0.3.8 + FCVG484 + 10-14-2020_15:34:36 + 0.4.2 @@ -55,98 +55,281 @@ - + 0x7 - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - - - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 - 0x0 + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 @@ -1320,7 +1503,7 @@ 0x0 - 0xff000000 + 0xFF000000 @@ -1411,11 +1594,314 @@ 0x8000 - - 0x0 - - - 0x120 + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 + 0x1 + 0x1 + 0x0 + 0x0 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x1 + 0x0 + 0x0 + 0x1 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x0 + 0x1 + 0x1 + 0x0 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + + + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 + 0x1 diff --git a/examples/mss-rtc/mpfs-rtc-time/src/middleware/config/readme.txt b/examples/mss-rtc/mpfs-rtc-time/src/middleware/config/readme.txt new file mode 100644 index 0000000..95f6cb2 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/middleware/config/readme.txt @@ -0,0 +1 @@ +contains files relating to configuration of third party modules \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-time/src/middleware/readme.txt b/examples/mss-rtc/mpfs-rtc-time/src/middleware/readme.txt new file mode 100644 index 0000000..0ffaed9 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/middleware/readme.txt @@ -0,0 +1 @@ +contains files relating to third party modules \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.c index 7794e57..9a98eba 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.c @@ -7,7 +7,6 @@ */ #include #include "mpfs_hal/mss_hal.h" -#include "mss_rtc_regs.h" #include "mss_rtc.h" #ifdef __cplusplus @@ -42,6 +41,7 @@ extern "C" { #define MASK_32_BIT 0xFFFFFFFFu #define MAX_PRESCALAR_COUNT 0x03FFFFFFu #define CALENDAR_SHIFT 8u +#define COMPARE_ALL_BITS 0xFFFFFFFFu /*-------------------------------------------------------------------------*//** * Index into look-up table. diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.h index 7eecd8f..002b5d5 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc.h @@ -188,8 +188,6 @@ #ifndef MSS_RTC_H_ #define MSS_RTC_H_ -#include "mss_rtc_regs.h" - #ifdef __cplusplus extern "C" { #endif @@ -233,6 +231,13 @@ extern "C" { #define MSS_RTC_FRIDAY 6u #define MSS_RTC_SATURDAY 7u + +/**************************************************************************//** + MSS RTC module instance base addresses +*/ +#define MSS_RTC_LO_ADDR 0x20124000u +#define MSS_RTC_HI_ADDR 0x28124000u + /***************************************************************************//** MSS RTC base addresses. These definitions provides access to the MSS RTC mapped at two different @@ -273,6 +278,42 @@ typedef struct mss_rtc_calender uint8_t week; } mss_rtc_calender_t ; +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +typedef struct +{ + volatile uint32_t CONTROL_REG ; + volatile uint32_t MODE_REG ; + volatile uint32_t PRESCALER_REG ; + volatile uint32_t ALARM_LOWER_REG ; + volatile uint32_t ALARM_UPPER_REG ; + volatile uint32_t COMPARE_LOWER_REG ; + volatile uint32_t COMPARE_UPPER_REG ; + uint32_t RESERVED0 ; + volatile uint32_t DATE_TIME_LOWER_REG ; + volatile uint32_t DATE_TIME_UPPER_REG ; + + uint32_t RESERVED1[2] ; + volatile uint32_t SECONDS_REG ; + volatile uint32_t MINUTES_REG ; + volatile uint32_t HOURS_REG ; + volatile uint32_t DAY_REG ; + volatile uint32_t MONTH_REG ; + volatile uint32_t YEAR_REG ; + volatile uint32_t WEEKDAY_REG ; + volatile uint32_t WEEK_REG ; + + volatile uint32_t SECONDS_CNT_REG ; + volatile uint32_t MINUTES_CNT_REG ; + volatile uint32_t HOURS_CNT_REG ; + volatile uint32_t DAY_CNT_REG ; + volatile uint32_t MONTH_CNT_REG ; + volatile uint32_t YEAR_CNT_REG ; + volatile uint32_t WEEKDAY_CNT_REG ; + volatile uint32_t WEEK_CNT_REG ; +} RTC_TypeDef; + /*-------------------------------------------------------------------------*//** The MSS_RTC_init() function initializes the RTC driver and hardware to a known state. To initialize the RTC hardware, this function: diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc_regs.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc_regs.h deleted file mode 100644 index fbd580a..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/drivers/mss_rtc/mss_rtc_regs.h +++ /dev/null @@ -1,67 +0,0 @@ - /****************************************************************************** - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * Register bit offsets and masks definitions for PolarFire SoC MSS RTC Driver. - - */ -#ifndef MSS_RTC_REG_H__ -#define MSS_RTC_REG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "mpfs_hal/mss_hal.h" - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ -typedef struct -{ - volatile uint32_t CONTROL_REG ; - volatile uint32_t MODE_REG ; - volatile uint32_t PRESCALER_REG ; - volatile uint32_t ALARM_LOWER_REG ; - volatile uint32_t ALARM_UPPER_REG ; - volatile uint32_t COMPARE_LOWER_REG ; - volatile uint32_t COMPARE_UPPER_REG ; - uint32_t RESERVED0 ; - volatile uint32_t DATE_TIME_LOWER_REG ; - volatile uint32_t DATE_TIME_UPPER_REG ; - - uint32_t RESERVED1[2] ; - volatile uint32_t SECONDS_REG ; - volatile uint32_t MINUTES_REG ; - volatile uint32_t HOURS_REG ; - volatile uint32_t DAY_REG ; - volatile uint32_t MONTH_REG ; - volatile uint32_t YEAR_REG ; - volatile uint32_t WEEKDAY_REG ; - volatile uint32_t WEEK_REG ; - - volatile uint32_t SECONDS_CNT_REG ; - volatile uint32_t MINUTES_CNT_REG ; - volatile uint32_t HOURS_CNT_REG ; - volatile uint32_t DAY_CNT_REG ; - volatile uint32_t MONTH_CNT_REG ; - volatile uint32_t YEAR_CNT_REG ; - volatile uint32_t WEEKDAY_CNT_REG ; - volatile uint32_t WEEK_CNT_REG ; -} RTC_TypeDef; - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define MSS_RTC_LO_ADDR 0x20124000u -#define MSS_RTC_HI_ADDR 0x28124000u - -#define COMPARE_ALL_BITS 0xFFFFFFFFu - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_RTC_REG_H__ */ - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal.h index 282def4..d91def0 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal.h @@ -1,4 +1,4 @@ -/******************************************************************************* +/***************************************************************************//** * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT @@ -49,7 +49,7 @@ void HAL_enable_interrupts( void ); /***************************************************************************//** * Disable all interrupts at the processor core level. - * Return the interrupts enable state before disabling occured so that it can + * Return the interrupts enable state before disabling occurred so that it can * later be restored. */ psr_t HAL_disable_interrupts( void ); diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal_irq.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal_irq.c index d0187dc..2fea28e 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal_irq.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal_irq.c @@ -14,11 +14,7 @@ */ #include #include "hal/hal.h" -#include "mpfs_hal/atomic.h" -#include "mpfs_hal/encoding.h" -#include "mpfs_hal/mcall.h" -#include "mpfs_hal/mss_util.h" -#include "mpfs_hal/mtrap.h" +#include "mpfs_hal/common/mss_util.h" #ifdef __cplusplus extern "C" { diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal_version.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal_version.h new file mode 100644 index 0000000..7d4d31c --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hal_version.h @@ -0,0 +1,50 @@ +#ifndef HAL_VERSION_H +#define HAL_VERSION_H + +/******************************************************************************* + * Copyright 2019-2020 Microchip Corporation. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * + * + */ + +/******************************************************************************* + * @file mpfs_halversion.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief MICROCHIP FPGA Embedded Software Hardware Abstraction layer - HAL + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HAL_VERSION_MAJOR 1 +#define HAL_VERSION_MINOR 8 +#define HAL_VERSION_PATCH 0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_macros.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_macros.h index 2ed2fc6..cab0935 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_macros.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_macros.h @@ -10,15 +10,15 @@ * * Hardware registers access macros. * - * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW + * THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USE FOR NEW * DEVELOPMENT. * - * These macros are used to access peripheral's registers. They allow access to + * These macros are used to access peripheral registers. They allow access to * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should * be done through these macros in order to ease porting across different * processors/bus architectures. * - * Some of these macros also allow to access a specific register field. + * Some of these macros also allow access to a specific register field. * */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.S b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.S index 5e8627f..31352f6 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.S +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.S @@ -1,12 +1,9 @@ -/******************************************************************************* +/***************************************************************************//** * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT * * MPFS HAL Embedded Software - * - */ -/***************************************************************************//** * * Hardware registers access functions. * The implementation of these function is platform and toolchain specific. @@ -45,7 +42,8 @@ HW_set_32bit_reg: * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral * register. * - * R0: addr_t reg_addr + * a0: addr_t reg_addr + * @return 32 bits value read from the peripheral register. */ HW_get_32bit_reg: @@ -106,6 +104,7 @@ HW_set_16bit_reg: * register. * * a0: addr_t reg_addr + * @return 16 bits value read from the peripheral register. */ HW_get_16bit_reg: @@ -167,6 +166,7 @@ HW_set_8bit_reg: * register. * * a0: addr_t reg_addr + * @return 8 bits value read from the peripheral register. */ HW_get_8bit_reg: diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.h index de25342..10ae546 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/hw_reg_access.h @@ -9,9 +9,9 @@ /***************************************************************************//** * * Hardware registers access functions. - * The implementation of these function is platform and toolchain specific. + * The implementation of these function is platform and tool-chain specific. * The functions declared here are implemented using assembler as part of the - * processor/toolchain specific HAL. + * processor/tool-chain specific HAL. * */ #ifndef HW_REG_ACCESS diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/readme.md b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/readme.md new file mode 100644 index 0000000..ce9ae8f --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/hal/readme.md @@ -0,0 +1,41 @@ +=============================================================================== +# hal folder +=============================================================================== + +The HAL folder provides support code for use by the bare metal drivers for the +fabric IP cores. +The HAL folder contains files using a combination of C and assembly source code. + +The hal folder should be included in a PolarFire SoC Embedded project under the +platform directory. See location in the drawing below. + +The hal folder contains: + +* register access functions +* assert macros + +### Project directory strucutre, showing where hal folder sits. + + +---------+ +-----------+ + | src +----->|application| + +---------+ | +-----------+ + | + | +-----------+ + +-->|modules | + | +-----------+ + | + | +-----------+ +---------+ + +-->|platform +---->|config | + +-----------+ | +---------+ + | + | +---------+ + +->|drivers | + | +---------+ + | + | +---------+ + +->|hal | + | +---------+ + | + | +---------+ + +->|mpfs_hal | + +---------+ \ No newline at end of file diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/atomic.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/atomic.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/atomic.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/atomic.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/bits.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/bits.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/bits.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/bits.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/encoding.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/encoding.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/encoding.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/encoding.h index 0c5c256..c86fb17 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/encoding.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/encoding.h @@ -231,22 +231,22 @@ asm volatile ("mv %0, " #reg : "=r"(__tmp)); \ __tmp; }) -#define read_csr(reg) ({ unsigned long __tmp; \ +#define read_csr(reg) __extension__({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) -#define write_csr(reg, val) ({ \ +#define write_csr(reg, val) __extension__({ \ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) #define swap_csr(reg, val) ({ unsigned long __tmp; \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ __tmp; }) -#define set_csr(reg, bit) ({ unsigned long __tmp; \ +#define set_csr(reg, bit) __extension__({ unsigned long __tmp; \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ +#define clear_csr(reg, bit) __extension__({ unsigned long __tmp; \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_assert.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_assert.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_assert.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_assert.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_axiswitch.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_axiswitch.c similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_axiswitch.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_axiswitch.c diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_axiswitch.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_axiswitch.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_axiswitch.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_axiswitch.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_clint.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_clint.c new file mode 100644 index 0000000..051fe47 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_clint.c @@ -0,0 +1,167 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/******************************************************************************* + * + * @file mss_clint.c + * @author Microchip-FPGA Embedded Systems Solutions + * @brief CLINT access data structures and functions. + * + */ +#include "mpfs_hal/mss_hal.h" +#include + +static uint64_t g_systick_increment[5] = {0ULL,0ULL,0ULL,0ULL,0ULL}; + +/** + * call once at startup + * @return + */ +void reset_mtime(void) +{ +#if ROLLOVER_TEST + CLINT->MTIME = 0xFFFFFFFFFFFFF000ULL; +#else + CLINT->MTIME = 0ULL; +#endif +} + +/** + * readmtime + * @return mtime + */ +uint64_t readmtime(void) +{ + return (CLINT->MTIME); +} + +/** + * Configure system tick + * @return SUCCESS or FAIL + */ +uint32_t SysTick_Config(void) +{ + const uint32_t tick_rate[5] = {HART0_TICK_RATE_MS, HART1_TICK_RATE_MS ,HART2_TICK_RATE_MS ,HART3_TICK_RATE_MS ,HART4_TICK_RATE_MS}; + volatile uint32_t ret_val = ERROR; + + uint64_t mhart_id = read_csr(mhartid); + + /* + * We are assuming the tick rate is in milli-seconds + * + * convert RTC frequency into milliseconds and multiple by the tick rate + * + */ + + g_systick_increment[mhart_id] = ((LIBERO_SETTING_MSS_RTC_TOGGLE_CLK/1000U) * tick_rate[mhart_id]); + + if (g_systick_increment[mhart_id] > 0ULL) + { + + CLINT->MTIMECMP[mhart_id] = CLINT->MTIME + g_systick_increment[mhart_id]; + + set_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ + + __enable_irq(); + + ret_val = SUCCESS; + } + + return (ret_val); +} + +/** + * Disable system tick interrupt + */ +void disable_systick(void) +{ + clear_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ + return; +} + + +/*------------------------------------------------------------------------------ + * RISC-V interrupt handler for machine timer interrupts. + */ +void handle_m_timer_interrupt(void) +{ + + volatile uint64_t hart_id = read_csr(mhartid); + volatile uint32_t error_loop; + clear_csr(mie, MIP_MTIP); + + switch(hart_id) + { + case 0U: + SysTick_Handler_h0_IRQHandler(); + break; + case 1U: + SysTick_Handler_h1_IRQHandler(); + break; + case 2U: + SysTick_Handler_h2_IRQHandler(); + break; + case 3U: + SysTick_Handler_h3_IRQHandler(); + break; + case 4U: + SysTick_Handler_h4_IRQHandler(); + break; + default: + while (hart_id != 0U) + { + error_loop++; + } + break; + } + + CLINT->MTIMECMP[read_csr(mhartid)] = CLINT->MTIME + g_systick_increment[hart_id]; + + set_csr(mie, MIP_MTIP); + +} + + +/** + * + */ +void handle_m_soft_interrupt(void) +{ + volatile uint64_t hart_id = read_csr(mhartid); + volatile uint32_t error_loop; + + switch(hart_id) + { + case 0U: + Software_h0_IRQHandler(); + break; + case 1U: + Software_h1_IRQHandler(); + break; + case 2U: + Software_h2_IRQHandler(); + break; + case 3U: + Software_h3_IRQHandler(); + break; + case 4U: + Software_h4_IRQHandler(); + break; + default: + while (hart_id != 0U) + { + error_loop++; + } + break; + } + + /*Clear software interrupt*/ + clear_soft_interrupt(); +} + diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_clint.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_clint.h similarity index 83% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_clint.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_clint.h index 60c90a6..f8cf46e 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_clint.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_clint.h @@ -44,6 +44,7 @@ typedef struct CLINT_Type_t #define CLINT ((CLINT_Type *)CLINT_BASE) + /*============================================================================== * The function raise_soft_interrupt() raises a synchronous software interrupt by * writing into the MSIP register. @@ -70,6 +71,38 @@ static inline void clear_soft_interrupt(void) (void)reg; /* use reg to avoid compiler warning */ } +/* + * return mtime + */ +uint64_t readmtime(void); + +/** + * call once at startup + * @return + */ +void reset_mtime(void); + +/** + * Configure system tick + * @return SUCCESS or FAIL + */ +uint32_t SysTick_Config(void); + +/** + * Disable system tick interrupt + */ +void disable_systick(void); + +/*------------------------------------------------------------------------------ + * RISC-V interrupt handler for machine timer interrupts. + */ +void handle_m_timer_interrupt(void); + +/** + * + */ +void handle_m_soft_interrupt(void); + #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_h2f.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_h2f.c similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_h2f.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_h2f.c diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_h2f.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_h2f.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_h2f.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_h2f.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_hart_ints.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_hart_ints.h similarity index 56% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_hart_ints.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_hart_ints.h index f764087..5dc0553 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_hart_ints.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_hart_ints.h @@ -41,6 +41,12 @@ typedef struct BEU_Types_ volatile BEU_Type regs[5]; } BEU_Types; +#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL +#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL +#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL +#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL +#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL + #define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0) /* @@ -217,6 +223,153 @@ typedef struct BEU_Types_ #define H2_FABRIC_F2H_31_U54_INT 47 +void handle_m_ext_interrupt(void); +void Software_h0_IRQHandler(void); +void Software_h1_IRQHandler(void); +void Software_h2_IRQHandler(void); +void Software_h3_IRQHandler(void); +void Software_h4_IRQHandler(void); +void SysTick_Handler_h0_IRQHandler(void); +void SysTick_Handler_h1_IRQHandler(void); +void SysTick_Handler_h2_IRQHandler(void); +void SysTick_Handler_h3_IRQHandler(void); +void SysTick_Handler_h4_IRQHandler(void); + +/* + * + * Local interrupt defines + * + */ +void maintenance_e51_local_IRQHandler_0(void); +void usoc_smb_interrupt_e51_local_IRQHandler_1(void); +void usoc_vc_interrupt_e51_local_IRQHandler_2(void); +void g5c_message_e51_local_IRQHandler_3(void); +void g5c_devrst_e51_local_IRQHandler_4(void); +void wdog4_tout_e51_local_IRQHandler_5(void); +void wdog3_tout_e51_local_IRQHandler_6(void); +void wdog2_tout_e51_local_IRQHandler_7(void); +void wdog1_tout_e51_local_IRQHandler_8(void); +void wdog0_tout_e51_local_IRQHandler_9(void); +void wdog0_mvrp_e51_local_IRQHandler_10(void); +void mmuart0_e51_local_IRQHandler_11(void); +void envm_e51_local_IRQHandler_12(void); +void ecc_correct_e51_local_IRQHandler_13(void); +void ecc_error_e51_local_IRQHandler_14(void); +void scb_interrupt_e51_local_IRQHandler_15(void); +void fabric_f2h_32_e51_local_IRQHandler_16(void); +void fabric_f2h_33_e51_local_IRQHandler_17(void); +void fabric_f2h_34_e51_local_IRQHandler_18(void); +void fabric_f2h_35_e51_local_IRQHandler_19(void); +void fabric_f2h_36_e51_local_IRQHandler_20(void); +void fabric_f2h_37_e51_local_IRQHandler_21(void); +void fabric_f2h_38_e51_local_IRQHandler_22(void); +void fabric_f2h_39_e51_local_IRQHandler_23(void); +void fabric_f2h_40_e51_local_IRQHandler_24(void); +void fabric_f2h_41_e51_local_IRQHandler_25(void); +void fabric_f2h_42_e51_local_IRQHandler_26(void); +void fabric_f2h_43_e51_local_IRQHandler_27(void); +void fabric_f2h_44_e51_local_IRQHandler_28(void); +void fabric_f2h_45_e51_local_IRQHandler_29(void); +void fabric_f2h_46_e51_local_IRQHandler_30(void); +void fabric_f2h_47_e51_local_IRQHandler_31(void); +void fabric_f2h_48_e51_local_IRQHandler_32(void); +void fabric_f2h_49_e51_local_IRQHandler_33(void); +void fabric_f2h_50_e51_local_IRQHandler_34(void); +void fabric_f2h_51_e51_local_IRQHandler_35(void); +void fabric_f2h_52_e51_local_IRQHandler_36(void); +void fabric_f2h_53_e51_local_IRQHandler_37(void); +void fabric_f2h_54_e51_local_IRQHandler_38(void); +void fabric_f2h_55_e51_local_IRQHandler_39(void); +void fabric_f2h_56_e51_local_IRQHandler_40(void); +void fabric_f2h_57_e51_local_IRQHandler_41(void); +void fabric_f2h_58_e51_local_IRQHandler_42(void); +void fabric_f2h_59_e51_local_IRQHandler_43(void); +void fabric_f2h_60_e51_local_IRQHandler_44(void); +void fabric_f2h_61_e51_local_IRQHandler_45(void); +void fabric_f2h_62_e51_local_IRQHandler_46(void); +void fabric_f2h_63_e51_local_IRQHandler_47(void); + +/* + * U54 + */ +void spare_u54_local_IRQHandler_0(void); +void spare_u54_local_IRQHandler_1(void); +void spare_u54_local_IRQHandler_2(void); + +void mac_mmsl_u54_1_local_IRQHandler_3(void); +void mac_emac_u54_1_local_IRQHandler_4(void); +void mac_queue3_u54_1_local_IRQHandler_5(void); +void mac_queue2_u54_1_local_IRQHandler_6(void); +void mac_queue1_u54_1_local_IRQHandler_7(void); +void mac_int_u54_1_local_IRQHandler_8(void); + +void mac_mmsl_u54_2_local_IRQHandler_3(void); +void mac_emac_u54_2_local_IRQHandler_4(void); +void mac_queue3_u54_2_local_IRQHandler_5(void); +void mac_queue2_u54_2_local_IRQHandler_6(void); +void mac_queue1_u54_2_local_IRQHandler_7(void); +void mac_int_u54_2_local_IRQHandler_8(void); + +void mac_mmsl_u54_3_local_IRQHandler_3(void); +void mac_emac_u54_3_local_IRQHandler_4(void); +void mac_queue3_u54_3_local_IRQHandler_5(void); +void mac_queue2_u54_3_local_IRQHandler_6(void); +void mac_queue1_u54_3_local_IRQHandler_7(void); +void mac_int_u54_3_local_IRQHandler_8(void); + +void mac_mmsl_u54_4_local_IRQHandler_3(void); +void mac_emac_u54_4_local_IRQHandler_4(void); +void mac_queue3_u54_4_local_IRQHandler_5(void); +void mac_queue2_u54_4_local_IRQHandler_6(void); +void mac_queue1_u54_4_local_IRQHandler_7(void); +void mac_int_u54_4_local_IRQHandler_8(void); + +void wdog_tout_u54_h1_local_IRQHandler_9(void); +void wdog_tout_u54_h2_local_IRQHandler_9(void); +void wdog_tout_u54_h3_local_IRQHandler_9(void); +void wdog_tout_u54_h4_local_IRQHandler_9(void); +void mvrp_u54_local_IRQHandler_10(void); +void mmuart_u54_h1_local_IRQHandler_11(void); +void mmuart_u54_h2_local_IRQHandler_11(void); +void mmuart_u54_h3_local_IRQHandler_11(void); +void mmuart_u54_h4_local_IRQHandler_11(void); +void spare_u54_local_IRQHandler_12(void); +void spare_u54_local_IRQHandler_13(void); +void spare_u54_local_IRQHandler_14(void); +void spare_u54_local_IRQHandler_15(void); +void fabric_f2h_0_u54_local_IRQHandler_16(void); +void fabric_f2h_1_u54_local_IRQHandler_17(void); +void fabric_f2h_2_u54_local_IRQHandler_18(void); +void fabric_f2h_3_u54_local_IRQHandler_19(void); +void fabric_f2h_4_u54_local_IRQHandler_20(void); +void fabric_f2h_5_u54_local_IRQHandler_21(void); +void fabric_f2h_6_u54_local_IRQHandler_22(void); +void fabric_f2h_7_u54_local_IRQHandler_23(void); +void fabric_f2h_8_u54_local_IRQHandler_24(void); +void fabric_f2h_9_u54_local_IRQHandler_25(void); +void fabric_f2h_10_u54_local_IRQHandler_26(void); +void fabric_f2h_11_u54_local_IRQHandler_27(void); +void fabric_f2h_12_u54_local_IRQHandler_28(void); +void fabric_f2h_13_u54_local_IRQHandler_29(void); +void fabric_f2h_14_u54_local_IRQHandler_30(void); +void fabric_f2h_15_u54_local_IRQHandler_31(void); +void fabric_f2h_16_u54_local_IRQHandler_32(void); +void fabric_f2h_17_u54_local_IRQHandler_33(void); +void fabric_f2h_18_u54_local_IRQHandler_34(void); +void fabric_f2h_19_u54_local_IRQHandler_35(void); +void fabric_f2h_20_u54_local_IRQHandler_36(void); +void fabric_f2h_21_u54_local_IRQHandler_37(void); +void fabric_f2h_22_u54_local_IRQHandler_38(void); +void fabric_f2h_23_u54_local_IRQHandler_39(void); +void fabric_f2h_24_u54_local_IRQHandler_40(void); +void fabric_f2h_25_u54_local_IRQHandler_41(void); +void fabric_f2h_26_u54_local_IRQHandler_42(void); +void fabric_f2h_27_u54_local_IRQHandler_43(void); +void fabric_f2h_28_u54_local_IRQHandler_44(void); +void fabric_f2h_29_u54_local_IRQHandler_45(void); +void fabric_f2h_30_u54_local_IRQHandler_46(void); +void fabric_f2h_31_u54_local_IRQHandler_47(void); + #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_stubs.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_stubs.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c index 198796b..80d9321 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_stubs.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_irq_handler_stubs.c @@ -19,8 +19,8 @@ * same prototype in the user's application code. * */ +#include #include -#include "mss_hal.h" #ifdef __cplusplus extern "C" { diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_l2_cache.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_l2_cache.c similarity index 52% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_l2_cache.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_l2_cache.c index 67fed4e..165d9d2 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_l2_cache.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_l2_cache.c @@ -14,112 +14,20 @@ #include #include -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #include "mss_l2_cache.h" /*============================================================================== - * Define describing cache characteristics. + * Local defines */ -#define MAX_WAY_ENABLE 15 -#define NB_SETS 512 -#define NB_BANKS 4 -#define CACHE_BLOCK_BYTE_LENGTH 64 -#define UINT64_BYTE_LENGTH 8 -#define WAY_BYTE_LENGTH (CACHE_BLOCK_BYTE_LENGTH * NB_SETS * NB_BANKS) - -#define ZERO_DEVICE_BOTTOM 0x0A000000ULL -#define ZERO_DEVICE_TOP 0x0C000000ULL - -#define CACHE_CTRL_BASE 0x02010000ULL - -#define INIT_MARKER 0xC0FFEEBEC0010000ULL - +#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) static const uint64_t g_init_marker = INIT_MARKER; - -/*============================================================================== - * Cache controller registers definitions - */ -#define RO volatile const -#define RW volatile -#define WO volatile - -typedef struct { - RO uint8_t BANKS; - RO uint8_t WAYS; - RO uint8_t SETS; - RO uint8_t BYTES; -} CACHE_CONFIG_typedef; - -typedef struct { - CACHE_CONFIG_typedef CONFIG; - RO uint32_t RESERVED; - RW uint8_t WAY_ENABLE; - RO uint8_t RESERVED0[55]; - - WO uint32_t ECC_INJECT_ERROR; - RO uint32_t RESERVED1[47]; - - RO uint64_t ECC_DIR_FIX_ADDR; - RO uint32_t ECC_DIR_FIX_COUNT; - RO uint32_t RESERVED2[13]; - - RO uint64_t ECC_DATA_FIX_ADDR; - RO uint32_t ECC_DATA_FIX_COUNT; - RO uint32_t RESERVED3[5]; - - RO uint64_t ECC_DATA_FAIL_ADDR; - RO uint32_t ECC_DATA_FAIL_COUNT; - RO uint32_t RESERVED4[37]; - - WO uint64_t FLUSH64; - RO uint64_t RESERVED5[7]; - - WO uint32_t FLUSH32; - RO uint32_t RESERVED6[367]; - - RW uint64_t WAY_MASK_DMA; - - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_0; - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_1; - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_2; - RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_3; - - RW uint64_t WAY_MASK_E51_DCACHE; - RW uint64_t WAY_MASK_E51_ICACHE; - - RW uint64_t WAY_MASK_U54_1_DCACHE; - RW uint64_t WAY_MASK_U54_1_ICACHE; - - RW uint64_t WAY_MASK_U54_2_DCACHE; - RW uint64_t WAY_MASK_U54_2_ICACHE; - - RW uint64_t WAY_MASK_U54_3_DCACHE; - RW uint64_t WAY_MASK_U54_3_ICACHE; - - RW uint64_t WAY_MASK_U54_4_DCACHE; - RW uint64_t WAY_MASK_U54_4_ICACHE; -} CACHE_CTRL_typedef; - -#define CACHE_CTRL ((CACHE_CTRL_typedef *) CACHE_CTRL_BASE) - +#endif /*============================================================================== * Local functions. */ -static void config_l2_scratchpad(void); -static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start); - -/** - * \brief L2 waymask configuration settings from Libero - * - */ -const uint64_t way_mask_values[] = { - LIBERO_SETTING_WAY_MASK_M0, - LIBERO_SETTING_WAY_MASK_M1, - LIBERO_SETTING_WAY_MASK_M2, - LIBERO_SETTING_WAY_MASK_M3, - LIBERO_SETTING_WAY_MASK_M4 -}; +static void check_config_l2_scratchpad(void); /*============================================================================== @@ -128,16 +36,114 @@ const uint64_t way_mask_values[] = { * - Set the number of cache ways used as cache based on the MSS Configurator * settings. * - Configure some of the enabled ways as scratchpad based on linker - * configuration. + * configuration and space allocated by configurator. */ -void config_l2_cache(void) +__attribute__((weak)) void config_l2_cache(void) { + ASSERT(LIBERO_SETTING_WAY_ENABLE < 16U); + /* * Set the number of ways that will be shared between cache and scratchpad. */ CACHE_CTRL->WAY_ENABLE = LIBERO_SETTING_WAY_ENABLE; - config_l2_scratchpad(); + /* + * shutdown L2 as directed + */ + SYSREG->L2_SHUTDOWN_CR = LIBERO_SETTING_L2_SHUTDOWN_CR; + + /* The scratchpad has already been set-up, first check enough space before copying */ + check_config_l2_scratchpad(); + + /* If you are not using scratchpad, no need to include the following code */ + + ASSERT(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS); + + + + /* + * Compute the mask used to specify ways that will be used by the + * scratchpad. + */ + + uint32_t scratchpad_ways_mask = 0U; +#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) + uint32_t inc; + uint32_t seed_ways_mask = 0x1U << LIBERO_SETTING_WAY_ENABLE; + for(inc = 0; inc < LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS; ++inc) + { + scratchpad_ways_mask |= (seed_ways_mask >> inc) ; + } +#endif + + /* + * Make sure ways are masked if being used as scratchpad + */ + ASSERT((LIBERO_SETTING_WAY_MASK_DMA & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_E51_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_E51_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_1_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_2_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_3_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_4_DCACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_1_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_2_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_3_ICACHE & scratchpad_ways_mask) == 0UL); + ASSERT((LIBERO_SETTING_WAY_MASK_U54_4_ICACHE & scratchpad_ways_mask) == 0UL); + + /* + * Setup all masters, apart from one we are using to setup scratch + */ + CACHE_CTRL->WAY_MASK_DMA = LIBERO_SETTING_WAY_MASK_DMA; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_0; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_1; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_2; + CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_3; + CACHE_CTRL->WAY_MASK_E51_DCACHE = LIBERO_SETTING_WAY_MASK_E51_ICACHE; + CACHE_CTRL->WAY_MASK_U54_1_DCACHE = LIBERO_SETTING_WAY_MASK_U54_1_DCACHE; + CACHE_CTRL->WAY_MASK_U54_1_ICACHE = LIBERO_SETTING_WAY_MASK_U54_1_ICACHE; + CACHE_CTRL->WAY_MASK_U54_2_DCACHE = LIBERO_SETTING_WAY_MASK_U54_2_DCACHE; + CACHE_CTRL->WAY_MASK_U54_2_ICACHE = LIBERO_SETTING_WAY_MASK_U54_2_ICACHE; + CACHE_CTRL->WAY_MASK_U54_3_DCACHE = LIBERO_SETTING_WAY_MASK_U54_3_DCACHE; + CACHE_CTRL->WAY_MASK_U54_3_ICACHE = LIBERO_SETTING_WAY_MASK_U54_3_ICACHE; + CACHE_CTRL->WAY_MASK_U54_4_DCACHE = LIBERO_SETTING_WAY_MASK_U54_4_DCACHE; + CACHE_CTRL->WAY_MASK_U54_4_ICACHE = LIBERO_SETTING_WAY_MASK_U54_4_ICACHE; + +#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) + /* + * Assign ways to Zero Device + */ + uint64_t * p_scratchpad = (uint64_t *)ZERO_DEVICE_BOTTOM; + uint32_t ways_inc; + uint64_t current_way = 0x1U << (((LIBERO_SETTING_WAY_ENABLE + 1U) - LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS) ); + for(ways_inc = 0; ways_inc < LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS; ++ways_inc) + { + /* + * Populate the scratchpad memory one way at a time. + */ + CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way; + /* + * Write to the first 64-bit location of each cache block. + */ + for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc) + { + *p_scratchpad = g_init_marker + inc; + p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH; + } + current_way = current_way << 1U; + mb(); + } +#endif /* (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) */ + /* + * Prevent E51 from evicting from scratchpad ways. + */ + CACHE_CTRL->WAY_MASK_E51_DCACHE = LIBERO_SETTING_WAY_MASK_E51_DCACHE; + mb(); + } @@ -147,17 +153,22 @@ void config_l2_cache(void) * __l2_scratchpad_vma_end * * These linker symbols specify the start address and length of the scratchpad. - * The scratchpad must be located within the Sero Device memory range. + * The scratchpad must be located within the Zero Device memory range. */ -static void config_l2_scratchpad(void) +static void check_config_l2_scratchpad(void) { extern char __l2_scratchpad_vma_start; extern char __l2_scratchpad_vma_end; + uint8_t n_scratchpad_ways; const uint64_t end = (const uint64_t)&__l2_scratchpad_vma_end; const uint64_t start = (const uint64_t)&__l2_scratchpad_vma_start; uint64_t modulo; + ASSERT(start >= (uint64_t)ZERO_DEVICE_BOTTOM); + ASSERT(end < (uint64_t)ZERO_DEVICE_TOP); + ASSERT(end >= start); + /* * Figure out how many cache ways will be required from linker script * symbols. @@ -169,12 +180,12 @@ static void config_l2_scratchpad(void) ++n_scratchpad_ways; } - if(n_scratchpad_ways > 0) - { - reserve_scratchpad_ways(n_scratchpad_ways, (uint64_t *)start); - } + ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways); } +#if 0 // todo - remove, no longer used + + /*============================================================================== * Reserve a number of cache ways to be used as scratchpad memory. * @@ -192,7 +203,6 @@ static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) uint64_t scratchpad_ways = 0; uint64_t non_scratchpad_ways; uint32_t inc; - int ways_inc; ASSERT(scratchpad_start >= (uint64_t *)ZERO_DEVICE_BOTTOM); ASSERT(scratchpad_start < (uint64_t *)ZERO_DEVICE_TOP); @@ -249,7 +259,7 @@ static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) * Assign ways to Zero Device */ uint64_t * p_scratchpad = scratchpad_start; - + int ways_inc; uint64_t current_way = 1; for(ways_inc = 0; ways_inc < nways; ++ways_inc) { @@ -275,3 +285,4 @@ static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start) CACHE_CTRL->WAY_MASK_E51_DCACHE = non_scratchpad_ways; } } +#endif diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_l2_cache.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_l2_cache.h new file mode 100644 index 0000000..fce9015 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_l2_cache.h @@ -0,0 +1,532 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ + +/*************************************************************************** + * @file mss_l2_cache.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief MACROs defines and prototypes associated with L2 Cache + * + */ +#ifndef MSS_L2_CACHE_H +#define MSS_L2_CACHE_H + +#include +#include "encoding.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The following defines will be present in configurator generated xml Q1 2021 + * In the interim, you can manually edit if required. + */ +#if !defined (LIBERO_SETTING_WAY_ENABLE) +/*Way indexes less than or equal to this register value may be used by the +cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave +8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is +128KB. */ +#define LIBERO_SETTING_WAY_ENABLE 0x00000007UL + /* WAY_ENABLE [0:8] RW value= 0x7 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_DMA) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_DMA 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_0) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_1) +/*Way mask register master DMA. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_2) +/*Way mask registerAXI slave port 2. Set field to zero to disable way from this +master. The available cache ways are 0 to number set in WAY_ENABLE register. If +using scratch pad memory, the ways you want reserved for scrathpad are not +available for selection, you must set to 0. e.g. If three ways reserved for +scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all +masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_3) +/*Way mask register AXI slave port 3. Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_DCACHE) +/*Way mask register E51 data cache (hart0). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_E51_ICACHE) +/*Way mask registerE52 instruction cache (hart0). Set field to zero to disable +way from this master. The available cache ways are 0 to number set in +WAY_ENABLE register. If using scratch pad memory, the ways you want reserved +for scrathpad are not available for selection, you must set to 0. e.g. If three +ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set +to zero for all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_DCACHE) +/*Way mask register data cache (hart1). Set field to zero to disable way from +this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_ICACHE) +/*Way mask register instruction cache (hart1). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_DCACHE) +/*Way mask register data cache (hart2). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_ICACHE) +/*Way mask register instruction cache (hart2). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_DCACHE) +/*Way mask register data cache (hart3). Set field to 1 to disable way from this +master.Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_ICACHE) +/*Way mask register instruction cache(hart3). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_DCACHE) +/*Way mask register data cache (hart4). Set field to 1 to disable way from this +master. Set field to zero to disable way from this master. The available cache +ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, +the ways you want reserved for scrathpad are not available for selection, you +must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, +WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not +evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_ICACHE) +/*Way mask register instruction cache (hart4). Set field to zero to disable way +from this master. The available cache ways are 0 to number set in WAY_ENABLE +register. If using scratch pad memory, the ways you want reserved for scrathpad +are not available for selection, you must set to 0. e.g. If three ways reserved +for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for +all masters, so they can not evict the way. */ +#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000FFFFUL + /* WAY_MASK_0 [0:1] RW value= 0x1 */ + /* WAY_MASK_1 [1:1] RW value= 0x1 */ + /* WAY_MASK_2 [2:1] RW value= 0x1 */ + /* WAY_MASK_3 [3:1] RW value= 0x1 */ + /* WAY_MASK_4 [4:1] RW value= 0x1 */ + /* WAY_MASK_5 [5:1] RW value= 0x1 */ + /* WAY_MASK_6 [6:1] RW value= 0x1 */ + /* WAY_MASK_7 [7:1] RW value= 0x1 */ + /* WAY_MASK_8 [8:1] RW value= 0x1 */ + /* WAY_MASK_9 [9:1] RW value= 0x1 */ + /* WAY_MASK_10 [10:1] RW value= 0x1 */ + /* WAY_MASK_11 [11:1] RW value= 0x1 */ + /* WAY_MASK_12 [12:1] RW value= 0x1 */ + /* WAY_MASK_13 [13:1] RW value= 0x1 */ + /* WAY_MASK_14 [14:1] RW value= 0x1 */ + /* WAY_MASK_15 [15:1] RW value= 0x1 */ +#endif +#if !defined (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS) +/*Number of ways reserved for scratchpad. Note 1: This is not a register Note +2: each way is 128KB. Note 3: Embedded software expects cache ways allocated +for scratchpad start at way 0, and work up. */ +#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000000UL + /* NUM_OF_WAYS [0:8] RW value= 0x0 */ +#endif + + +#if !defined (LIBERO_SETTING_L2_SHUTDOWN_CR) +/*Number of ways reserved for scratchpad. Note 1: This is not a register Note +2: each way is 128KB. Note 3: Embedded software expects cache ways allocated +for scratchpad start at way 0, and work up. */ +#define LIBERO_SETTING_L2_SHUTDOWN_CR 0x00000000UL + /* NUM_OF_WAYS [0:8] RW value= 0x0 */ +#endif + + + +/*============================================================================== + * Define describing cache characteristics. + */ +#define MAX_WAY_ENABLE 15 +#define NB_SETS 512 +#define NB_BANKS 4 +#define CACHE_BLOCK_BYTE_LENGTH 64 +#define UINT64_BYTE_LENGTH 8 +#define WAY_BYTE_LENGTH (CACHE_BLOCK_BYTE_LENGTH * NB_SETS * NB_BANKS) + +#define ZERO_DEVICE_BOTTOM 0x0A000000ULL +#define ZERO_DEVICE_TOP 0x0C000000ULL + +#define CACHE_CTRL_BASE 0x02010000ULL + +#define INIT_MARKER 0xC0FFEEBEC0010000ULL + +#define SHUTDOWN_CACHE_CC24_00_07_MASK 0x01 +#define SHUTDOWN_CACHE_CC24_08_15_MASK 0x02 +#define SHUTDOWN_CACHE_CC24_16_23_MASK 0x04 +#define SHUTDOWN_CACHE_CC24_24_31_MASK 0x08 + + +/*============================================================================== + * Cache controller registers definitions + */ +#define RO volatile const +#define RW volatile +#define WO volatile + +typedef struct { + RO uint8_t BANKS; + RO uint8_t WAYS; + RO uint8_t SETS; + RO uint8_t BYTES; +} CACHE_CONFIG_typedef; + +typedef struct { + CACHE_CONFIG_typedef CONFIG; + RO uint32_t RESERVED; + RW uint8_t WAY_ENABLE; + RO uint8_t RESERVED0[55]; + + RW uint32_t ECC_INJECT_ERROR; + RO uint32_t RESERVED1[47]; + + RO uint64_t ECC_DIR_FIX_ADDR; + RO uint32_t ECC_DIR_FIX_COUNT; + RO uint32_t RESERVED2[13]; + + RO uint64_t ECC_DATA_FIX_ADDR; + RO uint32_t ECC_DATA_FIX_COUNT; + RO uint32_t RESERVED3[5]; + + RO uint64_t ECC_DATA_FAIL_ADDR; + RO uint32_t ECC_DATA_FAIL_COUNT; + RO uint32_t RESERVED4[37]; + + WO uint64_t FLUSH64; + RO uint64_t RESERVED5[7]; + + WO uint32_t FLUSH32; + RO uint32_t RESERVED6[367]; + + RW uint64_t WAY_MASK_DMA; + + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_0; + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_1; + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_2; + RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_3; + + RW uint64_t WAY_MASK_E51_DCACHE; + RW uint64_t WAY_MASK_E51_ICACHE; + + RW uint64_t WAY_MASK_U54_1_DCACHE; + RW uint64_t WAY_MASK_U54_1_ICACHE; + + RW uint64_t WAY_MASK_U54_2_DCACHE; + RW uint64_t WAY_MASK_U54_2_ICACHE; + + RW uint64_t WAY_MASK_U54_3_DCACHE; + RW uint64_t WAY_MASK_U54_3_ICACHE; + + RW uint64_t WAY_MASK_U54_4_DCACHE; + RW uint64_t WAY_MASK_U54_4_ICACHE; +} CACHE_CTRL_typedef; + +#define CACHE_CTRL ((volatile CACHE_CTRL_typedef *) CACHE_CTRL_BASE) + +void config_l2_cache(void); +uint8_t check_num_scratch_ways(uint64_t *start, uint64_t *end); + +#ifdef __cplusplus +} +#endif + +#endif /* MSS_L2_CACHE_H */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_mpu.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mpu.c similarity index 59% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_mpu.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mpu.c index 31491db..5f9c4c7 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_mpu.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mpu.c @@ -18,7 +18,7 @@ *//*=========================================================================*/ #include #include -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #ifndef SIFIVE_HIFIVE_UNLEASHED @@ -178,107 +178,6 @@ const uint64_t mpu_trace_values[] = { LIBERO_SETTING_TRACE_MPU_CFG_PMP1, }; -/** - * \brief PMP configuration from Libero - * - */ -const uint64_t pmp_values[][18] = { - /* hart 0 */ - {LIBERO_SETTING_HART0_CSR_PMPCFG0, - LIBERO_SETTING_HART0_CSR_PMPCFG2, - LIBERO_SETTING_HART0_CSR_PMPADDR0, - LIBERO_SETTING_HART0_CSR_PMPADDR1, - LIBERO_SETTING_HART0_CSR_PMPADDR2, - LIBERO_SETTING_HART0_CSR_PMPADDR3, - LIBERO_SETTING_HART0_CSR_PMPADDR4, - LIBERO_SETTING_HART0_CSR_PMPADDR5, - LIBERO_SETTING_HART0_CSR_PMPADDR6, - LIBERO_SETTING_HART0_CSR_PMPADDR7, - LIBERO_SETTING_HART0_CSR_PMPADDR8, - LIBERO_SETTING_HART0_CSR_PMPADDR9, - LIBERO_SETTING_HART0_CSR_PMPADDR10, - LIBERO_SETTING_HART0_CSR_PMPADDR11, - LIBERO_SETTING_HART0_CSR_PMPADDR12, - LIBERO_SETTING_HART0_CSR_PMPADDR13, - LIBERO_SETTING_HART0_CSR_PMPADDR14, - LIBERO_SETTING_HART0_CSR_PMPADDR15}, - /* hart 1 */ - {LIBERO_SETTING_HART1_CSR_PMPCFG0, - LIBERO_SETTING_HART1_CSR_PMPCFG2, - LIBERO_SETTING_HART1_CSR_PMPADDR0, - LIBERO_SETTING_HART1_CSR_PMPADDR1, - LIBERO_SETTING_HART1_CSR_PMPADDR2, - LIBERO_SETTING_HART1_CSR_PMPADDR3, - LIBERO_SETTING_HART1_CSR_PMPADDR4, - LIBERO_SETTING_HART1_CSR_PMPADDR5, - LIBERO_SETTING_HART1_CSR_PMPADDR6, - LIBERO_SETTING_HART1_CSR_PMPADDR7, - LIBERO_SETTING_HART1_CSR_PMPADDR8, - LIBERO_SETTING_HART1_CSR_PMPADDR9, - LIBERO_SETTING_HART1_CSR_PMPADDR10, - LIBERO_SETTING_HART1_CSR_PMPADDR11, - LIBERO_SETTING_HART1_CSR_PMPADDR12, - LIBERO_SETTING_HART1_CSR_PMPADDR13, - LIBERO_SETTING_HART1_CSR_PMPADDR14, - LIBERO_SETTING_HART1_CSR_PMPADDR15}, - /* hart 2 */ - {LIBERO_SETTING_HART2_CSR_PMPCFG0, - LIBERO_SETTING_HART2_CSR_PMPCFG2, - LIBERO_SETTING_HART2_CSR_PMPADDR0, - LIBERO_SETTING_HART2_CSR_PMPADDR1, - LIBERO_SETTING_HART2_CSR_PMPADDR2, - LIBERO_SETTING_HART2_CSR_PMPADDR3, - LIBERO_SETTING_HART2_CSR_PMPADDR4, - LIBERO_SETTING_HART2_CSR_PMPADDR5, - LIBERO_SETTING_HART2_CSR_PMPADDR6, - LIBERO_SETTING_HART2_CSR_PMPADDR7, - LIBERO_SETTING_HART2_CSR_PMPADDR8, - LIBERO_SETTING_HART2_CSR_PMPADDR9, - LIBERO_SETTING_HART2_CSR_PMPADDR10, - LIBERO_SETTING_HART2_CSR_PMPADDR11, - LIBERO_SETTING_HART2_CSR_PMPADDR12, - LIBERO_SETTING_HART2_CSR_PMPADDR13, - LIBERO_SETTING_HART2_CSR_PMPADDR14, - LIBERO_SETTING_HART2_CSR_PMPADDR15}, - /* hart 3 */ - {LIBERO_SETTING_HART3_CSR_PMPCFG0, - LIBERO_SETTING_HART3_CSR_PMPCFG2, - LIBERO_SETTING_HART3_CSR_PMPADDR0, - LIBERO_SETTING_HART3_CSR_PMPADDR1, - LIBERO_SETTING_HART3_CSR_PMPADDR2, - LIBERO_SETTING_HART3_CSR_PMPADDR3, - LIBERO_SETTING_HART3_CSR_PMPADDR4, - LIBERO_SETTING_HART3_CSR_PMPADDR5, - LIBERO_SETTING_HART3_CSR_PMPADDR6, - LIBERO_SETTING_HART3_CSR_PMPADDR7, - LIBERO_SETTING_HART3_CSR_PMPADDR8, - LIBERO_SETTING_HART3_CSR_PMPADDR9, - LIBERO_SETTING_HART3_CSR_PMPADDR10, - LIBERO_SETTING_HART3_CSR_PMPADDR11, - LIBERO_SETTING_HART3_CSR_PMPADDR12, - LIBERO_SETTING_HART3_CSR_PMPADDR13, - LIBERO_SETTING_HART3_CSR_PMPADDR14, - LIBERO_SETTING_HART3_CSR_PMPADDR15}, - /* hart 4 */ - {LIBERO_SETTING_HART4_CSR_PMPCFG0, - LIBERO_SETTING_HART4_CSR_PMPCFG2, - LIBERO_SETTING_HART4_CSR_PMPADDR0, - LIBERO_SETTING_HART4_CSR_PMPADDR1, - LIBERO_SETTING_HART4_CSR_PMPADDR2, - LIBERO_SETTING_HART4_CSR_PMPADDR3, - LIBERO_SETTING_HART4_CSR_PMPADDR4, - LIBERO_SETTING_HART4_CSR_PMPADDR5, - LIBERO_SETTING_HART4_CSR_PMPADDR6, - LIBERO_SETTING_HART4_CSR_PMPADDR7, - LIBERO_SETTING_HART4_CSR_PMPADDR8, - LIBERO_SETTING_HART4_CSR_PMPADDR9, - LIBERO_SETTING_HART4_CSR_PMPADDR10, - LIBERO_SETTING_HART4_CSR_PMPADDR11, - LIBERO_SETTING_HART4_CSR_PMPADDR12, - LIBERO_SETTING_HART4_CSR_PMPADDR13, - LIBERO_SETTING_HART4_CSR_PMPADDR14, - LIBERO_SETTING_HART4_CSR_PMPADDR15}, -}; /***************************************************************************//** * MSS_MPU_auto_configure() @@ -289,43 +188,43 @@ const uint64_t pmp_values[][18] = { */ uint8_t mpu_configure(void) { - config_copy((void *)(&(MSS_MPU(MSS_MPU_FIC0)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC0)->PMPCFG)), &(mpu_fic0_values), sizeof(mpu_fic0_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_FIC1)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC1)->PMPCFG)), &(mpu_fic1_values), sizeof(mpu_fic1_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_FIC2)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC2)->PMPCFG)), &(mpu_fic2_values), sizeof(mpu_fic2_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_CRYPTO)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_CRYPTO)->PMPCFG)), &(mpu_crypto_values), sizeof(mpu_crypto_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_GEM0)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_GEM0)->PMPCFG)), &(mpu_gem0_values), sizeof(mpu_gem0_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_GEM1)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_GEM1)->PMPCFG)), &(mpu_gem1_values), sizeof(mpu_gem1_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_USB)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_USB)->PMPCFG)), &(mpu_usb_values), sizeof(mpu_usb_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_MMC)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_MMC)->PMPCFG)), &(mpu_mmc_values), sizeof(mpu_mmc_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_SCB)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_SCB)->PMPCFG)), &(mpu_scb_values), sizeof(mpu_scb_values)); - config_copy((void *)(&(MSS_MPU(MSS_MPU_TRACE)->PMPCFG)), + config_64_copy((void *)(&(MSS_MPU(MSS_MPU_TRACE)->PMPCFG)), &(mpu_trace_values), sizeof(mpu_trace_values)); @@ -431,36 +330,6 @@ static uint64_t pmp_get_napot_base_and_range(uint64_t reg, uint64_t *range) #endif -/***************************************************************************//** - * MPU_auto_configure() - * Set MPU's up with configuration from Libero - * - * - * @return - */ -uint8_t pmp_configure(uint8_t hart_id) /* set-up with settings from Libero */ -{ - write_csr(pmpcfg0, pmp_values[hart_id][0]); - write_csr(pmpcfg2, pmp_values[hart_id][1]); - write_csr(pmpaddr0, pmp_values[hart_id][2]); - write_csr(pmpaddr0, pmp_values[hart_id][3]); - write_csr(pmpaddr0, pmp_values[hart_id][4]); - write_csr(pmpaddr0, pmp_values[hart_id][5]); - write_csr(pmpaddr0, pmp_values[hart_id][6]); - write_csr(pmpaddr0, pmp_values[hart_id][7]); - write_csr(pmpaddr0, pmp_values[hart_id][8]); - write_csr(pmpaddr0, pmp_values[hart_id][9]); - write_csr(pmpaddr0, pmp_values[hart_id][10]); - write_csr(pmpaddr0, pmp_values[hart_id][11]); - write_csr(pmpaddr0, pmp_values[hart_id][12]); - write_csr(pmpaddr0, pmp_values[hart_id][13]); - write_csr(pmpaddr0, pmp_values[hart_id][14]); - write_csr(pmpaddr0, pmp_values[hart_id][15]); - write_csr(pmpaddr0, pmp_values[hart_id][16]); - write_csr(pmpaddr0, pmp_values[hart_id][17]); - - return(0); -} #ifdef __cplusplus } diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_mpu.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mpu.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_mpu.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mpu.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mtrap.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mtrap.c similarity index 88% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mtrap.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mtrap.c index d0f5742..150a449 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mtrap.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mtrap.c @@ -9,18 +9,18 @@ /*************************************************************************** * - * @file mtrap.h + * @file mss_mtrap.h * @author Microchip-FPGA Embedded Systems Solutions * @brief trap functions * */ -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #ifdef __cplusplus extern "C" { #endif -static uint64_t g_systick_increment[5] = {0ULL,0ULL,0ULL,0ULL,0ULL}; + void handle_local_interrupt(uint8_t interrupt_no); void handle_m_soft_interrupt(void); @@ -31,7 +31,6 @@ void misaligned_load_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc); void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc); void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc); void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc); -void reset_mtime(void); void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc) @@ -724,164 +723,29 @@ void handle_local_interrupt(uint8_t interrupt_no) #endif } - -/** - * call once at startup - * @return - */ -void reset_mtime(void) -{ -#if ROLLOVER_TEST - CLINT->MTIME = 0xFFFFFFFFFFFFF000ULL; -#else - CLINT->MTIME = 0ULL; -#endif -} - -/** - * Configure system tick - * @return SUCCESS or FAIL - */ -uint32_t SysTick_Config(void) -{ - const uint32_t tick_rate[5] = {HART0_TICK_RATE_MS, HART1_TICK_RATE_MS ,HART2_TICK_RATE_MS ,HART3_TICK_RATE_MS ,HART4_TICK_RATE_MS}; - volatile uint32_t ret_val = ERROR; - - uint64_t mhart_id = read_csr(mhartid); - - /* - * We are assuming the tick rate is in milli-seconds - * - * convert RTC frequency into milliseconds and multiple by the tick rate - * - */ - - g_systick_increment[mhart_id] = ((LIBERO_SETTING_MSS_RTC_TOGGLE_CLK/1000U) * tick_rate[mhart_id]); - - if (g_systick_increment[mhart_id] > 0ULL) - { - - CLINT->MTIMECMP[mhart_id] = CLINT->MTIME + g_systick_increment[mhart_id]; - - set_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ - - __enable_irq(); - - ret_val = SUCCESS; - } - - return (ret_val); -} - -/** - * Disable system tick interrupt - */ -void disable_systick(void) -{ - clear_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */ - return; -} - - /*------------------------------------------------------------------------------ - * RISC-V interrupt handler for machine timer interrupts. - */ -void handle_m_timer_interrupt(void) -{ - - volatile uint64_t hart_id = read_csr(mhartid); - volatile uint32_t error_loop; - clear_csr(mie, MIP_MTIP); - - switch(hart_id) - { - case 0U: - SysTick_Handler_h0_IRQHandler(); - break; - case 1U: - SysTick_Handler_h1_IRQHandler(); - break; - case 2U: - SysTick_Handler_h2_IRQHandler(); - break; - case 3U: - SysTick_Handler_h3_IRQHandler(); - break; - case 4U: - SysTick_Handler_h4_IRQHandler(); - break; - default: - while (hart_id != 0U) - { - error_loop++; - } - break; - } - - CLINT->MTIMECMP[read_csr(mhartid)] = CLINT->MTIME + g_systick_increment[hart_id]; - - set_csr(mie, MIP_MTIP); - -} - - -/** * */ -void handle_m_soft_interrupt(void) -{ - volatile uint64_t hart_id = read_csr(mhartid); - volatile uint32_t error_loop; - - switch(hart_id) - { - case 0U: - Software_h0_IRQHandler(); - break; - case 1U: - Software_h1_IRQHandler(); - break; - case 2U: - Software_h2_IRQHandler(); - break; - case 3U: - Software_h3_IRQHandler(); - break; - case 4U: - Software_h4_IRQHandler(); - break; - default: - while (hart_id != 0U) - { - error_loop++; - } - break; - } - - /*Clear software interrupt*/ - clear_soft_interrupt(); -} - void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc) { uintptr_t mcause = read_csr(mcause); - if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) - { - handle_m_ext_interrupt(); - } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U)) + if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U)) { handle_local_interrupt((uint8_t)(mcause & MCAUSE_CAUSE)); } - else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { - handle_m_timer_interrupt(); + handle_m_ext_interrupt(); } else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)) { handle_m_soft_interrupt(); } + else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) + { + handle_m_timer_interrupt(); + } else { uint32_t i; diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mtrap.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mtrap.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mtrap.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_mtrap.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_l2_cache.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_plic.c similarity index 61% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_l2_cache.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_plic.c index 8e78a57..bd747a8 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_l2_cache.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_plic.c @@ -7,26 +7,23 @@ * */ -/*************************************************************************** - * @file mss_l2_cache.h +/******************************************************************************* + * + * @file mss_plic.c * @author Microchip-FPGA Embedded Systems Solutions - * @brief MACROs defines and prototypes associated with L2 Cache + * @brief MPFS PLIC and PRCI access data structures and functions. + * + * PLIC related data which cannot be placed in mss_plic.h * */ -#ifndef MSS_L2_CACHE_H -#define MSS_L2_CACHE_H - -#include -#include "encoding.h" +#include "mpfs_hal/mss_hal.h" #ifdef __cplusplus extern "C" { #endif -void config_l2_cache(void); +const unsigned long plic_hart_lookup[5U] = {0U, 1U, 3U, 5U, 7U}; #ifdef __cplusplus } #endif - -#endif /* MSS_L2_CACHE_H */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_plic.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_plic.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_plic.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_plic.h index 99c0373..f60f564 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_plic.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_plic.h @@ -694,6 +694,8 @@ typedef struct #define TARGET_OFFSET_HART4_M 7U #define TARGET_OFFSET_HART4_S 8U +extern const unsigned long plic_hart_lookup[5U]; + /***************************************************************************//** * PLIC: Platform Level Interrupt Controller */ @@ -917,9 +919,7 @@ static inline uint32_t PLIC_ClaimIRQ(void) { uint64_t hart_id = read_csr(mhartid); - const unsigned long lookup[5U] = {0U, 1U, 3U, 5U, 7U}; - - return (PLIC->TARGET[lookup[hart_id]].CLAIM_COMPLETE); + return (PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE); } /***************************************************************************//** @@ -930,11 +930,9 @@ static inline void PLIC_CompleteIRQ(uint32_t source) { uint64_t hart_id = read_csr(mhartid); - const unsigned long lookup[5U] = {0U, 1U, 3U, 5U, 7U}; - ASSERT(source <= MAX_PLIC_INT); - PLIC->TARGET[lookup[hart_id]].CLAIM_COMPLETE = source; + PLIC->TARGET[plic_hart_lookup[hart_id]].CLAIM_COMPLETE = source; } /***************************************************************************//** @@ -952,11 +950,10 @@ static inline void PLIC_CompleteIRQ(uint32_t source) static inline void PLIC_SetPriority_Threshold(uint32_t threshold) { uint64_t hart_id = read_csr(mhartid); - const unsigned long lookup[5U] = {0U, 1U, 3U, 5U, 7U}; ASSERT(threshold <= 7); - PLIC->TARGET[lookup[hart_id]].PRIORITY_THRESHOLD = threshold; + PLIC->TARGET[plic_hart_lookup[hart_id]].PRIORITY_THRESHOLD = threshold; } /***************************************************************************//** diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_pmp.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_pmp.c new file mode 100644 index 0000000..e778f25 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_pmp.c @@ -0,0 +1,159 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * + */ +/******************************************************************************* + * @file mss_mpu.c + * @author Microchip-FPGA Embedded Systems Solutions + * @brief PolarFire SoC MSS MPU driver for configuring access regions for the + * external masters. + * + */ +/*=========================================================================*//** + + *//*=========================================================================*/ +#include +#include +#include "mpfs_hal/mss_hal.h" + +/** + * \brief PMP configuration from Libero + * + */ +const uint64_t pmp_values[][18] = { + /* hart 0 */ + {LIBERO_SETTING_HART0_CSR_PMPCFG0, + LIBERO_SETTING_HART0_CSR_PMPCFG2, + LIBERO_SETTING_HART0_CSR_PMPADDR0, + LIBERO_SETTING_HART0_CSR_PMPADDR1, + LIBERO_SETTING_HART0_CSR_PMPADDR2, + LIBERO_SETTING_HART0_CSR_PMPADDR3, + LIBERO_SETTING_HART0_CSR_PMPADDR4, + LIBERO_SETTING_HART0_CSR_PMPADDR5, + LIBERO_SETTING_HART0_CSR_PMPADDR6, + LIBERO_SETTING_HART0_CSR_PMPADDR7, + LIBERO_SETTING_HART0_CSR_PMPADDR8, + LIBERO_SETTING_HART0_CSR_PMPADDR9, + LIBERO_SETTING_HART0_CSR_PMPADDR10, + LIBERO_SETTING_HART0_CSR_PMPADDR11, + LIBERO_SETTING_HART0_CSR_PMPADDR12, + LIBERO_SETTING_HART0_CSR_PMPADDR13, + LIBERO_SETTING_HART0_CSR_PMPADDR14, + LIBERO_SETTING_HART0_CSR_PMPADDR15}, + /* hart 1 */ + {LIBERO_SETTING_HART1_CSR_PMPCFG0, + LIBERO_SETTING_HART1_CSR_PMPCFG2, + LIBERO_SETTING_HART1_CSR_PMPADDR0, + LIBERO_SETTING_HART1_CSR_PMPADDR1, + LIBERO_SETTING_HART1_CSR_PMPADDR2, + LIBERO_SETTING_HART1_CSR_PMPADDR3, + LIBERO_SETTING_HART1_CSR_PMPADDR4, + LIBERO_SETTING_HART1_CSR_PMPADDR5, + LIBERO_SETTING_HART1_CSR_PMPADDR6, + LIBERO_SETTING_HART1_CSR_PMPADDR7, + LIBERO_SETTING_HART1_CSR_PMPADDR8, + LIBERO_SETTING_HART1_CSR_PMPADDR9, + LIBERO_SETTING_HART1_CSR_PMPADDR10, + LIBERO_SETTING_HART1_CSR_PMPADDR11, + LIBERO_SETTING_HART1_CSR_PMPADDR12, + LIBERO_SETTING_HART1_CSR_PMPADDR13, + LIBERO_SETTING_HART1_CSR_PMPADDR14, + LIBERO_SETTING_HART1_CSR_PMPADDR15}, + /* hart 2 */ + {LIBERO_SETTING_HART2_CSR_PMPCFG0, + LIBERO_SETTING_HART2_CSR_PMPCFG2, + LIBERO_SETTING_HART2_CSR_PMPADDR0, + LIBERO_SETTING_HART2_CSR_PMPADDR1, + LIBERO_SETTING_HART2_CSR_PMPADDR2, + LIBERO_SETTING_HART2_CSR_PMPADDR3, + LIBERO_SETTING_HART2_CSR_PMPADDR4, + LIBERO_SETTING_HART2_CSR_PMPADDR5, + LIBERO_SETTING_HART2_CSR_PMPADDR6, + LIBERO_SETTING_HART2_CSR_PMPADDR7, + LIBERO_SETTING_HART2_CSR_PMPADDR8, + LIBERO_SETTING_HART2_CSR_PMPADDR9, + LIBERO_SETTING_HART2_CSR_PMPADDR10, + LIBERO_SETTING_HART2_CSR_PMPADDR11, + LIBERO_SETTING_HART2_CSR_PMPADDR12, + LIBERO_SETTING_HART2_CSR_PMPADDR13, + LIBERO_SETTING_HART2_CSR_PMPADDR14, + LIBERO_SETTING_HART2_CSR_PMPADDR15}, + /* hart 3 */ + {LIBERO_SETTING_HART3_CSR_PMPCFG0, + LIBERO_SETTING_HART3_CSR_PMPCFG2, + LIBERO_SETTING_HART3_CSR_PMPADDR0, + LIBERO_SETTING_HART3_CSR_PMPADDR1, + LIBERO_SETTING_HART3_CSR_PMPADDR2, + LIBERO_SETTING_HART3_CSR_PMPADDR3, + LIBERO_SETTING_HART3_CSR_PMPADDR4, + LIBERO_SETTING_HART3_CSR_PMPADDR5, + LIBERO_SETTING_HART3_CSR_PMPADDR6, + LIBERO_SETTING_HART3_CSR_PMPADDR7, + LIBERO_SETTING_HART3_CSR_PMPADDR8, + LIBERO_SETTING_HART3_CSR_PMPADDR9, + LIBERO_SETTING_HART3_CSR_PMPADDR10, + LIBERO_SETTING_HART3_CSR_PMPADDR11, + LIBERO_SETTING_HART3_CSR_PMPADDR12, + LIBERO_SETTING_HART3_CSR_PMPADDR13, + LIBERO_SETTING_HART3_CSR_PMPADDR14, + LIBERO_SETTING_HART3_CSR_PMPADDR15}, + /* hart 4 */ + {LIBERO_SETTING_HART4_CSR_PMPCFG0, + LIBERO_SETTING_HART4_CSR_PMPCFG2, + LIBERO_SETTING_HART4_CSR_PMPADDR0, + LIBERO_SETTING_HART4_CSR_PMPADDR1, + LIBERO_SETTING_HART4_CSR_PMPADDR2, + LIBERO_SETTING_HART4_CSR_PMPADDR3, + LIBERO_SETTING_HART4_CSR_PMPADDR4, + LIBERO_SETTING_HART4_CSR_PMPADDR5, + LIBERO_SETTING_HART4_CSR_PMPADDR6, + LIBERO_SETTING_HART4_CSR_PMPADDR7, + LIBERO_SETTING_HART4_CSR_PMPADDR8, + LIBERO_SETTING_HART4_CSR_PMPADDR9, + LIBERO_SETTING_HART4_CSR_PMPADDR10, + LIBERO_SETTING_HART4_CSR_PMPADDR11, + LIBERO_SETTING_HART4_CSR_PMPADDR12, + LIBERO_SETTING_HART4_CSR_PMPADDR13, + LIBERO_SETTING_HART4_CSR_PMPADDR14, + LIBERO_SETTING_HART4_CSR_PMPADDR15}, +}; + +/***************************************************************************//** + * MPU_auto_configure() + * Set MPU's up with configuration from Libero + * + * + * @return + */ +uint8_t pmp_configure(uint8_t hart_id) /* set-up with settings from Libero */ +{ + /* make sure enables are off */ + write_csr(pmpcfg0, 0); + write_csr(pmpcfg2, 0); + /* set required addressing */ + write_csr(pmpaddr0, pmp_values[hart_id][2]); + write_csr(pmpaddr1, pmp_values[hart_id][3]); + write_csr(pmpaddr2, pmp_values[hart_id][4]); + write_csr(pmpaddr3, pmp_values[hart_id][5]); + write_csr(pmpaddr4, pmp_values[hart_id][6]); + write_csr(pmpaddr5, pmp_values[hart_id][7]); + write_csr(pmpaddr6, pmp_values[hart_id][8]); + write_csr(pmpaddr7, pmp_values[hart_id][9]); + write_csr(pmpaddr8, pmp_values[hart_id][10]); + write_csr(pmpaddr9, pmp_values[hart_id][11]); + write_csr(pmpaddr10, pmp_values[hart_id][12]); + write_csr(pmpaddr11, pmp_values[hart_id][13]); + write_csr(pmpaddr12, pmp_values[hart_id][14]); + write_csr(pmpaddr13, pmp_values[hart_id][15]); + write_csr(pmpaddr14, pmp_values[hart_id][16]); + write_csr(pmpaddr15, pmp_values[hart_id][17]); + /* now set the enables */ + write_csr(pmpcfg0, pmp_values[hart_id][0]); + write_csr(pmpcfg2, pmp_values[hart_id][1]); + + return(0); +} diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_prci.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_pmp.h similarity index 50% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_prci.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_pmp.h index f723493..9e085f5 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_prci.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_pmp.h @@ -1,4 +1,4 @@ - /******************************************************************************* +/******************************************************************************* * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. * * SPDX-License-Identifier: MIT @@ -6,30 +6,30 @@ * MPFS HAL Embedded Software * */ - /******************************************************************************* - * @file mss_prci.h + * @file mss_mpu.h * @author Microchip-FPGA Embedded Systems Solutions - * @brief PRCI: Power, Reset, Clock, Interrupt + * @brief PolarFire SoC MSS MPU driver APIS for configuring access regions for + * the external masters. * */ +/*=========================================================================*//** + + *//*=========================================================================*/ +#ifndef MSS_MPU_H +#define MSS_MPU_H -#ifndef MSS_PRCI_H -#define MSS_PRCI_H #ifdef __cplusplus extern "C" { #endif -/*============================================================================== - * PRCI: Power, Reset, Clock, Interrupt - */ -#define PRCI_BASE 0x10000000UL /* FU540-C000 on unleashed board- 0x10000000UL */ +uint8_t pmp_configure(uint8_t hart_id); #ifdef __cplusplus } #endif -#endif /* MSS_PRCI_H */ +#endif /* MSS_MPU_H */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_seg.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_seg.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_seg.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_seg.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_sysreg.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_sysreg.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_sysreg.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_sysreg.h index e37b6be..3ef4247 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_sysreg.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_sysreg.h @@ -64,8 +64,6 @@ extern "C" { cture member permissions */ #endif -#include "mss_peripheral_base_add.h" - /* Defines all Top Register offsets*/ /* Date of Source Revision File: 12-Jul-18*/ /* PROTOCOL=MSS; BASE=32'h20012000*/ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_util.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_util.c similarity index 83% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_util.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_util.c index afe40e4..f1e2ea2 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/mss_util.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_util.c @@ -15,7 +15,7 @@ */ #include #include -#include "mss_hal.h" +#include "mpfs_hal/mss_hal.h" #ifdef __cplusplus extern "C" { @@ -91,46 +91,6 @@ void __disable_local_irq(uint8_t local_interrupt) } } -/* - * Functions - */ -uint64_t readmtime(void) -{ - volatile uint64_t hartid = read_csr(mhartid); - volatile uint64_t * mtime_hart = NULL; - uint64_t mtime = 0ULL; - - switch(hartid) { - case 0: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H0; - break; - - case 1: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H1; - break; - - case 2: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H2; - break; - - case 3: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H3; - break; - - case 4: - mtime_hart = (volatile uint64_t *)U5CP_MTIME_H4; - break; - - default: - return (0ULL); - break; - } - - mtime = *mtime_hart; - return (mtime); -} - - uint64_t readmcycle(void) { return (read_csr(mcycle)); diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_util.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_util.h similarity index 96% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_util.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_util.h index 3f052cb..ea20c2a 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_util.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/mss_util.h @@ -24,8 +24,6 @@ extern "C" { #endif -#define DDR_BASE (0x80000000ul) - /* * Useful macros */ @@ -38,8 +36,10 @@ extern "C" { #define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y)) #define READ_REG64(x) (*((volatile uint64_t *)(x))) +/* + * return mcycle + */ uint64_t readmcycle(void); -uint64_t readmtime(void); void sleep_ms(uint64_t msecs); void sleep_cycles(uint64_t ncycles); diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_cfm.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_cfm.c similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_cfm.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_cfm.c index 61e6633..e81f08d 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_cfm.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_cfm.c @@ -11,8 +11,7 @@ #include #include -#include "../../mpfs_hal/mss_hal.h" - +#include "mpfs_hal/mss_hal.h" #include "mss_cfm.h" diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_cfm.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_cfm.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_cfm.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_cfm.h diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr.c similarity index 97% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr.c index f3277bd..8063bf8 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr.c @@ -13,10 +13,10 @@ * @brief DDR related code * */ -#include "mpfs_hal/mss_hal.h" -#ifdef DDR_SUPPORT #include #include +#include "mpfs_hal/mss_hal.h" +#ifdef DDR_SUPPORT #include "mss_ddr_debug.h" #include "simulation.h" @@ -24,8 +24,16 @@ * Local Defines */ /* This string is updated if any change to ddr driver */ -#define DDR_DRIVER_VERSION_STRING "0.0.013" +#define DDR_DRIVER_VERSION_STRING "0.1.004" /* Version | Change */ +/* 0.1.004 | Corrected default RPC220 setting so dq/dqs window centred */ +/* 0.1.003 | refclk_phase correctly masked during bclk sclk sw training */ +/* 0.1.002 | Reset modified- corrects softreset on retry issue (1.8.x) */ +/* 0.1.001 | Reset modified- corrects softreset on retry issue (1.7.2) */ +/* 0.0.016 | Added #define DDR_FULL_32BIT_NC_CHECK_EN to mss_ddr.h */ +/* 0.0.016 | updated mss_ddr_debug.c with additio of 32-bit write test */ +/* 0.0.015 | DDR3L - Use Software Bclk Sclk training */ +/* 0.0.014 | DDR3 and DDR update to sync with SVG proven golden version */ /* 0.0.013 | Added code to turn off DM if DDR4 and using ECC */ /* 0.0.012 | Added support for turning off unused I/O from Libero */ @@ -107,12 +115,7 @@ static uint8_t get_best_sweep(sweep_index *good_index); * External function declarations */ extern void delay(uint32_t n); -#ifdef DDR_FULL_32BIT_NC_CHECK_EN -#ifndef HSS -extern uint32_t ddr_read_write_fn (uint64_t* DDR_word_ptr, uint32_t no_access,\ - uint32_t pattern); -#endif -#endif + #ifdef DEBUG_DDR_INIT extern mss_uart_instance_t *g_debug_uart; #ifdef DEBUG_DDR_DDRCFG @@ -220,7 +223,8 @@ static uint32_t ddr_setup(void) #endif ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + //config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); // config_copy((uint8_t *)&sweep_results[0U][0U][0U][0U][0U],0U, sizeof(sweep_results)); retry_count = 0U; #ifdef DEBUG_DDR_INIT @@ -415,7 +419,7 @@ static uint32_t ddr_setup(void) } ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x0U; /* reset controller */ DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; @@ -424,7 +428,7 @@ static uint32_t ddr_setup(void) #else /* we are not SWEEP_ENABLED */ ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x0U; /* reset controller */ DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; @@ -499,7 +503,7 @@ static uint32_t ddr_setup(void) */ ddr_error_count = 0U; error = 0U; - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); DDRCFG->DFI.PHY_DFI_INIT_START.PHY_DFI_INIT_START = 0x00000000U; /* reset controller */ DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x00000000U; @@ -758,26 +762,31 @@ static uint32_t ddr_setup(void) /* To verify if separate reset required for DDR4 - believe it is not */ #ifndef SPECIAL_TRAINIG_RESET CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; - +#ifndef SOFT_RESET_PRE_TAG_172 + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ + 0x00000000U; + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ + 0x00000001U; +#endif /* !SOFT_RESET_PRE_TAG_172 */ #else - /* Disable CKE */ - DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; - - /* Assert FORCE_RESET */ - DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; - delay(100); - /* release reset to memory here, set INIT_FORCE_RESET to 0 */ - DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; - delay(500000); - - /* Enable CKE */ - DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; - delay(1000); - + /* Disable CKE */ + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; + + /* Assert FORCE_RESET */ + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; + delay(100); + /* release reset to memory here, set INIT_FORCE_RESET to 0 */ + DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; + delay(500000); + + /* Enable CKE */ + DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; + delay(1000); + /* reset pin is bit [1] */ CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; -#endif +#endif ddr_training_state = DDR_TRAINING_ROTATE_CLK; break; case DDR_TRAINING_ROTATE_CLK: @@ -893,8 +902,10 @@ static uint32_t ddr_setup(void) /* * Initiate software training */ +#ifdef SOFT_RESET_PRE_TAG_172 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ 0x00000001U; +#endif ddr_training_state = DDR_TRAINING_IP_SM_BCLKSCLK_SW; } else @@ -903,10 +914,16 @@ static uint32_t ddr_setup(void) * Initiate IP training and wait for dfi_init_complete */ /*asserting training_reset */ - - CFG_DDR_SGMII_PHY->training_reset.training_reset =\ + if (ddr_type != DDR3) + { + CFG_DDR_SGMII_PHY->training_reset.training_reset =\ 0x00000000U; - + } + else + { + DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ + 0x00000001U; + } ddr_training_state = DDR_TRAINING_IP_SM_START; } } @@ -982,7 +999,7 @@ static uint32_t ddr_setup(void) * refclk phase offset manually * We may need to sweep this */ - refclk_phase = (uint32_t)((answer+SW_TRAING_BCLK_SCLK_OFFSET + 5U + LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET ) << 2U); + refclk_phase = (uint32_t)(((answer+SW_TRAING_BCLK_SCLK_OFFSET + 5U + LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET ) & 0x07UL) << 2U); bclk_phase = ((answer+SW_TRAING_BCLK_SCLK_OFFSET) & 0x07UL ) << 8U; bclk90_phase= ((answer+SW_TRAING_BCLK_SCLK_OFFSET+2U) & 0x07UL ) << 11U; MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); @@ -1016,9 +1033,9 @@ static uint32_t ddr_setup(void) CFG_DDR_SGMII_PHY->rpc168.rpc168 = 0x0U; } #ifdef DDR_TRAINING_IP_SM_START_DELAY - delay(100); + delay(100); #endif - /* release reset to training */ + /* release reset to training */ CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000000U; #ifdef IP_SM_START_TRAINING_PAUSE /* todo: pause removed at Alister's request for test. Will @@ -1102,6 +1119,7 @@ static uint32_t ddr_setup(void) } else if(CFG_DDR_SGMII_PHY->training_status.training_status & ADDCMD_BIT) { + timeout = 0xFFFFF; ddr_training_state = DDR_TRAINING_IP_SM_WRLVL; } if(--timeout == 0U) @@ -1130,6 +1148,7 @@ static uint32_t ddr_setup(void) } else if(CFG_DDR_SGMII_PHY->training_status.training_status & WRLVL_BIT) { + timeout = 0xFFFFF; ddr_training_state = DDR_TRAINING_IP_SM_RDGATE; } if(--timeout == 0U) @@ -1245,7 +1264,7 @@ static uint32_t ddr_setup(void) } /* Check that DQ/DQS calculated window is above 5 taps. */ if(CFG_DDR_SGMII_PHY->dqdqs_status1.dqdqs_status1 < \ - DQ_DQS_NUM_TAPS) + DQ_DQS_NUM_TAPS) { t_status = t_status | 0x01U; } @@ -1260,16 +1279,16 @@ static uint32_t ddr_setup(void) /* * We can now set vref on the memory * mode register for lpddr4 - * May include other modes, and include a sweep - * Alister looking into this and will revert. + * May include other modes, and include a sweep + * Alister looking into this and will revert. */ if (ddr_type == LPDDR4) - { + { #ifdef SET_VREF_LPDDR4_MODE_REGS - mode_register_write(DDR_MODE_REG_VREF,\ + mode_register_write(DDR_MODE_REG_VREF,\ DDR_MODE_REG_VREF_VALUE); #endif - } + } ddr_training_state = DDR_TRAINING_SET_FINAL_MODE; } else /* fail, try again */ @@ -1328,6 +1347,8 @@ static uint32_t ddr_setup(void) if (ddr_type == LPDDR4) { uint8_t lane; + /* Changed default value to centre dq/dqs on window */ + CFG_DDR_SGMII_PHY->rpc220.rpc220 = 0xCUL; for(lane = 0U; lane < number_of_lanes_to_calibrate; lane++) { load_dq(lane); @@ -1339,11 +1360,11 @@ static uint32_t ddr_setup(void) write_calibration_lpddr4_using_mtc(\ number_of_lanes_to_calibrate); #else - error =\ + error =\ write_calibration_using_mtc(\ number_of_lanes_to_calibrate); -#endif - } +#endif + } else { SIM_FEEDBACK1(2U); @@ -1379,7 +1400,7 @@ static uint32_t ddr_setup(void) /* * Clear write calibration data */ - config_copy((uint8_t *)&calib_data,0U,sizeof(calib_data)); + memfill((uint8_t *)&calib_data,0U,sizeof(calib_data)); /* * Try the next offset */ @@ -1416,9 +1437,9 @@ static uint32_t ddr_setup(void) case DDR_SANITY_CHECKS: //setup_ddr_segments(); //todo: create state here, as no need to do further up - // Also, sw should set with default values here to allow full memory range check - // on non cached and cached as we are doing now - // and set to Libero values once DDR write/read verified + // Also, sw should set with default values here to allow full memory range check + // on non cached and cached as we are doing now + // and set to Libero values once DDR write/read verified /* * Now start the write calibration if training successful */ @@ -1458,11 +1479,11 @@ static uint32_t ddr_setup(void) * write and read back test from drr, non cached access */ { -#ifdef DDR_FULL_32BIT_NC_CHECK_EN +#if (DDR_FULL_32BIT_NC_CHECK_EN == 1) #ifndef HSS - error = ddr_read_write_fn((uint64_t*)MSS_BASE_ADD_DRC_NC,\ + error = ddr_read_write_fn((uint64_t*)LIBERO_SETTING_DDR_64_NON_CACHE,\ SW_CFG_NUM_READS_WRITES,\ - SW_CONFIG_PATTERN); + SW_CONFIG_PATTERN); #else bool HSS_MemTestDDRFast(void); #endif @@ -1572,7 +1593,7 @@ static uint32_t ddr_setup(void) */ #ifdef DEBUG_DDR_INIT { - tip_register_status (g_debug_uart); + tip_register_status (g_debug_uart); (void)uprint32(g_debug_uart, "\n\r\n\r DDR_TRAINING_PASS: ",\ ddr_training_state); (void)uprint32(g_debug_uart, "\n ****************************************************", 0); @@ -1873,18 +1894,18 @@ static void set_ddr_rpc_regs(DDR_TYPE ddr_type) /* * If this define is not present, indicates older * Libero core (pre 2.0.109) - * So we run this code + * So we run this code */ CFG_DDR_SGMII_PHY->ovrt10.ovrt10 =\ LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10; - { - /* Use pull-ups to set the CMD/ADD ODT */ + { + /* Use pull-ups to set the CMD/ADD ODT */ CFG_DDR_SGMII_PHY->rpc245.rpc245 =\ - 0x00000000; + 0x00000000; CFG_DDR_SGMII_PHY->rpc237.rpc237 =\ - 0xffffffff; - } + 0xffffffff; + } /* OVRT_EN_ADDCMD2 (default 0xE06), register named ovrt12 */ CFG_DDR_SGMII_PHY->ovrt11.ovrt11 =\ @@ -2810,15 +2831,15 @@ static uint8_t \ for (laneToTest = 0x00U; laneToTest #include #include #include "mpfs_hal/mss_hal.h" -#include "mss_ddr_debug.h" /******************************************************************************* * Local Defines @@ -36,6 +36,9 @@ extern uint8_t sweep_results[MAX_NUMBER_DPC_VS_GEN_SWEEPS]\ [MAX_NUMBER_ADDR_CMD_OFFSET_SWEEPS]; #endif #endif +#ifdef DEBUG_DDR_INIT +extern mss_uart_instance_t *g_debug_uart; +#endif /******************************************************************************* * External function declarations @@ -46,12 +49,16 @@ extern void delay(uint32_t n); * Local function declarations */ static uint32_t ddr_write ( volatile uint64_t *DDR_word_ptr,\ - uint32_t no_of_access, uint8_t data_ptrn ); + uint32_t no_of_access, uint8_t data_ptrn, DDR_ACCESS_SIZE data_size ); static uint32_t ddr_read ( volatile uint64_t *DDR_word_ptr,\ - uint32_t no_of_access, uint8_t data_ptrn ); -#ifdef DEBUG_DDR_INIT -extern mss_uart_instance_t *g_debug_uart; -#endif + uint32_t no_of_access, uint8_t data_ptrn, DDR_ACCESS_SIZE data_size ); + + +__attribute__((weak)) int rand(void) +{ + return 0; +} + #ifdef DEBUG_DDR_INIT /***************************************************************************//** @@ -165,13 +172,18 @@ static uint32_t ddr_write ( volatile uint64_t *DDR_word_ptr, uint32_t no_of_access, - uint8_t data_ptrn + uint8_t data_ptrn, + DDR_ACCESS_SIZE data_size ) { uint32_t i; uint64_t DATA; uint32_t error_count = 0U; + uint32_t *DDR_32_ptr = (uint32_t *)DDR_word_ptr; + uint16_t *DDR_16_ptr = (uint16_t *)DDR_word_ptr; + uint8_t *DDR_8_ptr = (uint8_t *)DDR_word_ptr; + switch (data_ptrn) { case PATTERN_INCREMENTAL : DATA = 0x00000000; break; @@ -197,8 +209,30 @@ static uint32_t ddr_write for( i = 0; i< (no_of_access); i++) { - *DDR_word_ptr = DATA; - DDR_word_ptr = DDR_word_ptr + 1; + switch(data_size) + { + case DDR_8_BIT: + DATA &= 0xFFUL; + *DDR_8_ptr = (uint8_t)DATA; + DDR_8_ptr = DDR_8_ptr + 1; + break; + case DDR_16_BIT: + DATA &= 0xFFFFUL; + *DDR_16_ptr = (uint16_t)DATA; + DDR_16_ptr = DDR_16_ptr + 1; + break; + case DDR_32_BIT: + DATA &= 0xFFFFFFFFUL; + *DDR_32_ptr = (uint32_t)DATA; + DDR_32_ptr = DDR_32_ptr + 1; + break; + default: + case DDR_64_BIT: + *DDR_word_ptr = DATA; + DDR_word_ptr = DDR_word_ptr + 1; + break; + } + #ifdef DEBUG_DDR_INIT if((i%0x1000000UL) ==0UL) { @@ -254,7 +288,8 @@ uint32_t ddr_read ( volatile uint64_t *DDR_word_ptr, uint32_t no_of_access, - uint8_t data_ptrn + uint8_t data_ptrn, + DDR_ACCESS_SIZE data_size ) { uint32_t i; @@ -263,9 +298,16 @@ uint32_t ddr_read volatile uint64_t ddr_data; volatile uint64_t *DDR_word_pt_t, *first_DDR_word_pt_t; uint32_t rand_addr_offset; + uint8_t *DDR_8_pt_t; + uint16_t *DDR_16_pt_t; + uint32_t *DDR_32_pt_t; err_cnt = 0U; first_DDR_word_pt_t = DDR_word_ptr; + DDR_8_pt_t = (uint8_t *)DDR_word_ptr; + DDR_16_pt_t = (uint16_t *)DDR_word_ptr; + DDR_32_pt_t = (uint32_t *)DDR_word_ptr; + switch (data_ptrn) { case PATTERN_INCREMENTAL : DATA = 0x00000000; break; @@ -275,6 +317,9 @@ uint32_t ddr_read case PATTERN_RANDOM : DATA = (uint64_t)rand ( ); *DDR_word_ptr = DATA; + *DDR_8_pt_t = (uint8_t)DATA; + *DDR_16_pt_t = (uint16_t)DATA; + *DDR_32_pt_t = (uint32_t)DATA; break; case PATTERN_0xCCCCCCCC : DATA = 0xCCCCCCCCCCCCCCCC; @@ -295,8 +340,26 @@ uint32_t ddr_read } for( i = 0; i< (no_of_access); i++) { - DDR_word_pt_t = DDR_word_ptr; - ddr_data = *DDR_word_pt_t; + switch(data_size) + { + case DDR_8_BIT: + DATA &= 0xFFUL; + ddr_data = *DDR_8_pt_t; + break; + case DDR_16_BIT: + DATA &= 0xFFFFUL; + ddr_data = *DDR_16_pt_t; + break; + case DDR_32_BIT: + DATA &= 0xFFFFFFFFUL; + ddr_data = *DDR_32_pt_t; + break; + default: + case DDR_64_BIT: + DDR_word_pt_t = DDR_word_ptr; + ddr_data = *DDR_word_pt_t; + break; + } #ifdef DEBUG_DDR_INIT if((i%0x1000000UL) ==0UL) @@ -333,6 +396,9 @@ uint32_t ddr_read #endif } DDR_word_ptr = DDR_word_ptr + 1U; + DDR_8_pt_t = DDR_8_pt_t +1U; + DDR_16_pt_t = DDR_16_pt_t +1U; + DDR_32_pt_t = DDR_32_pt_t +1U; switch (data_ptrn) { case PATTERN_INCREMENTAL : DATA = DATA + 0x01; break; @@ -358,7 +424,13 @@ uint32_t ddr_read DATA = (uint64_t)rand ( ); rand_addr_offset = (uint32_t)(rand() & 0xFFFFCUL); DDR_word_ptr = first_DDR_word_pt_t + rand_addr_offset; - *DDR_word_ptr = DATA; + DDR_8_pt_t = (uint8_t *)(first_DDR_word_pt_t + rand_addr_offset); + DDR_16_pt_t = (uint16_t *)(first_DDR_word_pt_t + rand_addr_offset); + DDR_32_pt_t = (uint32_t *)(first_DDR_word_pt_t + rand_addr_offset); + *DDR_word_ptr = DATA; + *DDR_8_pt_t = (uint8_t)DATA; + *DDR_16_pt_t = (uint16_t)DATA; + *DDR_32_pt_t = (uint32_t)DATA; break; case PATTERN_0xCCCCCCCC : DATA = 0xCCCCCCCCCCCCCCCC; @@ -399,12 +471,24 @@ uint32_t ddr_read_write_fn (uint64_t* DDR_word_ptr, uint32_t no_access,\ #ifdef DEBUG_DDR_INIT uprint32(g_debug_uart,"\n\r\t Pattern: 0x", pattern_shift); #endif + +#if TEST_64BIT_ACCESS == 1 /* write the pattern */ error_cnt += ddr_write ((uint64_t *)DDR_word_ptr,\ - no_access, pattern_mask); + no_access, pattern_mask, DDR_64_BIT); /* read back and verifies */ error_cnt += ddr_read ((uint64_t *)DDR_word_ptr, \ - no_access, pattern_mask); + no_access, pattern_mask, DDR_64_BIT); +#endif + +#if TEST_32BIT_ACCESS == 1 + /* write the pattern */ + error_cnt += ddr_write ((uint64_t *)DDR_word_ptr,\ + no_access, pattern_mask, DDR_32_BIT); + /* read back and verifies */ + error_cnt += ddr_read ((uint64_t *)DDR_word_ptr, \ + no_access, pattern_mask, DDR_32_BIT); +#endif } } DDR_word_ptr++; /* increment the address */ diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_debug.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h similarity index 94% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_debug.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h index 3bd1f05..e8cf430 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/nwc/mss_ddr_debug.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_debug.h @@ -40,13 +40,29 @@ #define __MSS_DDr_DEBUG_H_ 1 #ifdef DEBUG_DDR_INIT -#include "drivers/mss_uart/mss_uart.h" +#include "drivers/mss_mmuart/mss_uart.h" #endif #ifdef __cplusplus extern "C" { #endif +#ifndef TEST_64BIT_ACCESS +#define TEST_64BIT_ACCESS 1 +#endif + +#ifndef TEST_32BIT_ACCESS +#define TEST_32BIT_ACCESS 1 +#endif + +typedef enum DDR_ACCESS_SIZE_ +{ + DDR_8_BIT, + DDR_16_BIT, + DDR_32_BIT, + DDR_64_BIT +} DDR_ACCESS_SIZE; + /***************************************************************************//** The ddr_read_write_fn function is used to write/read test patterns to the DDR diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_defs.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_defs.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_defs.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_sgmii_phy_defs.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_sgmii_phy_defs.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_sgmii_phy_defs.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_sgmii_phy_defs.h index 25d440d..3f0710d 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_ddr_sgmii_phy_defs.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_ddr_sgmii_phy_defs.h @@ -19,7 +19,7 @@ #define MSS_DDR_SGMII_PHY_DEFS_H_ -#include "mpfs_hal/mss_hal.h" +#include #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_io.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_io.c similarity index 97% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_io.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_io.c index cf7e0e2..c040578 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_io.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_io.c @@ -13,14 +13,14 @@ * @brief MSS IO related code * */ +#include #include #include -#include "mpfs_hal/mss_hal.h" /******************************************************************************* * external functions */ -extern g5_mss_top_scb_regs_TypeDef *SCB_REGS; + /* * IOMUX values from Libero @@ -154,7 +154,7 @@ static uint8_t io_mux_and_bank_config(void) * entry to the IOMUX structure * * */ - config_copy((void *)(&(SYSREG->IOMUX0_CR)), + config_32_copy((void *)(&(SYSREG->IOMUX0_CR)), &(iomux_config_values), sizeof(IOMUX_CONFIG)); @@ -186,11 +186,11 @@ static uint8_t io_mux_and_bank_config(void) | io_cfg_lp_bypass_en |14 | | * */ - config_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), + config_32_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), &(mssio_bank4_io_config), sizeof(MSSIO_BANK4_CONFIG)); - config_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), + config_32_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), &(mssio_bank2_io_config), sizeof(MSSIO_BANK2_CONFIG)); diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_io_config.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_io_config.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_io_config.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_io_config.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_nwc_init.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c similarity index 98% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_nwc_init.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c index b965195..03e186b 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_nwc_init.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_nwc_init.c @@ -16,13 +16,12 @@ #include #include - #include "mpfs_hal/mss_hal.h" #include "mss_nwc_init.h" #include "simulation.h" #ifdef DEBUG_DDR_INIT -#include "drivers/mss_uart/mss_uart.h" +#include "drivers/mss_mmuart/mss_uart.h" extern mss_uart_instance_t *g_debug_uart ; uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); #endif @@ -48,13 +47,8 @@ void delay(uint32_t n); /******************************************************************************* * extern defined functions */ -extern void delay(uint32_t n); #ifndef SIFIVE_HIFIVE_UNLEASHED extern void mss_pll_config(void); -extern uint32_t sgmii_setup(void); -#ifdef MSSIO_SUPPORT -extern uint8_t mssio_setup(void); -#endif #endif #ifdef DEBUG_DDR_INIT uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); @@ -63,8 +57,6 @@ uint32_t setup_ddr_debug_port(mss_uart_instance_t * uart); /****************************************************************************** * Public Functions - API ******************************************************************************/ -uint8_t mss_nwc_init(void); - /** * MSS_DDR_init_simulation(void) diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_nwc_init.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_nwc_init.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_nwc_init.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_pll.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_pll.c similarity index 97% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_pll.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_pll.c index e5257a0..202b96f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_pll.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_pll.c @@ -65,7 +65,7 @@ static void copy_switch_code(void); * Public Functions - API * ******************************************************************************/ void mss_pll_config(void); - +void sgmii_mux_config(uint8_t option); /******************************************************************************* Local functions * @@ -302,11 +302,11 @@ __attribute__((section(".ram_codetext"))) \ } /***************************************************************************//** - * sgmii_mux_config_via_scb(uint8_t option) + * sgmii_mux_config(uint8_t option) * @param option 1 => soft reset, load RPC settings * 0 => write values using SCB ******************************************************************************/ -void sgmii_mux_config_via_scb(uint8_t option) +void sgmii_mux_config(uint8_t option) { switch(option) { @@ -321,7 +321,7 @@ void sgmii_mux_config_via_scb(uint8_t option) */ /* CFM_ETH - 0x3E200000 - - 0x08 */ MSS_SCB_CFM_SGMII_MUX->SGMII_CLKMUX =\ - LIBERO_SETTING_SGMII_SGMII_CLKMUX; + LIBERO_SETTING_SGMII_SGMII_CLKMUX; /* * SCB address: 0x3E20 0010 * Clock_Receiver @@ -360,7 +360,7 @@ void sgmii_mux_config_via_scb(uint8_t option) */ /* 0x05 => ref to SGMII and DDR */ MSS_SCB_CFM_SGMII_MUX->RFCKMUX =\ - LIBERO_SETTING_SGMII_SGMII_CLKMUX; + LIBERO_SETTING_SGMII_REFCLKMUX; break; case RPC_REG_UPDATE: @@ -373,18 +373,6 @@ void sgmii_mux_config_via_scb(uint8_t option) } } - -/***************************************************************************//** - * sgmii_mux_config_via_scb(option) - * @param option 1 => soft reset, load RPC settings - * 0 => write values using SCB - ******************************************************************************/ -void pre_configure_sgmii_and_ddr_pll_via_scb(uint8_t option) -{ - sgmii_mux_config_via_scb(option); -} - - /***************************************************************************//** * * On startup, MSS supplied with 80MHz SCB clock @@ -584,7 +572,7 @@ void ddr_pll_config(REG_LOAD_METHOD option) * CFG_DDR_SGMII_PHY->PLL_CAL_MAIN.PLL_CAL_MAIN =\ * LIBERO_SETTING_DDR_PLL_CAL; */ CFG_DDR_SGMII_PHY->PLL_PHADJ_MAIN.PLL_PHADJ_MAIN =\ - LIBERO_SETTING_MSS_PLL_PHADJ; + LIBERO_SETTING_DDR_PLL_PHADJ; /*__I CFG_DDR_SGMII_PHY_SSCG_REG_0_MAIN_TypeDef SSCG_REG_0_MAIN; */ /*__I CFG_DDR_SGMII_PHY_SSCG_REG_1_MAIN_TypeDef SSCG_REG_1_MAIN; */ CFG_DDR_SGMII_PHY->SSCG_REG_2_MAIN.SSCG_REG_2_MAIN =\ @@ -679,7 +667,7 @@ void sgmii_pll_config_scb(uint8_t option) /* PLL phase registers */ - MSS_SCB_SGMII_PLL->PLL_PHADJ = LIBERO_SETTING_MSS_PLL_PHADJ; + MSS_SCB_SGMII_PLL->PLL_PHADJ = LIBERO_SETTING_SGMII_PLL_PHADJ; MSS_SCB_SGMII_PLL->PLL_CTRL = (LIBERO_SETTING_SGMII_PLL_CTRL)\ | 0x01U; /* bit 0 == REG_POWERDOWN_B */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_pll.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_pll.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_pll.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_pll.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_scb_nwc_regs.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h similarity index 99% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_scb_nwc_regs.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h index fe58e91..77aa5ea 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_scb_nwc_regs.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_scb_nwc_regs.h @@ -17,7 +17,7 @@ #ifndef MSS_DDR_SGMII_MSS_SCB_NWC_REGS_H_ #define MSS_DDR_SGMII_MSS_SCB_NWC_REGS_H_ -#include "mpfs_hal/mss_hal.h" +#include #ifdef __cplusplus diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_sgmii.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_sgmii.c similarity index 98% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_sgmii.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_sgmii.c index d93ca4b..47a79da 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_sgmii.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_sgmii.c @@ -23,12 +23,14 @@ * local functions */ static void setup_sgmii_rpc_per_config(void); +#ifdef SGMII_SUPPORT static uint32_t sgmii_channel_setup(void); +#endif /* * extern functions */ -extern void pre_configure_sgmii_and_ddr_pll_via_scb(uint8_t option); +extern void sgmii_mux_config(uint8_t option); uint32_t sgmii_setup(void) @@ -44,15 +46,13 @@ uint32_t sgmii_setup(void) } else { - pre_configure_sgmii_and_ddr_pll_via_scb(0U); /* 0U => configure - using the SCB */ sgmii_off_mode(); + sgmii_mux_config(RPC_REG_UPDATE); } #else { - pre_configure_sgmii_and_ddr_pll_via_scb(0U); /* 0U => configure - using the SCB */ sgmii_off_mode(); + sgmii_mux_config(RPC_REG_UPDATE); } #endif return(0UL); @@ -64,6 +64,7 @@ uint32_t sgmii_setup(void) * @param sgmii_instruction * @return */ +#ifdef SGMII_SUPPORT static uint32_t sgmii_channel_setup(void) { /* @@ -283,7 +284,7 @@ static uint32_t sgmii_channel_setup(void) */ SIM_FEEDBACK1(9U); /* 0U => configure using scb, 1U => NVMAP reset */ - pre_configure_sgmii_and_ddr_pll_via_scb(1U); + sgmii_mux_config(RPC_REG_UPDATE); SIM_FEEDBACK1(10U); /* 0U => configure using scb, 1U => NVMAP reset */ sgmii_pll_config_scb(1U); @@ -398,7 +399,7 @@ static uint32_t sgmii_channel_setup(void) return(0U); } - +#endif /** * setup_sgmii_rpc_per_config diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_sgmii.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_sgmii.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/mss_sgmii.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/mss_sgmii.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/readme.md b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/readme.md similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/readme.md rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/readme.md diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/simulation.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/simulation.h similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/nwc/simulation.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/nwc/simulation.h diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/readme.md b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/readme.md new file mode 100644 index 0000000..f2ad581 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/common/readme.md @@ -0,0 +1,121 @@ +=============================================================================== +# mpfs_hal +=============================================================================== + +The PolarFire-SoC MSS HAL provides the initial boot code, interrupt handling, +and hardware access methods for the MPFS MSS. The terms PolarFire-SoC HAL and +MPFS HAL are used interchangeably but in the main the term PolarFire-SoC MSS HAL +is preferred. +The PolarFire-SoC MSS hal is a combination of C and assembly source code. + +The mpfs_hal folder is included in an PolarFire Embedded project under the +platform directory. + +It contains : + +* Start-up code executing from reset +* Interrupt handling support +* Exception handling support +* Memory protection configuration, PMP and MPU +* DDR configuration +* SGMII configuration +* MSSIO setup + +## Inputs to the mss_hal +There are two configuration sources. + +1. Libero design + + Libero input through header files located in the config/hardware under the + platform directory. These files are generated using the PF SoC embedded + software configuration generator. It takes an xml file generated in the Libero + design flow and produces header files based on the xml content in a suitable + form for consumption by the hal. + +2. Software configuration + Software configuration settings are located in the mpfs_hal_config folder. + + +### Example Project directory structure, showing where mpfs_hal folder sits. + +~~~~ + + +---------+ + | project | + +----+----+ +---------+ +-----------+ + +-----+| src |----->|application| + +---------+ | +-----------+ + | + | +-----------+ + +-->|boards | + + +----+------+ + | | +---------------+ + | +---------+|icicle-kit-es | + | +---+-----------+ + | | + | | +---------------+ + | +->|platform_config| + | | +---------------+ + | | + | | +---------------+ + | |---------|drivers_config | + | | +---------------+ + | | + | | +---------------+ + | |---------|linker | + | | +---------------+ + | | + | | +---------------+ + | |---------|mpfs_hal_config| + | | +---------------+ + | | + | | + | | +---------------+ + | +>|soc_config | + | | +---+-----------+ + | | | + | | | +---------------+------------------------+ + | | +->|multiple folders with fpga config for sw| + | | +----------------------------------------+ + | | + | | + | | + | | +---------------+ + | +>|soc_fpga_design| + | +--+------------+ + | | + | | +---------------+ + | +-->|libero_tcl | + | | +---------------+ + | | + | +-----------+ | +---------------+ + +--+|middleware + +-->|xml | + | +-----------+ +---------------+ + | + + + | +-----------+ + +--+|platform | + +----+------+ + | +---------------+ + +---------+|drivers | + | +---------------+ + | + | +---------------+ + +---------+|hal | + | +---------------+ + | + | +---------------+ + +---------+|mpfs_hal | + | +---------------+ + | + | +-------------------------+ + +---------+|platform_config_reference| + | +-------------------------+ + | + | +---------------------+ + +---------+|soc_config_generator | + +---------------------+ +~~~~ + +Please see the user guide for further details on +use. diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mcall.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mcall.h deleted file mode 100644 index faf2db5..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mcall.h +++ /dev/null @@ -1,35 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * -*/ - -/*********************************************************************************** - * @file mcall.h - * @author Microchip-FPGA Embedded Systems Solutions - * @brief mcall definitions - - */ -#ifndef RISCV_SBI_H -#define RISCV_SBI_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define SBI_SET_TIMER 0 -#define SBI_CLEAR_IPI 3 -#define SBI_SEND_IPI 4 -#define SBI_REMOTE_FENCE_I 5 -#define SBI_REMOTE_SFENCE_VMA 6 -#define SBI_REMOTE_SFENCE_VMA_ASID 7 - -#ifdef __cplusplus -} -#endif - -#endif //RISCV_SBI_H - diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mpfs_hal_version.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mpfs_hal_version.h new file mode 100644 index 0000000..7fb26dd --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mpfs_hal_version.h @@ -0,0 +1,50 @@ +#ifndef MPFS_HAL_VERSION_H +#define MPFS_HAL_VERSION_H + +/******************************************************************************* + * Copyright 2019-2020 Microchip Corporation. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * + * + */ + +/******************************************************************************* + * @file mpfs_halversion.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief PolareFire SoC Hardware Abstraction layer - MPFS HAL version. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MPFS_HAL_VERSION_MAJOR 1 +#define MPFS_HAL_VERSION_MINOR 8 +#define MPFS_HAL_VERSION_PATCH 0 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_coreplex.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_coreplex.h deleted file mode 100644 index 8d35fc6..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_coreplex.h +++ /dev/null @@ -1,100 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ - -/*************************************************************************** - * @file mss_coreplex.h - * @author Microchip-FPGA Embedded Systems Solutions - * @brief Coreplex definitions - * - */ -#ifndef MSS_COREPLEX_H -#define MSS_COREPLEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * U5 COREPLEX DEFINITIONS - */ -#define U5CP_CLINT_BASE (0x02000000) -#define U5CP_CACHE_CTRL_PORT_BASE (0x02010000) -#define CACHE_CTRL_NUM_BANKS_OFFSET (0x000) -#define CACHE_CTRL_NUM_WAYS_OFFSET (0x001) -#define CACHE_CTRL_NUM_SETS_OFFSET (0x002) -#define CACHE_CTRL_BLKSIZE_OFFSET (0x003) -#define CACHE_CTRL_WAYENB_OFFSET (0x008) -#define CACHE_CTRL_ERR_INJ_OFFSET (0x040) -#define CACHE_CTRL_ADDR_META_DATA_ERR_OFFSET (0x100) -#define CACHE_CTRL_NUM_META_DATA_ERRS_OFFSET (0x108) -#define CACHE_CTRL_ADDR_DATA_ERR_OFFSET (0x140) -#define CACHE_CTRL_NUM_DATA_ERRS_OFFSET (0x148) -#define CACHE_CTRL_ADDR_UNCORRECTABLE_DATA_OFFSET (0x160) -#define CACHE_CTRL_NUM_UNCORRECTABLE_DATA_ERRS_OFFSET (0x168) -#define CACHE_CTRL_FLUSH64_OFFSET (0x200) -#define CACHE_CTRL_FLUSH32_OFFSET (0x240) -#define CACHE_CTRL_MASTER0_WAY_OFFSET (0x800) - -#define CACHE_CTRL_NUM_BANKS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_BANKS_OFFSET) -#define CACHE_CTRL_NUM_WAYS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_WAYS_OFFSET) -#define CACHE_CTRL_NUM_SETS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_SETS_OFFSET) -#define CACHE_CTRL_BLKSIZE_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_BLKSIZE_OFFSET) -#define CACHE_CTRL_WAYENB_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_WAYENB_OFFSET) -#define CACHE_CTRL_ERR_INJ_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ERR_INJ_OFFSET) -#define CACHE_CTRL_ADDR_META_DATA_ERR_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ADDR_META_DATA_ERR_OFFSET) -#define CACHE_CTRL_NUM_META_DATA_ERRS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_META_DATA_ERRS_OFFSET) -#define CACHE_CTRL_ADDR_DATA_ERR_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ADDR_DATA_ERR_OFFSET) -#define CACHE_CTRL_NUM_DATA_ERRS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_DATA_ERRS_OFFSET) -#define CACHE_CTRL_ADDR_UNCORRECTABLE_DATA_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_ADDR_UNCORRECTABLE_DATA_OFFSET) -#define CACHE_CTRL_NUM_UNCORRECTABLE_DATA_ERRS_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_NUM_UNCORRECTABLE_DATA_ERRS_OFFSET) -#define CACHE_CTRL_FLUSH64_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_FLUSH64_OFFSET) -#define CACHE_CTRL_FLUSH32_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_FLUSH32_OFFSET) -#define CACHE_CTRL_MASTER0_WAY_REG \ - (U5CP_CACHE_CTRL_PORT_BASE + CACHE_CTRL_MASTER0_WAY_OFFSET) - -#define U5CP_MSIP_BASE (U5CP_CLINT_BASE) -#define U5CP_MSIP_H0 (U5CP_MSIP_BASE + 0x00) -#define U5CP_MSIP_H1 (U5CP_MSIP_BASE + 0x04) -#define U5CP_MSIP_H2 (U5CP_MSIP_BASE + 0x08) -#define U5CP_MSIP_H3 (U5CP_MSIP_BASE + 0x0C) -#define U5CP_MSIP_H4 (U5CP_MSIP_BASE + 0x10) - -#define U5CP_MTIMECMP_BASE (U5CP_CLINT_BASE + 0x4000) -#define U5CP_MTIMECMP_H0 (U5CP_MTIMECMP_BASE + 0x00) -#define U5CP_MTIMECMP_H1 (U5CP_MTIMECMP_BASE + 0x04) -#define U5CP_MTIMECMP_H2 (U5CP_MTIMECMP_BASE + 0x08) -#define U5CP_MTIMECMP_H3 (U5CP_MTIMECMP_BASE + 0x0C) -#define U5CP_MTIMECMP_H4 (U5CP_MTIMECMP_BASE + 0x10) - -#define U5CP_MTIME_BASE (U5CP_CLINT_BASE + 0xBFF8) -#define U5CP_MTIME_H0 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H1 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H2 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H3 (U5CP_MTIME_BASE + 0x00) -#define U5CP_MTIME_H4 (U5CP_MTIME_BASE + 0x00) - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_COREPLEX_H */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_hal.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_hal.h index 87bd7ae..90cfbea 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_hal.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_hal.h @@ -27,13 +27,13 @@ typedef long ssize_t; #endif #endif -#include "mss_assert.h" -#include "mpfs_hal/nwc/mss_ddr_defs.h" -#include "mpfs_hal/nwc/mss_ddr_SGMII_regs.h" -#include "mpfs_hal/nwc/mss_io_config.h" -#include "mpfs_hal/nwc/mss_pll.h" -#include "mpfs_hal/nwc/mss_scb_nwc_regs.h" -#include "mpfs_hal/nwc/mss_scb_nwc_regs.h" +#include "common/mss_assert.h" +#include "common/nwc/mss_ddr_defs.h" +#include "common/nwc/mss_ddr_SGMII_regs.h" +#include "common/nwc/mss_io_config.h" +#include "common/nwc/mss_pll.h" +#include "common/nwc/mss_scb_nwc_regs.h" +#include "common/nwc/mss_scb_nwc_regs.h" /* * mss_sw_config.h may be edited as required and should be located outside the * mpfs_hal folder @@ -44,31 +44,28 @@ typedef long ssize_t; * mss_sw_config.h. This allows defines in hw_platform.h be overload from * mss_sw_config.h if necessary. * */ -#include "atomic.h" -#include "bits.h" -#include "encoding.h" +#include "common/atomic.h" +#include "common/bits.h" +#include "common/encoding.h" #include "soc_config/hw_platform.h" -#include "mpfs_hal/nwc/mss_ddr.h" -#include "mss_clint.h" -#include "mss_coreplex.h" -#include "mss_h2f.h" -#include "mss_hart_ints.h" -#include "mss_ints.h" -#include "mss_mpu.h" -#include "mss_peripheral_base_add.h" -#include "mss_plic.h" -#include "mss_prci.h" -#include "mss_seg.h" -#include "mss_sysreg.h" -#include "mss_util.h" -#include "mtrap.h" -#include "mss_l2_cache.h" -#include "mss_axiswitch.h" -#include "nwc/mss_cfm.h" -#include "nwc/mss_ddr.h" -#include "nwc/mss_sgmii.h" -#include "system_startup.h" -#include "nwc/mss_ddr_debug.h" +#include "common/nwc/mss_ddr.h" +#include "common/mss_clint.h" +#include "common/mss_h2f.h" +#include "common/mss_hart_ints.h" +#include "common/mss_mpu.h" +#include "common/mss_pmp.h" +#include "common/mss_plic.h" +#include "common/mss_seg.h" +#include "common/mss_sysreg.h" +#include "common/mss_util.h" +#include "common/mss_mtrap.h" +#include "common/mss_l2_cache.h" +#include "common/mss_axiswitch.h" +#include "common/nwc/mss_cfm.h" +#include "common/nwc/mss_ddr.h" +#include "common/nwc/mss_sgmii.h" +#include "startup_gcc/system_startup.h" +#include "common/nwc/mss_ddr_debug.h" #ifdef SIMULATION_TEST_FEEDBACK #include "nwc/simulation.h" #endif @@ -77,9 +74,6 @@ typedef long ssize_t; extern "C" { #endif -uint32_t SysTick_Config(void); -void disable_systick(void); - #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_ints.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_ints.h deleted file mode 100644 index 92a4394..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_ints.h +++ /dev/null @@ -1,180 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ - -/******************************************************************************* - * - * @file mss_ints.h - * @author Microchip-FPGA Embedded Systems Solutions - * @brief MPFS interrupt prototypes - * - * Interrupt function prototypes - * - */ - -#ifndef MSS_INTS_H -#define MSS_INTS_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -void handle_m_ext_interrupt(void); -void Software_h0_IRQHandler(void); -void Software_h1_IRQHandler(void); -void Software_h2_IRQHandler(void); -void Software_h3_IRQHandler(void); -void Software_h4_IRQHandler(void); -void SysTick_Handler_h0_IRQHandler(void); -void SysTick_Handler_h1_IRQHandler(void); -void SysTick_Handler_h2_IRQHandler(void); -void SysTick_Handler_h3_IRQHandler(void); -void SysTick_Handler_h4_IRQHandler(void); - -/* - * - * Local interrupt stubs - * - */ -void maintenance_e51_local_IRQHandler_0(void); -void usoc_smb_interrupt_e51_local_IRQHandler_1(void); -void usoc_vc_interrupt_e51_local_IRQHandler_2(void); -void g5c_message_e51_local_IRQHandler_3(void); -void g5c_devrst_e51_local_IRQHandler_4(void); -void wdog4_tout_e51_local_IRQHandler_5(void); -void wdog3_tout_e51_local_IRQHandler_6(void); -void wdog2_tout_e51_local_IRQHandler_7(void); -void wdog1_tout_e51_local_IRQHandler_8(void); -void wdog0_tout_e51_local_IRQHandler_9(void); -void wdog0_mvrp_e51_local_IRQHandler_10(void); -void mmuart0_e51_local_IRQHandler_11(void); -void envm_e51_local_IRQHandler_12(void); -void ecc_correct_e51_local_IRQHandler_13(void); -void ecc_error_e51_local_IRQHandler_14(void); -void scb_interrupt_e51_local_IRQHandler_15(void); -void fabric_f2h_32_e51_local_IRQHandler_16(void); -void fabric_f2h_33_e51_local_IRQHandler_17(void); -void fabric_f2h_34_e51_local_IRQHandler_18(void); -void fabric_f2h_35_e51_local_IRQHandler_19(void); -void fabric_f2h_36_e51_local_IRQHandler_20(void); -void fabric_f2h_37_e51_local_IRQHandler_21(void); -void fabric_f2h_38_e51_local_IRQHandler_22(void); -void fabric_f2h_39_e51_local_IRQHandler_23(void); -void fabric_f2h_40_e51_local_IRQHandler_24(void); -void fabric_f2h_41_e51_local_IRQHandler_25(void); -void fabric_f2h_42_e51_local_IRQHandler_26(void); -void fabric_f2h_43_e51_local_IRQHandler_27(void); -void fabric_f2h_44_e51_local_IRQHandler_28(void); -void fabric_f2h_45_e51_local_IRQHandler_29(void); -void fabric_f2h_46_e51_local_IRQHandler_30(void); -void fabric_f2h_47_e51_local_IRQHandler_31(void); -void fabric_f2h_48_e51_local_IRQHandler_32(void); -void fabric_f2h_49_e51_local_IRQHandler_33(void); -void fabric_f2h_50_e51_local_IRQHandler_34(void); -void fabric_f2h_51_e51_local_IRQHandler_35(void); -void fabric_f2h_52_e51_local_IRQHandler_36(void); -void fabric_f2h_53_e51_local_IRQHandler_37(void); -void fabric_f2h_54_e51_local_IRQHandler_38(void); -void fabric_f2h_55_e51_local_IRQHandler_39(void); -void fabric_f2h_56_e51_local_IRQHandler_40(void); -void fabric_f2h_57_e51_local_IRQHandler_41(void); -void fabric_f2h_58_e51_local_IRQHandler_42(void); -void fabric_f2h_59_e51_local_IRQHandler_43(void); -void fabric_f2h_60_e51_local_IRQHandler_44(void); -void fabric_f2h_61_e51_local_IRQHandler_45(void); -void fabric_f2h_62_e51_local_IRQHandler_46(void); -void fabric_f2h_63_e51_local_IRQHandler_47(void); - -/* - * U54 - */ -void spare_u54_local_IRQHandler_0(void); -void spare_u54_local_IRQHandler_1(void); -void spare_u54_local_IRQHandler_2(void); - -void mac_mmsl_u54_1_local_IRQHandler_3(void); -void mac_emac_u54_1_local_IRQHandler_4(void); -void mac_queue3_u54_1_local_IRQHandler_5(void); -void mac_queue2_u54_1_local_IRQHandler_6(void); -void mac_queue1_u54_1_local_IRQHandler_7(void); -void mac_int_u54_1_local_IRQHandler_8(void); - -void mac_mmsl_u54_2_local_IRQHandler_3(void); -void mac_emac_u54_2_local_IRQHandler_4(void); -void mac_queue3_u54_2_local_IRQHandler_5(void); -void mac_queue2_u54_2_local_IRQHandler_6(void); -void mac_queue1_u54_2_local_IRQHandler_7(void); -void mac_int_u54_2_local_IRQHandler_8(void); - -void mac_mmsl_u54_3_local_IRQHandler_3(void); -void mac_emac_u54_3_local_IRQHandler_4(void); -void mac_queue3_u54_3_local_IRQHandler_5(void); -void mac_queue2_u54_3_local_IRQHandler_6(void); -void mac_queue1_u54_3_local_IRQHandler_7(void); -void mac_int_u54_3_local_IRQHandler_8(void); - -void mac_mmsl_u54_4_local_IRQHandler_3(void); -void mac_emac_u54_4_local_IRQHandler_4(void); -void mac_queue3_u54_4_local_IRQHandler_5(void); -void mac_queue2_u54_4_local_IRQHandler_6(void); -void mac_queue1_u54_4_local_IRQHandler_7(void); -void mac_int_u54_4_local_IRQHandler_8(void); - -void wdog_tout_u54_h1_local_IRQHandler_9(void); -void wdog_tout_u54_h2_local_IRQHandler_9(void); -void wdog_tout_u54_h3_local_IRQHandler_9(void); -void wdog_tout_u54_h4_local_IRQHandler_9(void); -void mvrp_u54_local_IRQHandler_10(void); -void mmuart_u54_h1_local_IRQHandler_11(void); -void mmuart_u54_h2_local_IRQHandler_11(void); -void mmuart_u54_h3_local_IRQHandler_11(void); -void mmuart_u54_h4_local_IRQHandler_11(void); -void spare_u54_local_IRQHandler_12(void); -void spare_u54_local_IRQHandler_13(void); -void spare_u54_local_IRQHandler_14(void); -void spare_u54_local_IRQHandler_15(void); -void fabric_f2h_0_u54_local_IRQHandler_16(void); -void fabric_f2h_1_u54_local_IRQHandler_17(void); -void fabric_f2h_2_u54_local_IRQHandler_18(void); -void fabric_f2h_3_u54_local_IRQHandler_19(void); -void fabric_f2h_4_u54_local_IRQHandler_20(void); -void fabric_f2h_5_u54_local_IRQHandler_21(void); -void fabric_f2h_6_u54_local_IRQHandler_22(void); -void fabric_f2h_7_u54_local_IRQHandler_23(void); -void fabric_f2h_8_u54_local_IRQHandler_24(void); -void fabric_f2h_9_u54_local_IRQHandler_25(void); -void fabric_f2h_10_u54_local_IRQHandler_26(void); -void fabric_f2h_11_u54_local_IRQHandler_27(void); -void fabric_f2h_12_u54_local_IRQHandler_28(void); -void fabric_f2h_13_u54_local_IRQHandler_29(void); -void fabric_f2h_14_u54_local_IRQHandler_30(void); -void fabric_f2h_15_u54_local_IRQHandler_31(void); -void fabric_f2h_16_u54_local_IRQHandler_32(void); -void fabric_f2h_17_u54_local_IRQHandler_33(void); -void fabric_f2h_18_u54_local_IRQHandler_34(void); -void fabric_f2h_19_u54_local_IRQHandler_35(void); -void fabric_f2h_20_u54_local_IRQHandler_36(void); -void fabric_f2h_21_u54_local_IRQHandler_37(void); -void fabric_f2h_22_u54_local_IRQHandler_38(void); -void fabric_f2h_23_u54_local_IRQHandler_39(void); -void fabric_f2h_24_u54_local_IRQHandler_40(void); -void fabric_f2h_25_u54_local_IRQHandler_41(void); -void fabric_f2h_26_u54_local_IRQHandler_42(void); -void fabric_f2h_27_u54_local_IRQHandler_43(void); -void fabric_f2h_28_u54_local_IRQHandler_44(void); -void fabric_f2h_29_u54_local_IRQHandler_45(void); -void fabric_f2h_30_u54_local_IRQHandler_46(void); -void fabric_f2h_31_u54_local_IRQHandler_47(void); - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_INTS_H */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_peripheral_base_add.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_peripheral_base_add.h deleted file mode 100644 index 402da44..0000000 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_peripheral_base_add.h +++ /dev/null @@ -1,108 +0,0 @@ -/******************************************************************************* - * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. - * - * SPDX-License-Identifier: MIT - * - * MPFS HAL Embedded Software - * - */ - -/******************************************************************************* - * - * @file mss_peripheral_base_add.h - * @author Microchip-FPGA Embedded Systems Solutions - * MSSIO bank numbers - * - */ - -#ifndef MSS_ADDRESS_MAP_H -#define MSS_ADDRESS_MAP_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL -#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL -#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL -#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL -#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL - -#define ERROR_DEVICE 0x18000000UL /* hifive unleashed only */ - -/* APB slots */ -/* - * By default, all the APB peripherals are connected to AXI-Slave 5 using the AXI to AHB and AHB to APB - * bridges. This means that the multiple CPUS and Fabric interfaces arbitrate - * for access to the APB slaves resulting in a variable access latency depended on system activity. This may - * cause system issues in particular in AMP mode with two separate operating systems running on different CPU’s - * A second AHB/APB bus system is connected to the AXI slave 6 port using system addresses 0x28000000-0x2FFFFFFF. - * Each of the APB peripherals can be configured at device start up to be connected the main APB bus - * (0x20000000-0x203FFFFF) or to the AMP APB bus (0x28000000-0x283FFFFF). This allows two independent access systems - * from the CPUS to the peripherals. Devices marked as DUAL SLOT in the defines below may be mapped to the second APB - * bus structure. - * - */ -#define MSS_BASE_ADD_MMUART0 0x20000000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG0 0x20001000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_SYSREG_PRIV 0x20002000UL -#define MSS_BASE_ADD_SYSREG_SCB 0x20003000UL -#define MSS_BASE_ADD_AXISW_CFG 0x20004000UL -#define MSS_BASE_ADD_MPUCFG 0x20005000UL -#define MSS_BASE_ADD_FMETER 0x20006000UL -#define MSS_BASE_ADD_FI_CFG 0x20007000UL -#define MSS_BASE_ADD_MMC_CFG 0x20008000UL -#define MSS_BASE_ADD_DRC_CFG 0x20080000UL -#define MSS_BASE_ADD_MMUART1 0x20100000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG1 0x20101000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MMUART2 0x20102000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG2 0x20103000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MMUART3 0x20104000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG3 0x20105000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MMUART4 0x20106000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_WDOG4 0x20107000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_SPI0 0x20108000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_SPI1 0x20109000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_I2C0 0x2010A000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_I2C1 0x2010B000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_AN0 0x2010C000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_AN1 0x2010D000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MAC0_CFG 0x20110000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MAC1_CFG 0x20112000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_GPIO0 0x20120000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_GPIO1 0x20121000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_GPIO2 0x20122000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MSRTC 0x20124000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_MSTIMER 0x20125000UL /* DUAL SLOT */ -#define MSS_BASE_ADD_H2FINT 0x20126000UL /* DUAL SLOT */ - -#define MSS_BASE_ADD_NVM_CFG 0x20200000UL -#define MSS_BASE_ADD_USB_CFG 0x20201000UL -#define MSS_BASE_ADD_NVM_DATA 0x20220000UL -#define MSS_BASE_ADD_QSPI_XIP 0x21000000UL -#define MSS_BASE_ADD_ATHENA 0x22000000UL -#define MSS_BASE_ADD_TRACE_AXIC 0x23000000UL -#define MSS_BASE_ADD_TRACE_SMB 0x23010000UL -#define MSS_BASE_ADD_TRACE_VC 0x23020000UL - -#define MSS_BASE_ADD_IOSCB_DATA 0x30000000UL -#define MSS_BASE_ADD_IOSCB_CFG 0x37080000UL -#define MSS_BASE_ADD_FIC3_FAB 0x40000000UL - -#define MSS_BASE_ADD_FIC0 0x60000000UL -#define MSS_BASE_ADD_DRC_CACHE 0x80000000UL -#define MSS_BASE_ADD_DRC_NC 0xC0000000UL -#define MSS_BASE_ADD_DRC_NC_WCB 0xD0000000UL -#define MSS_BASE_ADD_FIC1 0xE0000000UL - -#define MSS_BASE_ADD_DRC_CACHE_AXI_L2 0x1000000000UL -#define MSS_BASE_ADD_DRC_NC_AXI_NC 0x1400000000UL -#define MSS_BASE_ADD_DRC_NC_WCB_AXI_NC 0x1800000000UL -#define MSS_BASE_ADD_FIC0_AXI_F0 0x2000000000UL -#define MSS_BASE_ADD_FIC1_AXI_F1 0x3000000000UL - -#ifdef __cplusplus -} -#endif - -#endif /* MSS_ADDRESS_MAP_H */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/entry.S b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/mss_entry.S similarity index 60% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/entry.S rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/mss_entry.S index 9140f45..9e049de 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/entry.S +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/mss_entry.S @@ -13,9 +13,11 @@ * @brief entry functions. * */ -#include "bits.h" -#include "encoding.h" -#include "mtrap.h" + +#include "../common/bits.h" +#include "../common/encoding.h" +#include "../common/mss_mtrap.h" +#include "system_startup_defs.h" #include "mpfs_hal_config/mss_sw_config.h" .option norvc @@ -25,6 +27,13 @@ reset_vector: _start: + /* + * clear the Return Address Stack + */ + call .clear_ras + li a1, 0x3 + csrw 0x7c0, a1 + /* Setup trap handler */ la a4, trap_vector csrw mtvec, a4 # initalise machine trap vector address @@ -49,6 +58,14 @@ _start: csrw mscratch, zero csrw mcause, zero csrw mepc, zero + /* + * clear PMP enables + */ + csrw pmpcfg0, zero + csrw pmpcfg2, zero + /* + * clear regs + */ li x1, 0 li x2, 0 li x3, 0 @@ -183,6 +200,20 @@ _start: call .clear_dtim call .clear_l2lim .skip_mem_clear: + /* + * Clear bus error unit accrued register on start-up + * This is cleared by the first hart only + */ + la a4,0x01700020UL + sb x0, 0(a4) + la a4,0x01701020UL + sb x0, 0(a4) + la a4,0x01702020UL + sb x0, 0(a4) + la a4,0x01703020UL + sb x0, 0(a4) + la a4,0x01704020UL + sb x0, 0(a4) # now core MPFS_HAL_FIRST_HART jumps to main_first_hart .main_hart: j main_first_hart @@ -202,7 +233,17 @@ _start: # enabled- otherwise stays in wfi. # Other interrupts appera to bring out of wfi,even if # not enabled. - li a1, HLS_DATA_IN_WFI + + # + # Wait here until main hart is up and running + # + li a3, HLS_MAIN_HART_STARTED + la a1, (__stack_top_h0$ - HLS_DEBUG_AREA_SIZE) +.wait_main_hart: + LOAD a2, 0(a1) + bne a3, a2, .wait_main_hart + # Flag we are here to the main hart + li a1, HLS_OTHER_HART_IN_WFI STORE a1, 0(tp) /* flush the instruction cache */ fence.i @@ -223,7 +264,7 @@ _start: csrw mie, zero csrw mip, zero # set marker as to where we are - li a1, HLS_DATA_PASSED_WFI + li a1, HLS_OTHER_HART_PASSED_WFI STORE a1, 0(tp) j main_other_hart .LoopForeverOther: @@ -235,6 +276,7 @@ _start: /******************************************************************************/ /******************************interrupt handeling below here******************/ /******************************************************************************/ + trap_vector: # The mscratch register is an XLEN-bit read/write register dedicated for use by machine mode. # Typically, it is used to hold a pointer to a machine-mode hart-local context space and swapped @@ -337,10 +379,186 @@ restore_regs: fence.i ret + /*********************************************************************************** + * + * The following init_memory() symbol overrides the weak symbol in the HAL and does + * a safe copy of RW data and clears zero-init memory + * + */ + // zero_section helper function: + // a0 = exec_start_addr + // a1 = exec_end_addr + // + .globl zero_section + .type zero_section, @function +zero_section: + beq a0, a1, .zero_section_done + sd zero, (a0) + addi a0, a0, 8 + j zero_section +.zero_section_done: + ret + + // zero_section helper function: + // a0 = exec_start_addr + // a1 = exec_end_addr + // a2 = start count + // + .globl count_section + .type count_section, @function +count_section: + beq a0, a1, .count_section_done + sd a2, (a0) + addi a0, a0, 8 + addi a2, a2, 8 + j count_section +.count_section_done: + ret + + // copy_section helper function: + // a0 = load_addr + // a1 = exec_start_addr + // a2 = exec_end_addr + .globl copy_section + .type copy_section, @function +copy_section: + beq a1, a0, .copy_section_done // if load_addr == exec_start_addr, goto copy_section_done +.check_if_copy_section_done: + beq a1, a2, .copy_section_done // if offset != length, goto keep_copying +.keep_copying: + ld a3, 0(a0) // val = *load_addr + sd a3, 0(a1) // *exec_start_addr = val; + addi a0, a0, 8 // load_addr = load_addr + 8 + addi a1, a1, 8 // exec_start_addr = exec_start_addr + 8 + j .check_if_copy_section_done +.copy_section_done: + ret + + + +/*********************************************************************************** + * + * memfill() - fills memory, alternate to lib function when not available + */ + // config_copy helper function: + // a0 = dest + // a1 = value to fill + // a2 = length + .globl memfill + .type memfill, @function +memfill: + mv t1,a0 + mv t2,a1 + beqz a2,2f +1: + sb t2,0(t1) + addi a2,a2,-1 + addi t1,t1,1 + bnez a2,1b +2: + ret + +/*********************************************************************************** + * + * The following config_copy() symbol overrides the weak symbol in the HAL and does + * a safe copy of HW config data + */ + // config_copy helper function: + // a0 = dest + // a1 = src + // a2 = length + .globl config_copy + .type config_copy, @function +config_copy: + mv t1,a0 + beqz a2,2f +1: + lb t2,0(a1) + sb t2,0(t1) + addi a2,a2,-1 + addi t1,t1,1 + addi a1,a1,1 + bnez a2,1b +2: + ret + +/*********************************************************************************** + * + * config_32_copy () Copies a word at a time, used when copying to contigous registers + */ + // config_copy helper function: + // a0 = dest + // a1 = src + // a2 = length + .globl config_32_copy + .type config_32_copy, @function +config_32_copy: + mv t1,a0 + beqz a2,2f +1: + lw t2,0(a1) + sw t2,0(t1) + addi a2,a2,-4 + addi t1,t1,4 + addi a1,a1,4 + bnez a2,1b +2: + ret + + /*********************************************************************************** + * + * config_64_copy - copying using 64 bit loads, addresses must be on 64 bit boundary + */ + // config_copy helper function: + // a0 = dest + // a1 = src + // a2 = length + .globl config_64_copy + .type config_64_copy, @function +config_64_copy: + mv t1,a0 + beqz a2,2f +1: + ld t2,0(a1) + sd t2,0(t1) + addi a2,a2,-8 + addi t1,t1,8 + addi a1,a1,8 + bnez a2,1b +2: + ret + +/*********************************************************************************** + * + * The following copy_switch_code() symbol overrides the weak symbol in the HAL and does + * a safe copy of HW config data + */ + .globl copy_switch_code + .type copy_switch_code, @function +copy_switch_code: + la a5, __sc_start // a5 = __sc_start + la a4, __sc_load // a4 = __sc_load + beq a5,a4,.copy_switch_code_done // if a5 == a4, goto copy_switch_code_done + la a3, __sc_end // a3 = __sc_end + beq a5,a3,.copy_switch_code_done // if a5 == a3, goto copy_switch_code_done +.copy_switch_code_loop: + lw a2,0(a4) // a2 = *a4 + sw a2,0(a5) // *a5 = a2 + addi a5,a5,4 // a5+=4 + addi a4,a4,4 // a4+=4 + + bltu a5,a3,.copy_switch_code_loop // if a5 < a3, goto copy_switch_code_loop +.copy_switch_code_done: + ret /******************************************************************************* * */ +#define START__OF_LIM 0x08000000 +#define END__OF_LIM 0x08200000 +#define START__OF_DTM 0x01000000 +#define END__OF_DTM 0x01002000 + .clear_l2lim: // Clear the LIM @@ -371,3 +589,60 @@ restore_regs: blt a4, a5, 1b .done_clear: ret + +/* + * record_ecc_error_counts on reset + * These are non-zero in the coreplex. + * Can be checked later on to see if values have changed + * a0 = mECCDataFailCount save address + a1 = mECCDataCorrectionCount save address + a2 = mECCDirFixCount save address + */ +.record_ecc_error_counts: + # Store initial ECC errors + #define mECCDataFailCount 0x02010168U + la a5, mECCDataFailCount + mv a4, a0// eg. Use stat of DTIM in not used for anything else 0x01000100 + lw t2,0(a5) + sw t2,0(a4) + #define mECCDataCorrectionCount 0x02010148U + la a5, mECCDataCorrectionCount + mv a4, a1// eg. Use stat of DTIM in not used for anything else 0x01000110 + lw t2,0(a5) + sw t2,0(a4) + #define mECCDirFixCount 0x02010108u + la a5, mECCDirFixCount + mv a4, a2// eg. Use stat of DTIM in not used for anything else 0x01000120 + lw t2,0(a5) + sw t2,0(a4) + ret + +/* + * clear_ras , clear_ras_2_deep + * Two deep function calls. + * Used to clear the interal processor Return Address Stack + * This is belt and braces, may not be required + */ +.clear_ras: + mv a5, x1 + nop + call .clear_ras_2_deep + nop + nop + nop + nop + nop + nop + mv x1, a5 + ret + +.clear_ras_2_deep: + nop + nop + nop + nop + nop + nop + ret + + diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_mutex.S b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/mss_mutex.S similarity index 100% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/mss_mutex.S rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/mss_mutex.S diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/newlib_stubs.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c similarity index 99% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/newlib_stubs.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c index 267a8c9..e2ea215 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/newlib_stubs.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/newlib_stubs.c @@ -18,7 +18,7 @@ #include #include #include -#include "mss_hal.h" +#include "../mss_hal.h" /*============================================================================== * Redirection of standard output to a SmartFusion2 MSS UART. @@ -47,7 +47,7 @@ * MICROCHIP_STDIO_BAUD_RATE #define. */ #ifdef MICROCHIP_STDIO_THRU_UART -#include "drivers/mss_uart/mss_uart.h" +#include "drivers/mss_mmuart/mss_uart.h" #ifndef MICROCHIP_STDIO_BAUD_RATE #define MICROCHIP_STDIO_BAUD_RATE MSS_UART_115200_BAUD diff --git a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/system_startup.c b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup.c similarity index 88% rename from examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/system_startup.c rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup.c index d496d16..343fded 100644 --- a/examples/mss-rtc/mpfs-rtc-interrupt/src/platform/mpfs_hal/system_startup.c +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup.c @@ -29,9 +29,10 @@ */ #include #include -#include "mss_hal.h" +#include "../mss_hal.h" #ifdef MPFS_HAL_HW_CONFIG -#include "nwc/mss_nwc_init.h" +#include "../common/nwc/mss_nwc_init.h" +#include "system_startup_defs.h" #endif @@ -58,6 +59,8 @@ __attribute__((weak)) int main_first_hart(void) if(hartid == MPFS_HAL_FIRST_HART) { uint8_t hard_idx; + ptrdiff_t stack_top; + /* * We only use code within the conditional compile * #ifdef MPFS_HAL_HW_CONFIG @@ -91,13 +94,15 @@ __attribute__((weak)) int main_first_hart(void) * Copies text section if relocation required */ (void)copy_section(&__text_load, &__text_start, &__text_end); - #ifdef MPFS_HAL_HW_CONFIG /* * Start the other harts. They are put in wfi in entry.S * When debugging, harts are released from reset separately, * so we need to make sure hart is in wfi before we try and release. */ + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h0$); + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); + hls->in_wfi_indicator = HLS_MAIN_HART_STARTED; WFI_SM sm_check_thread = INIT_THREAD_PR; hard_idx = MPFS_HAL_FIRST_HART + 1U; while( hard_idx <= MPFS_HAL_LAST_HART) @@ -108,16 +113,29 @@ __attribute__((weak)) int main_first_hart(void) { default: case INIT_THREAD_PR: - hls = (HLS_DATA*)((uint8_t *)&__stack_bottom_h1$ - + (((uint8_t *)&__stack_top_h1$ - - (uint8_t *)&__stack_bottom_h1$) * hard_idx) - - (uint8_t *)(HLS_DEBUG_AREA_SIZE)); + + switch (hard_idx) + { + case 1: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h1$); + break; + case 2: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h2$); + break; + case 3: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h3$); + break; + case 4: + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h4$); + break; + } + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); sm_check_thread = CHECK_WFI; wait_count = 0U; break; case CHECK_WFI: - if( hls->in_wfi_indicator == HLS_DATA_IN_WFI ) + if( hls->in_wfi_indicator == HLS_OTHER_HART_IN_WFI ) { /* Separate state- to add a little delay */ sm_check_thread = SEND_WFI; @@ -131,7 +149,7 @@ __attribute__((weak)) int main_first_hart(void) break; case CHECK_WAKE: - if( hls->in_wfi_indicator == HLS_DATA_PASSED_WFI ) + if( hls->in_wfi_indicator == HLS_OTHER_HART_PASSED_WFI ) { sm_check_thread = INIT_THREAD_PR; hard_idx++; @@ -142,7 +160,7 @@ __attribute__((weak)) int main_first_hart(void) wait_count++; if(wait_count > 0x10U) { - if( hls->in_wfi_indicator == HLS_DATA_IN_WFI ) + if( hls->in_wfi_indicator == HLS_OTHER_HART_IN_WFI ) { raise_soft_interrupt(hard_idx); wait_count = 0UL; @@ -152,6 +170,9 @@ __attribute__((weak)) int main_first_hart(void) break; } } + stack_top = (ptrdiff_t)((uint8_t*)&__stack_top_h0$); + hls = (HLS_DATA*)(stack_top - HLS_DEBUG_AREA_SIZE); + hls->in_wfi_indicator = HLS_MAIN_HART_FIN_INIT; #endif /* MPFS_HAL_HW_CONFIG */ (void)main_other_hart(); @@ -359,66 +380,6 @@ __attribute__((weak)) void u54_4(void) park_hart(); } - /*============================================================================== - * Copy hardware configuration to registers. - * This function should be used in place of memcpy() to cover the use case - * where C library code has not yet been copied from its LMA to VMA. For - * example copying before the copy_section of the .text section has taken - * place. - */ - char * config_copy(void *dest, const void * src, size_t len) - { - char *csrc = (char *)src; - char *cdest = (char *)dest; - - for(uint32_t inc = 0; inc < len; inc++) - { - cdest[inc] = csrc[inc]; - } - - return(csrc); - } - - -/** - * copy_section - * @param p_load - * @param p_vma - * @param p_vma_end - */ -void copy_section -( - uint64_t * p_load, - uint64_t * p_vma, - uint64_t * p_vma_end) -{ - if ( p_vma != p_load) - { - while(p_vma < p_vma_end) - { - *p_vma = *p_load; - ++p_load; - ++p_vma; - } - } -} - -/** - * zero_section - * @param start - * @param end - */ -static void zero_section(uint64_t * start, uint64_t * end) -{ - uint64_t * p_zero = start; - - while(p_zero < end) - { - *p_zero = 0UL; - ++p_zero; - } -} - /*----------------------------------------------------------------------------- * _start() function called invoked * This function is called on power up and warm reset. @@ -431,6 +392,11 @@ static void zero_section(uint64_t * start, uint64_t * end) copy_section(&__sdata_load, &__sdata_start, &__sdata_end); copy_section(&__data_load, &__data_start, &__data_end); + + /* filling the lim as a test with identifiable content */ +#if 0 //todo: used during testing, remove + count_section(&__stack_top_h4$, &__l2lim_end, &__stack_top_h4$); +#endif copy_section(&__l2_scratchpad_load, &__l2_scratchpad_start, &__l2_scratchpad_end); zero_section(&__sbss_start, &__sbss_end); zero_section(&__bss_start, &__bss_end); @@ -456,6 +422,9 @@ __attribute__((weak)) uint8_t init_bus_error_unit(void) BEU->regs[hard_idx].ENABLE = (uint64_t)BEU_ENABLE; BEU->regs[hard_idx].PLIC_INT = (uint64_t)BEU_PLIC_INT; BEU->regs[hard_idx].LOCAL_INT = (uint64_t)BEU_LOCAL_INT; + BEU->regs[hard_idx].CAUSE = 0ULL; + BEU->regs[hard_idx].ACCRUED = 0ULL; + BEU->regs[hard_idx].VALUE = 0ULL; } #endif return (0U); diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/system_startup.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup.h similarity index 67% rename from examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/system_startup.h rename to examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup.h index 6c90e51..8691dc0 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/system_startup.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup.h @@ -37,8 +37,16 @@ typedef struct HLS_DATA_ /*------------------------------------------------------------------------------ * Symbols from the linker script used to locate the text, data and bss sections. */ +extern unsigned long __stack_top_h0$; +extern unsigned long __stack_bottom_h0$; extern unsigned long __stack_top_h1$; extern unsigned long __stack_bottom_h1$; +extern unsigned long __stack_top_h2$; +extern unsigned long __stack_bottom_h2$; +extern unsigned long __stack_top_h3$; +extern unsigned long __stack_bottom_h3$; +extern unsigned long __stack_top_h4$; +extern unsigned long __stack_bottom_h4$; extern unsigned long __data_load; extern unsigned long __data_start; @@ -58,6 +66,23 @@ extern unsigned long __text_load; extern unsigned long __text_start; extern unsigned long __text_end; +extern unsigned long __l2lim_end; + +extern unsigned long __e51itim_start; +extern unsigned long __e51itim_end; + +extern unsigned long __u54_1_itim_start; +extern unsigned long __u54_1_itim_end; + +extern unsigned long __u54_2_itim_start; +extern unsigned long __u54_2_itim_end; + +extern unsigned long __u54_3_itim_start; +extern unsigned long __u54_3_itim_end; + +extern unsigned long __u54_4_itim_start; +extern unsigned long __u54_4_itim_end; + /* * Function Declarations */ @@ -72,15 +97,31 @@ void init_memory( void); uint8_t init_mem_protection_unit(void); uint8_t init_pmp(uint8_t hart_id); uint8_t init_bus_error_unit( void); +char * memfill(void *dest, const void * src, size_t len); char * config_copy(void *dest, const void * src, size_t len); +char * config_32_copy(void *dest, const void * src, size_t len); +char * config_64_copy(void *dest, const void * src, size_t len); + void copy_section ( uint64_t * p_load, uint64_t * p_vma, uint64_t * p_vma_end ); +void zero_section +( + uint64_t *__sbss_start, + uint64_t * __sbss_end +); void load_virtual_rom(void); +void count_section +( + uint64_t * start_address, + uint64_t * end_address, + uint64_t * start_value +); + #ifdef __cplusplus } #endif diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h new file mode 100644 index 0000000..9ad2051 --- /dev/null +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/mpfs_hal/startup_gcc/system_startup_defs.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. + * + * SPDX-License-Identifier: MIT + * + * MPFS HAL Embedded Software + * +*/ + +/****************************************************************************** + * @file system_startup_defs.h + * @author Microchip-FPGA Embedded Systems Solutions + * @brief Defines for the system_startup_defs.c + */ + +#ifndef SYSTEM_STARTUP_DEFS_H +#define SYSTEM_STARTUP_DESF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Markers used to indicate startup status of hart + */ +#define HLS_MAIN_HART_STARTED 0x12344321U +#define HLS_MAIN_HART_FIN_INIT 0x55555555U +#define HLS_OTHER_HART_IN_WFI 0x12345678U +#define HLS_OTHER_HART_PASSED_WFI 0x87654321U + +/*------------------------------------------------------------------------------ + * Define the size of the HLS used + * In our HAL, we are using Hart Local storage for debug data storage only + * as well as flags for wfi instruction management. + * The TLS will take memory from top of the stack if allocated + * + */ +#if !defined (HLS_DEBUG_AREA_SIZE) +#define HLS_DEBUG_AREA_SIZE 64 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STARTUP_H */ diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld index 7613092..870f719 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-ddr-e51.ld @@ -131,11 +131,11 @@ HEAP_SIZE = 0k; /* needs to be calculated for your appli * These are the stack sizes that will be allocated to each hart before starting * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). */ -STACK_SIZE_E51_APPLICATION = 1k; -STACK_SIZE_U54_1_APPLICATION = 1k; -STACK_SIZE_U54_2_APPLICATION = 1k; -STACK_SIZE_U54_3_APPLICATION = 1k; -STACK_SIZE_U54_4_APPLICATION = 1k; +STACK_SIZE_E51_APPLICATION = 8k; +STACK_SIZE_U54_1_APPLICATION = 8k; +STACK_SIZE_U54_2_APPLICATION = 8k; +STACK_SIZE_U54_3_APPLICATION = 8k; +STACK_SIZE_U54_4_APPLICATION = 8k; /* reset address 0xC0000000 */ SECTION_START_ADDRESS = 0x80000000; @@ -166,6 +166,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -184,6 +185,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } > DDR_CACHED @@ -226,22 +231,11 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } > DDR_CACHED - - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > DDR_CACHED - + /* data section */ .data : ALIGN(0x10) { @@ -321,5 +315,13 @@ SECTIONS PROVIDE(__stack_top_h4$ = .); } > DDR_CACHED + + /* must be on 4k boundary- corresponds to page size */ + .free_lim : ALIGN(0x1000) + { + /* place __start_of_free_lim$ after last allocation of l2_lim */ + . = ALIGN(0x10); + PROVIDE(__start_of_free_lim$ = .); + } > DDR_CACHED } diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-dtim.ld b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-dtim.ld index 9429d04..b3ba45f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-dtim.ld +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-dtim.ld @@ -95,7 +95,7 @@ See mpfs-lim.ld example linker script when runing from LIM. MEMORY { - eNVM (rx) : ORIGIN = 0x20230000, LENGTH = 56k + eNVM (rx) : ORIGIN = 0x20220000, LENGTH = 64k ram_LIM (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k ram (rwx) : ORIGIN = 0x01000000, LENGTH = 8k scratchpad(rwx): ORIGIN = 0x0A000000, LENGTH = 512k @@ -154,6 +154,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -172,6 +173,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } > ram @@ -214,22 +219,11 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } > ram - - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > ram - + /* data section */ .data : ALIGN(0x10) { diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-envm.ld b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-envm.ld index ee898eb..6a84f8f 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-envm.ld +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-envm.ld @@ -100,7 +100,7 @@ MEMORY /* eNVM can be made into 128K section or split as required */ /* In this example, our reset vector is set to point to the */ /* start of SEC2 at 0x20220000. */ - eNVM_SEC_2_0_1_3 (rx) : ORIGIN = 0x20220000, LENGTH = 120k + eNVM_SEC_2_0_1_3 (rx) : ORIGIN = 0x20220000, LENGTH = 128k ram_LIM (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k ram_dtm (rwx) : ORIGIN = 0x01000000, LENGTH = 7k /* DTIM */ scratchpad(rwx): ORIGIN = 0x0A000000, LENGTH = 512k @@ -165,6 +165,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -183,6 +184,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } > eNVM_SEC_2_0_1_3 @@ -244,22 +249,11 @@ SECTIONS /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } > ram_LIM AT > eNVM_SEC_2_0_1_3 - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > ram_LIM - /* data section */ .data : ALIGN(0x10) { @@ -340,6 +334,9 @@ SECTIONS . += STACK_SIZE_U54_4_APPLICATION; PROVIDE(__app_stack_top_h4 = .); PROVIDE(__stack_top_h4$ = .); + /* place __start_of_free_lim$ after last allocation of l2_lim */ + . = ALIGN(0x10); + PROVIDE(__start_of_free_lim$ = .); } > ram_LIM } diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld index 0e96f29..39fbc58 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim-lma-scratchpad-vma.ld @@ -117,7 +117,17 @@ HEAP_SIZE = 8k; /* needs to be calculated for your appli /* TLS hart 1 */ /* etc */ /* note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ -STACK_SIZE_PER_HART = 1k; + +/* + * Stack size for each hart's application. + * These are the stack sizes that will be allocated to each hart before starting + * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). + */ +STACK_SIZE_E51_APPLICATION = 8k; +STACK_SIZE_U54_1_APPLICATION = 8k; +STACK_SIZE_U54_2_APPLICATION = 8k; +STACK_SIZE_U54_3_APPLICATION = 8k; +STACK_SIZE_U54_4_APPLICATION = 8k; SECTIONS @@ -131,6 +141,7 @@ SECTIONS *mss_h2f.o (.text .text* .rodata .rodata* .srodata*) *mss_l2_cache.o (.text .text* .rodata .rodata* .srodata*) *mss_mpu.o (.text .text* .rodata .rodata* .srodata*) + *mss_pmp.o (.text .text* .rodata .rodata* .srodata*) *mss_mutex.o (.text .text* .rodata .rodata* .srodata*) *mss_stubs.o (.text .text* .rodata .rodata* .srodata*) *mss_util.o (.text .text* .rodata .rodata* .srodata*) @@ -164,6 +175,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -182,6 +194,10 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; } >scratchpad AT> l2_lim @@ -204,22 +220,11 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; } >scratchpad AT> l2_lim - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > scratchpad - /* data section */ .data : ALIGN(0x10) { @@ -270,23 +275,33 @@ SECTIONS .stack : ALIGN(0x1000) { PROVIDE(__stack_bottom_h0$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h0 = .); + . += STACK_SIZE_E51_APPLICATION; + PROVIDE(__app_stack_top_h0 = .); PROVIDE(__stack_top_h0$ = .); PROVIDE(__stack_bottom_h1$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h1$ = .); + . += STACK_SIZE_U54_1_APPLICATION; + PROVIDE(__app_stack_top_h1 = .); PROVIDE(__stack_top_h1$ = .); PROVIDE(__stack_bottom_h2$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h2 = .); + . += STACK_SIZE_U54_2_APPLICATION; + PROVIDE(__app_stack_top_h2 = .); PROVIDE(__stack_top_h2$ = .); PROVIDE(__stack_bottom_h3$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h3 = .); + . += STACK_SIZE_U54_3_APPLICATION; + PROVIDE(__app_stack_top_h3 = .); PROVIDE(__stack_top_h3$ = .); PROVIDE(__stack_bottom_h4$ = .); - . += STACK_SIZE_PER_HART; + PROVIDE(__app_stack_bottom_h4 = .); + . += STACK_SIZE_U54_4_APPLICATION; + PROVIDE(__app_stack_top_h4 = .); PROVIDE(__stack_top_h4$ = .); } > l2_lim @@ -307,8 +322,10 @@ SECTIONS *(.ram_coderodata*) . = ALIGN (4); __sc_end = .; + /* place __start_of_free_lim$ after last allocation of l2_lim */ + PROVIDE(__start_of_free_lim$ = .); } >switch_code AT> l2_lim /* On the MPFS for startup code use, >switch_code AT>eNVM */ - + } diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim.ld b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim.ld index 8693161..7f9918a 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim.ld +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/linker/mpfs-lim.ld @@ -95,18 +95,17 @@ See mpfs-lim.ld example linker script when runing from LIM. MEMORY { - /* eNVM can be made into 128K section or split as required */ - /* In this example, our reset vector is set to point to the */ - /* start of SEC0 at 0x20222000. The initial 8K is reserved for data - /* storage in this example */ - eNVM_SEC2 (rx) : ORIGIN = 0x20220000, LENGTH = 8k - eNVM_SEC0_1_3 (rx) : ORIGIN = 0x20222000, LENGTH = 120k - /* LIM - we place code here in this example */ - ram (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k - ram_DTIM (rwx) : ORIGIN = 0x01000000, LENGTH = 7k - scratchpad(rwx): ORIGIN = 0x0A000000, LENGTH = 512k - /* This 1k of DTIM is used to run code when switching the eNVM clock */ - switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k + envm (rx) : ORIGIN = 0x20220000, LENGTH = 128k + dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k + switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k + e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k + u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k + u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k + u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k + u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k + l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k + l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k + ddr (rwx) : ORIGIN = 0x80000000, LENGTH = 1024m } HEAP_SIZE = 8k; /* needs to be calculated for your application if using */ @@ -123,24 +122,44 @@ HEAP_SIZE = 8k; /* needs to be calculated for your appli /* TLS hart 1 */ /* etc */ /* note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */ -/* STACK_SIZE_PER_HART = 1k; */ +/* STACK_SIZE_PER_HART = 8k; */ /* * Stack size for each hart's application. * These are the stack sizes that will be allocated to each hart before starting * each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4(). */ -STACK_SIZE_E51_APPLICATION = 1k; -STACK_SIZE_U54_1_APPLICATION = 1k; -STACK_SIZE_U54_2_APPLICATION = 1k; -STACK_SIZE_U54_3_APPLICATION = 1k; -STACK_SIZE_U54_4_APPLICATION = 1k; +STACK_SIZE_E51_APPLICATION = 8k; +STACK_SIZE_U54_1_APPLICATION = 8k; +STACK_SIZE_U54_2_APPLICATION = 8k; +STACK_SIZE_U54_3_APPLICATION = 8k; +STACK_SIZE_U54_4_APPLICATION = 8k; SECTIONS { + PROVIDE(__envm_start = ORIGIN(envm)); + PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); + PROVIDE(__l2lim_start = ORIGIN(l2lim)); + PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); + PROVIDE(__ddr_start = ORIGIN(ddr)); + PROVIDE(__ddr_end = ORIGIN(ddr) + LENGTH(ddr)); + PROVIDE(__dtim_start = ORIGIN(dtim)); + PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); + PROVIDE(__e51itim_start = ORIGIN(e51_itim)); + PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); + PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); + PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); + PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); + PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); + PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); + PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); + PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); + PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); + PROVIDE(__l2lim_start = ORIGIN(l2lim)); + PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); -/* text: test code section */ - . = 0x08000000; + /* text: text code section */ + . = __l2lim_start; .text : ALIGN(0x10) { __text_load = LOADADDR(.text); @@ -161,6 +180,7 @@ SECTIONS KEEP (*crtend.o(.dtors)) *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) *(.gcc_except_table) *(.eh_frame_hdr) *(.eh_frame) @@ -179,12 +199,18 @@ SECTIONS KEEP (*(.fini_array)) KEEP (*(SORT(.fini_array.*))) PROVIDE_HIDDEN (__fini_array_end = .); + + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + . = ALIGN(0x10); __text_end = .; - } > ram + . = ALIGN(0x10); + } > l2lim .l2_scratchpad : ALIGN(0x10) { + . = ALIGN (0x10); __l2_scratchpad_load = LOADADDR(.l2_scratchpad); __l2_scratchpad_start = .; __l2_scratchpad_vma_start = .; @@ -192,7 +218,7 @@ SECTIONS . = ALIGN(0x10); __l2_scratchpad_end = .; __l2_scratchpad_vma_end = .; - } >scratchpad AT> ram + } >l2zerodevice AT> l2lim /* * The .ram_code section will contain the code That is run from RAM. @@ -211,7 +237,7 @@ SECTIONS *(.ram_coderodata*) . = ALIGN (4); __sc_end = .; - } >switch_code AT> ram /* On the MPFS for startup code use, >switch_code AT>eNVM */ + } >switch_code AT> l2lim /* On the MPFS for startup code use, >switch_code AT>eNVM */ /* short/global data section */ .sdata : ALIGN(0x10) @@ -221,21 +247,10 @@ SECTIONS /* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */ /* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */ __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(0x10); __sdata_end = .; - } > ram - - /* - * The s2data section is required when using cetrtain versions of newlib-nano - * The _global_impure_ptr used in that libary is initialised to point here. - */ - .sdata2 : ALIGN(0x10) - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } > ram + } > l2lim /* data section */ .data : ALIGN(0x10) @@ -247,7 +262,7 @@ SECTIONS *(.data .data.* .gnu.linkonce.d.*) . = ALIGN(0x10); __data_end = .; - } > ram + } > l2lim /* sbss section */ .sbss : ALIGN(0x10) @@ -257,7 +272,7 @@ SECTIONS *(.scommon) . = ALIGN(0x10); __sbss_end = .; - } > ram + } > l2lim /* sbss section */ .bss : ALIGN(0x10) @@ -268,7 +283,7 @@ SECTIONS *(COMMON) . = ALIGN(0x10); __bss_end = .; - } > ram + } > l2lim /* End of uninitialized data segment */ _end = .; @@ -280,7 +295,7 @@ SECTIONS __heap_end = .; . = ALIGN(0x10); _heap_end = __heap_end; - } > ram + } > l2lim /* must be on 4k boundary- corresponds to page size */ .stack : ALIGN(0x1000) @@ -314,7 +329,11 @@ SECTIONS . += STACK_SIZE_U54_4_APPLICATION; PROVIDE(__app_stack_top_h4 = .); PROVIDE(__stack_top_h4$ = .); - - } > ram + /* place __start_of_free_lim$ after last allocation of l2_lim */ + . = ALIGN(0x10); + PROVIDE(__start_of_free_lim$ = .); + } > l2lim + + } diff --git a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h index cf7e2fb..4e794bc 100644 --- a/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h +++ b/examples/mss-rtc/mpfs-rtc-time/src/platform/platform_config_reference/mpfs_hal_config/mss_sw_config.h @@ -117,8 +117,8 @@ /* * If not using item, comment out line below */ -//#define SGMII_SUPPORT -//#define DDR_SUPPORT +#define SGMII_SUPPORT +#define DDR_SUPPORT #define MSSIO_SUPPORT //#define SIMULATION_TEST_FEEDBACK //#define E51_ENTER_SLEEP_STATE