[destination] ← <literal>.[destination]
ANDI #<data>,<ea>
Size
byte, word, longword
AND the immediate data to the destination operand. The ANDI
permits a literal operand to be ANDed with a destination other than a data register. For example, ANDI #$FE00,$1234
or ANDI.B #$F0,(A2)+
.
X | N | Z | V | C |
---|---|---|---|---|
- | * | * | 0 | 0 |
Dn | An | (An) | (An)+ | ‑(An) | (d,An) | (d,An,Xi) | ABS.W | ABS.L | (d,PC) | (d,PC,Xn) | imm |
---|---|---|---|---|---|---|---|---|---|---|---|
✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
[CCR] ← <data>.[CCR]
ANDI #<data>,CCR
Size
byte
AND the immediate data to the condition code register (i.e., the least-significant byte of the status register).
ANDI
is used to clear selected bits of the CCR
. For example, ANDI #$FA,CCR
clears the Z- and C-bits, i.e., XNZVC = X N 0 V 0.
X | N | Z | V | C |
---|---|---|---|---|
* | * | * | * | * |
- X: cleared if bit 4 of data is zero
- N: cleared if bit 3 of data is zero
- Z: cleared if bit 2 of data is zero
- V: cleared if bit 1 of data is zero
- C: cleared if bit 0 of data is zero
IF [S] = 1
THEN
[SR] ← <literal>.[SR]
ELSE TRAP
ANDI #<data>,SR
Size
word
AND the immediate data to the status register and store the result in the status register. All bits of the SR are affected.
This instruction is used to clear the interrupt mask, the S-bit, and the T-bit of the SR. ANDI #<data>,SR
affects both the status byte of the SR and the CCR. For example, ANDI #$7FFF,SR
clears the trace bit of the status register, while ANDI #$7FFE,SR
clears the trace bit and also clears the carry bit of the CCR.
X | N | Z | V | C |
---|---|---|---|---|
* | * | * | * | * |
From MOTOROLA M68000 FAMILY Programmer's reference manual. Copyright 1992 by Motorola Inc./NXP. Adapted with permission.